Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 17-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on March 20, 2026.
Newly submitted claims 16-20 directed to an invention that is independent or distinct from the invention originally claimed for the following reasons: the newly submitted claim is directed to an independent invention of manufacturing the silicon carbide semiconductor device.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 16-20 withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kono et al. (US 20170271437 A1) and Kawano et al. (US 20030075759 A1).
Regarding claim 1, Kono et al. disclose a silicon carbide semiconductor device (100) comprising:
a drift layer (26) of a first conductivity-type including silicon carbide (paragraph 17, Fig. 1);
a base region (28) of a second conductivity-type including silicon carbide provided on a top surface side of the drift layer (paragraph 18, Fig. 1);
a main region (30a, 30b) of the first conductivity-type including silicon carbide provided on a top surface side of the base region (28, Fig. 1);
a gate insulating film (16a, 16b) provided inside a trench (22a, 22b) penetrating the main region (30a, 30b) and the base region (28);
a gate electrode (18a, 18b) buried inside the trench with the gate insulating film interposed (Fig. 1); and
a main electrode (12) provided in contact with the main region (30a, 30b), wherein the main region includes
a first region (30a, 30b, first region is the same as main region, Fig. 1) with a bottom surface in contact with the base region (28).
Kono et al. disclose a 3C structure can be used for SiC crystal structures (paragraph 127). However, Kono does not disclose a second region including a 3C structure and provided at an upper part of the first region separately from the gate insulating film inside the trench so as to be in contact with the main electrode.
However, Kawano et al. disclose a second region (4a, Fig. 1) provided at an upper part of the first region (4) separately from the gate insulating film (7) inside the trench so as to be in contact with the main electrode (S). (Fig. 1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kono et al. in view of Kawano et al. such that a second region including a 3C structure and provided at an upper part of the first region separately from the gate insulating film inside the trench so as to be in contact with the main electrode. Doing so would improve ohmic contact and enhance reliability.
Regarding claim 3, Kono and Kawano are discussed above. Kono et al. does not disclose second region includes phosphorus or arsenic.
However, Kawano et al. disclose second region includes phosphorus or arsenic (paragraph 59).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kono et al. in view of Kawano et al. such that a second region includes phosphorus or arsenic. Doing so would increase conductivity.
Regarding claim 11, Kono is discussed above. Kono does not disclose a top surface of the gate electrode is located at a position shallower than a depth of the second region from a top surface.
However, Kawano discloses a top surface of the gate electrode (top surface of 6, Fig. 1) is located at a position shallower than a depth of the second region (4a) from a top surface (Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kono et al. in view of Kawano et al. such that the gate electrode is located at a position shallower than a depth of the second region from a top surface. Doing so would reduce on-resistance and enhance switching speed.
Regarding claim 12, Kono discloses a base contact region (28) of the second conductivity-type including silicon carbide provided on the top surface side of the base region (paragraph 18, implied silicon carbide is in the region and can be on the top surface) so as to be in contact with the main region (30a, 30b) (Fig. 1).
Regarding claim 13, Kono is discussed above. Kono does not disclose the second region is separated from the base contact region.
However, Kawano discloses the second region (4a) is separated from the base contact region (3, Fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kono et al. in view of Kawano et al. such that the second region is separated from the base contact region. Doing so would optimize electrical contact and high-voltage performance.
Regarding claim 14, Kono discloses the first region (30a) has an impurity concentration in a range of 1 x 1016 cm-3 or greater and 1 x 1019 cm-3 or less (paragraph 34).
Regarding claim 15, Kono discloses the first region (30a) includes nitrogen or phosphorus (paragraph 33, contains phosphorus).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kono et al. (US 20170271437 A1) and Kawano et al. (US 20030075759 A1) as applied to claim 1 above, in further view of Ohashi et al. (US 20200091295 A1).
Regarding claim 2, Kono and Kawano are discussed above. Kawano discloses a second region (4A, Fig. 1).
However, neither reference discloses a proportion of the 3C structure included in the second region is 10% or higher.
On the other hand, Ohashi et al. discloses a proportion of the 3C structure (3C is n-type) included in the second region is 10% or higher (paragraph 63).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kono and Kawano in view of Ohashi et al. such that a proportion of the 3C structure included in the second region is 10% or higher. Doing so would reduce ohmic contact resistance.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kono et al. (US 20170271437 A1) and Kawano et al. (US 20030075759 A1) as applied to claim 1 above, in further view of Burke et al. (US 8648412 B1).
Regarding claim 4, Kono and Kawano are discussed above. Neither reference disclose the second region includes an inactive element.
However, Kawano discloses a second region (4a, Fig. 1).
On the other hand, Burke et al. disclose a region can be formed as a result of argon (inactive element) implantation (paragraph 34).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kono et al. and Kawano et al. in view of Burke et al. such that the second region includes an inactive element. Doing so would stabilize the surface during high-temperature treatments and minimize unintended contamination.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kono et al. (US 20170271437 A1) and Kawano et al. (US 20030075759 A1) as applied to claim 1 above, in further view of Tanaka et al. (US 20160336391 A1).
Regarding claim 5, Kono and Kawano are discussed above. Neither references disclose the second region has an impurity concentration in a range of 1 x 1019 cm-3 or greater and 1 x 1022cm-3 or less.
However, Tanaka et al. disclose the second region (n-type impurity concentration region) has an impurity concentration in a range of 1 x 1019 cm-3 or greater and 1 x 1022cm-3 or less (paragraph 40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kono et al. and Kawano et al. in view of Tanaka et al. such that the second region has an impurity concentration in a range of 1 x 1019 cm-3 or greater and 1 x 1022cm-3 or less. Doing so would enable ohmic contact regions to ensure low resistivity and efficient current transport.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kono et al. (US 20170271437 A1) and Kawano et al. (US 20030075759 A1) as applied to claim 1 above, in further view of Saito et al. (US 20080017897 A1).
Regarding claim 7, Kono and Kawano are discussed above. Neither reference discloses the second region has a width in a range of 300 nanometers or greater and 500 nanometers or smaller.
However, Saito et al. disclose the second region (source contact region) has a width 4 micrometers (paragraph 120). A prima facie case of obviousness exists where the claimed range and prior art ranges do not overlap, but are close enough that one skilled in the art would have been expected them to have the same properties (Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kono et al. and Kawano et al. in view of Saito et al. such that the second region has a width in a range of 300 nanometers or greater and 500 nanometers or smaller. Doing so would balance on-state resistance, leakage current, and manufacturing tolerances.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kono et al. (US 20170271437 A1) and Kawano et al. (US 20030075759 A1) as applied to claim 1 above, in further view of Gotoh (US 20170200788 A1).
Regarding claim 8, Kono and Kawano are discussed above. Neither reference discloses the second region has a depth from a top surface set in a range of 30 nanometers or greater and 100 nanometers or smaller.
However, Gotoh discloses the second region (4, source contact region is the same as second region in the Claim) has a depth from a top surface set in a range of 400 nanometers or greater and 600 nanometers or smaller. A prima facie case of obviousness exists where the claimed range and prior art ranges do not overlap, but are close enough that one skilled in the art would have been expected them to have the same properties (Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kono et al. and Kawano et al. in view of Gotoh et al. such that the second region has a depth from a top surface set in a range of 30 nanometers or greater and 100 nanometers or smaller. Doing so would optimize the balance between low on-resistance and high reliability.
Claims 6, 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kono et al. (US 20170271437 A1) and Kawano et al. (US 20030075759 A1) as applied to claim 1 above, in further view of Yamamoto et al. (US 20120061682 A1).
Regarding claim 6, Kono and Kawano are discussed above. Kawano discloses the first region (4) interposed between the second region (4a).
However, neither reference discloses the gate insulating film has a width of 100 nanometer or greater.
However, Yamamoto et al. discloses gate insulating film (7) has a width of 100 nanometer or greater (paragraph 31).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kono et al. and Kawano et al. in view of Yamamoto such that the gate insulating film has a width of 100 nanometer or greater. Doing so would ensure long-term reliability, reduce electric field stress in the dielectric, and prevent premature dielectric breakdown.
Regarding claim 9, Kono and Kawano are discussed above. Kawano discloses a first region (4) and second region (4a), and an end part of the second region toward the gate electrode is shifted from an end part of the contact hole toward the gate electrode. Rearrangement of the second region toward the gate electrode is within skill level of one in the art. In re Japikse, 181 F.2d 1019, 86 USPQ70 (CCPA 1950).
Neither reference discloses an interlayer insulating film provided on top surfaces of the gate electrode and the first region and having a contact hole to which at least a part of the second region is exposed.
However, Yamamoto discloses an interlayer insulating film (7) provided on top surfaces of the gate electrode (8) and the first region (4a) and having a contact hole to which at least a part of the second region (4b) is exposed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kono et al. and Kawano et al. in view of Yamamoto such that an interlayer insulating film provided on top surfaces of the gate electrode and the first region and having a contact hole to which at least a part of the second region is exposed, wherein an end part of the second region toward the gate electrode is shifted from an end part of the contact hole toward the gate electrode. Doing so would improve device reliability and performance and managing parasitic capacitance.
Regarding claim 10, Kono and Kawano are discussed above. Kawano discloses an end part of the second region (4a) toward the gate electrode conforms to a position of an end part of the contact hole. Rearrangement of the second region toward the gate electrode so that it conforms to position of an end part of the contact hole is within the routine skill level of one in the art. In re Japikse, 181 F.2d 1019, 86 USPQ70 (CCPA 1950).
Neither reference discloses an interlayer insulating film provided on top surfaces of the gate electrode and the first region and having a contact hole to which at least a part of the second region is exposed
However, Yamamoto discloses an interlayer insulating film (7) provided on top surfaces of the gate electrode (8) and the first region (4a) and having a contact hole to which at least a part of the second region (4b) is exposed (Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kono et al. and Kawano et al. in view of Yamamoto such that an end part of the second region toward the gate electrode conforms to a position of an end part of the contact hole. Doing so would enhance performance and reliability of the device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVE PHAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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