Prosecution Insights
Last updated: April 19, 2026
Application No. 18/519,844

SYSTEMS AND METHODS FOR EXPLOITING QUEUES AND TRANSITIONAL STORAGE FOR IMPROVED LOW-LATENCY HIGH-BANDWIDTH ON-DIE DATA RETRIEVAL

Final Rejection §DP
Filed
Nov 27, 2023
Examiner
FRANKLIN, RICHARD B
Art Unit
2181
Tech Center
2100 — Computer Architecture & Software
Assignee
Intel Corporation
OA Round
6 (Final)
84%
Grant Probability
Favorable
7-8
OA Rounds
2y 7m
To Grant
84%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
531 granted / 636 resolved
+28.5% vs TC avg
Minimal +1% lift
Without
With
+0.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
20 currently pending
Career history
656
Total Applications
across all art units

Statute-Specific Performance

§101
6.1%
-33.9% vs TC avg
§103
45.4%
+5.4% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
11.6%
-28.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 636 resolved cases

Office Action

§DP
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 21, 25, 41, 45, 46, and 50 are pending. Response to Arguments Applicant’s amendment filed 09 March 2026 overcomes the rejections set forth under 35 U.S.C. 112(b) and the claim objections set forth in the previous office action. Applicant has not addressed the non-statutory double patenting rejection set forth in the previous office action in such a way which would remove the rejection. Therefore, the non-statutory double patenting rejection set forth in the previous office action is maintained in the instant office action. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 21, 25, 41, 45, 46, and 50 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 7 and 15 – 20 of U.S. Patent No. 11,869,113. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent require all the limitation of the claims of the instant application. Claims 21, 25, 41, 45, 46, and 50 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 7 and 15 – 20 of U.S. Patent No. 11,227,358. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent require all the limitation of the claims of the instant application. Allowable Subject Matter Claims 21, 25, 41, 45, 46, and 50 would be allowable if rewritten, amended, and/or a proper terminal disclaimer is filed to overcome the non-statutory double patenting rejection(s) set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: Claims 21 and 25 would be allowable if rewritten, amended, and/or a proper terminal disclaimer is filed to overcome the non-statutory double patenting rejection(s) set forth in this Office action because the prior art of record fails to teach alone or in combination logic on-die or on chip with the queue or transitional buffer, the logic is configured to cause the request of the at least one processing resource to be transferred to the queue or transitional buffer for temporary storage instead of transferring the request to off-chip memory when the queue or transitional buffer has a predetermined amount of storage capacity, where the request is transferred to the queue or transitional buffer without being processed instead of being transferred to the off-chip memory when the queue or the transitional buffer has the predetermined amount of storage capacity that is greater than a threshold level, wherein the logic is further configured to transfer the request to one or more of a different queue, a different transitional buffer, or a next level of memory when the queue or transitional buffer lacks the predetermined amount of storage capacity, wherein the logic is further configured to determine whether the queue or transitional buffer has the predetermined amount of storage capacity including greater than a threshold level of storage capacity, as required by independent claim 21, in combination with the other claimed limitations (emphasis added). Applicant has accurately described the differences between the prior art of record and the claimed invention in the remarks filed 20 November 2025. Specifically, the prior art of record teaches transferring the request to a queue or transitional buffer when the queue or transitional buffer has a predetermined amount of memory (US Patent No. 6,900,812; Col 11 Lines 1 – 6, Col 11 Line 64 – Col 12 Line 6), but does not teach the limitations of not transferring the request to an off chip memory when the queue has a greater than a threshold amount of memory. The prior art of record fails to teach the specific arrangement of elements and specific conditional request movements required by independent claim 21. Claim 25 would also be allowable because of its dependence upon allowable independent claim 21. Claims 41 and 45 would be allowable if rewritten, amended, and/or a proper terminal disclaimer is filed to overcome the non-statutory double patenting rejection(s) set forth in this Office action because the prior art of record fails to teach alone or in combination causing, by logic associated with processing circuitry of a computing device, a request associated with at least one processing resource to be transferred to a queue or transitional buffer for temporary storage instead of transferring the request to off-chip memory when the queue or transitional buffer has a predetermined amount of storage capacity, wherein the request is transferred to the queue or transitional buffer without being processed instead of being transferred to the off-chip memory when the queue or the transitional buffer has the predetermined amount of storage capacity that is greater than a threshold level; transferring the request to one or more of a different queue, a different transitional buffer, or a next level of memory when the queue or transitional buffer lacks the predetermined amount of storage capacity; and determining whether the queue or transitional buffer has the predetermined amount of storage capacity including greater than a threshold level of storage capacity, as required by independent claim 41, in combination with the other claimed limitations (emphasis added). Applicant has accurately described the differences between the prior art of record and the claimed invention in the remarks filed 20 November 2025. Specifically, the prior art of record teaches transferring the request to a queue or transitional buffer when the queue or transitional buffer has a predetermined amount of memory (US Patent No. 6,900,812; Col 11 Lines 1 – 6, Col 11 Line 64 – Col 12 Line 6), but does not teach the limitations of not transferring the request to an off chip memory when the queue has a greater than a threshold amount of memory. The prior art of record fails to teach the specific arrangement of elements and specific conditional request movements required by independent claim 41. Claim 45 would also be allowable because of its dependence upon allowable independent claim 41. Claims 46 and 50 would be allowable if rewritten, amended, and/or a proper terminal disclaimer is filed to overcome the non-statutory double patenting rejection(s) set forth in this Office action because the prior art of record fails to teach alone or in combination causing, by logic associated with processing circuitry of the computing device, a request associated with at least one processing resource to be transferred to a queue or transitional buffer for temporary storage instead of transferring the request to off-chip memory when the queue or transitional buffer has a predetermined amount of storage capacity, wherein the request is transferred to the queue or transitional buffer without being processed instead of being transferred to the off-chip memory when the queue or the transitional buffer has the predetermined amount of storage capacity that is greater than a threshold level; transferring the request to one or more of a different queue, a different transitional buffer, or a next level of memory when the queue or transitional buffer lacks the predetermined amount of storage capacity; and determining whether the queue or transitional buffer has the predetermined amount of storage capacity including greater than a threshold level of storage capacity, as required by independent claim 46, in combination with the other claimed limitations (emphasis added). Applicant has accurately described the differences between the prior art of record and the claimed invention in the remarks filed 20 November 2025. Specifically, the prior art of record teaches transferring the request to a queue or transitional buffer when the queue or transitional buffer has a predetermined amount of memory (US Patent No. 6,900,812; Col 11 Lines 1 – 6, Col 11 Line 64 – Col 12 Line 6), but does not teach the limitations of not transferring the request to an off chip memory when the queue has a greater than a threshold amount of memory. The prior art of record fails to teach the specific arrangement of elements and specific conditional request movements required by independent claim 46. Claim 50 would also be allowable because of its dependence upon allowable independent claim 46. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RICHARD B FRANKLIN/Examiner, Art Unit 2181 /IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
Read full office action

Prosecution Timeline

Nov 27, 2023
Application Filed
Feb 09, 2024
Response after Non-Final Action
Oct 17, 2024
Non-Final Rejection — §DP
Jan 13, 2025
Response Filed
Jan 22, 2025
Final Rejection — §DP
Feb 14, 2025
Response after Non-Final Action
Apr 03, 2025
Request for Continued Examination
Apr 12, 2025
Response after Non-Final Action
Apr 17, 2025
Non-Final Rejection — §DP
Jul 18, 2025
Response Filed
Jul 30, 2025
Final Rejection — §DP
Sep 22, 2025
Response after Non-Final Action
Nov 20, 2025
Request for Continued Examination
Dec 01, 2025
Response after Non-Final Action
Dec 05, 2025
Non-Final Rejection — §DP
Mar 09, 2026
Response Filed
Apr 03, 2026
Final Rejection — §DP (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

7-8
Expected OA Rounds
84%
Grant Probability
84%
With Interview (+0.8%)
2y 7m
Median Time to Grant
High
PTA Risk
Based on 636 resolved cases by this examiner. Grant probability derived from career allow rate.

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