DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2020/0357821, cited by applicant) in view of Ling et al. (US 2022/0285394, cited by applicant).
Regarding claim 17, Chen teaches a method comprising: forming a memory cell in a recess, including: forming a semiconductor material in the recess; forming a dielectric material adjacent the semiconductor material; forming a charge storage material adjacent the dielectric material; forming a ferroelectric material adjacent the charge storage material; and forming a conductive material in adjacent the dielectric material (figs. 4a-4l, the abstract and claim 23).
Chen fails to teach forming levels of first dielectric materials interleaved with levels of second dielectric materials; forming an opening through the levels of first dielectric materials and the levels of second dielectric materials to expose, at the opening, a portion of a level of dielectric material among the levels of first dielectric materials of the levels of second dielectric materials.
However, Ling teaches three-dimensional memory device and method comprising forming multilayer stacks over a substrate, wherein the multilayer stack includes alternating first dielectric layers and second dielectric layers; forming first trenches in the multilayer stacks; and removing portions of sidewalls of the second dielectric layers exposed by the first trenches (figs. 1A-3B, [0014]-[0015], [0019], [0020] and [0022]).
In view of Ling’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen by incorporating the teaching as taught by Ling in order to arrive at the claimed invention.
Regarding claim 18, Chen as modified by Ling teaches all subject matter claimed as applied above. Ling further teaches wherein the first dielectric materials include silicon dioxide, and the levels of second dielectric materials including silicon nitride (figs. 1A-1B and [0016]).
Regarding claim 19, Chen as modified by Ling teaches all subject matter claimed as applied above. Ling further teaches wherein the level of dielectric material is one of the levels of the first dielectric materials (figs. 1A-1B and [0016]).
Allowable Subject Matter
Claim1-16 and 24-28 are allowed.
Claims 20-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The prior art of record, taken alone or in combination, fails to teach or fairly suggest an apparatus comprising: a conductive structure; a ferroelectric portion encircling the conductive structure; a charge storage structure encircling the ferroelectric portion; a dielectric portion encircling the charge storage structure; a semiconductor portion encircling the dielectric portion; a first additional conductive structure adjacent a first side of the semiconductor portion; and especially, a second additional conductive structure adjacent a second side of the semiconductor portion, wherein a direction from the first additional conductive structure to the second additional conductive structure is perpendicular to a direction of a length of the conductive structure as recited in claim 1 and further limitations of the dependent claims 2-11.
The prior art of record, taken alone or in combination, fails to teach or fairly suggest an apparatus comprising: tiers located one over another, each of the tiers including memory cells, the tiers including a first tier and a second tier; a first conductive structure extending through the tiers; a first memory cell included in the memory cells of the first tier, the first memory cell including: a first ferroelectric portion adjacent a first portion of the first conductive structure; a first charge storage structure adjacent the first ferroelectric portion; a first dielectric portion adjacent the first charge storage structure; and a first semiconductor portion adjacent the first dielectric portion; a second memory cell included in the memory cells of a second tier of the tiers, the second memory cell including: a second ferroelectric portion adjacent a second portion of the first conductive structure; a second charge storage structure adjacent the second ferroelectric portion; a second dielectric portion adjacent the second charge storage structure; and a second semiconductor portion adjacent the second dielectric portion; a first additional conductive structure located in the first tier and adjacent a first side of the first semiconductor portion; a second additional conductive structure located in the first tier and adjacent a second side of the first semiconductor portion; especially, a third additional conductive structure located in the second tier and adjacent a first side of the second semiconductor portion; and a fourth additional conductive structure located in the second tier and adjacent a second side of the second semiconductor portion, wherein each of the first, second, third, and fourth additional conductive structures has a length perpendicular to a direction from the first tier to the second tier as recited in claim 12 and further limitations of the dependent claims 13-16.
The prior art of record, taken alone or in combination, fails to teach or fairly suggest a method comprising: forming levels of first dielectric materials interleaved with levels of second dielectric materials; forming a first opening and a second opening through the levels of first dielectric materials and the levels of second dielectric materials to expose a first portion of a level of dielectric material among the levels of first dielectric materials and the levels of second dielectric materials, and to expose a second portion of the level of dielectric material at the second opening; removing at least part of the first portion to form a first recess in the level of dielectric material, and removing at least part of the second portion to form a second recess in the level of dielectric material; forming, in each of the first and second recesses, a semiconductor material, a dielectric material adjacent the semiconductor material, a charge storage material adjacent the dielectric material, a ferroelectric material adjacent the charge storage material, and a conductive material adjacent the dielectric material; especially, removing a portion of the levels of first dielectric materials interleaved with the levels of second dielectric materials to expose a portion of the semiconductor material formed in the first recess and a portion of the semiconductor material formed in the second recess; and forming a first conductive material adjacent the portion of the semiconductor material in the first recess; and forming a second conductive material adjacent the portion of the semiconductor material in the second recess as recited in claim 24 and further limitations of the dependent claims 25-28.
The prior art of record, taken alone or in combination, fails to teach or fairly suggest the further arrangement of the dependent claims 20-23.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
References: Frantin et al. (US 2022/0384719); Cook (US 12,336,185); Simsek-Ege (US 12,308,333); Scarbrough et al. (US 12,245,426); Graettinger et al. (US 11,864,475); Fratin et al. (US 12,219,784) and Sills (US 2018/0197864) are cited because they are related to memory device system and method.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tuyen Kim Vo whose telephone number is (571)270-1657. The examiner can normally be reached Mon-Thurs: 8AM-6:30PM.
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/TUYEN K VO/ Primary Examiner, Art Unit 2876