CTNF 18/520,056 CTNF 80377 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The prior art documents submitted by applicant in the Information Disclosure Statement(s) filed on November 1, 2025 have all been considered and made of record (note the attached copy(ies) of form PTO-1449). Election/Restrictions 08-06 AIA Claim s 6-7, 12-14, and 27-31 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on January 2, 2026 . Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “at least one output of the modulator” must be shown or the feature(s) canceled from the claim(s). Also, it is not clear from the drawings how the output of the modulator is in communication with the photodiode assembly. No new matter should be entered. 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Inventorship 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Line 2 recites a dimension range (e.g., at least 5 micron wide) without an upper limit. The examiner unable to search the limitation since the metes and bounds of the material width is unclear. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-5, 8-11 and 15-26 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. (US 2024/0255696 A1, herein “Kuo”) in view of Kamineni et al. (US 2023/0366913 A1, herein “Kamineni”) . Regarding claims 1 and 18-20, 23-26 Kuo discloses an electro-optical device (Fig. 2) comprising: a modulator (Indium Phosphide stack 214 with modulator electrodes 224, or chiplet 320 formed of thin film lithium niobate) comprising: an electro-optical material (InP stack 214, “By including deep-silicon vias (DSVs) 224 or other electrically-conductive vias and the waveguide(s) 226 in the silicon photonics structure 202 , an optical mode 227 can receive gain, phase modulation, or amplitude modulation.” {Para [0034]}), and a first silicon waveguide (226), a passivation layer (benzocyclobutene 212) disposed between the electro-optical material (InP) and the first silicon waveguide (226), the passivation layer (212)comprising a first side and a second side; and a photodiode assembly (germanium photodiode 228, Para [0037]) comprising: an absorption region (germanium 230), wherein the photodiode assembly is positioned relative to the first side of the passivation layer (212) and the electro-optical material (214) is positioned relative to the second side of the passivation layer; and wherein the photodiode assembly is in communication with at least one output of the modulator (via interposer 206 and the various DSVs). PNG media_image1.png 571 767 media_image1.png Greyscale However, Kuo does not explicitly teach a second silicon waveguide. Kamineni teaches a structure to incorporate multiple low loss photonic circuit components. The embodiment of Fig. 5 shows a PIC wafer 500 having multiple low loss photonic circuit components such as Ge photodiode 518. Kamineni further teaches plurality of silicon waveguides (514, 516) provided for performing different functions per photonic circuit designs. For example, waveguides 514, 516 may be used to implement a single photon detector, a phase shift for a switch, or they may receive light form optical interposer 542 through a grating coupler (Para [0096]). It would have been obvious to one having ordinary skill at the time of filing to recognize implementing additional “second silicon waveguide” would be obvious to one having ordinary skill in the art to support the plurality of photonic circuit components functions. One would be motivated to implement a ‘second silicon waveguide” to provide optical interconnection(s) between the plurality of photonic circuits. Regarding claims 2, 4-5, and 10, Kuo in view of Kamineni (herein “Kuo / Kamineni”) teach the device of claim 1, and Kuo further discloses a dielectric waveguide (224) that is positioned between the passivation layer (212) and the electro-optical material (InP stack 214) such that the dielectric waveguide and the electro-optical material operates as two cores of a hybrid waveguide (as visible the dotted circular shape notates as optical mode 227 shows the coupling of the optical mode from the InP layers through the substrate (not labeled) and coupled into waveguide 226 (Para [0034]). Metal electrodes sitting above the electro-optical material (205, the examiner notes, the embodiment shown in Fig. 2 is only exemplary of one InP stack wherein the device 200 can have multiple active devices, thus, multiple metal electrodes) Kuo further discloses the various components are measured in microns (e.g., alignment tolerance, waveguide dimension, Para [0044], [0066]). However, Kuo / Kamineni do not teach: the electro-optical material is about 5 micron wide the electro-optical material is separate from the first silicon waveguide by less than about 1 micron the vertical separation between a bottom surface of the electrodes and a top surface of the electro-optical material between 0 and 2 micron It would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to optimize the dimension of the electro-optical material, active layer dimension and separations between the electro-optical layer and electrode would be obvious since these layers determines the optimal operating characteristics of the modulator and the photodiode, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955). Claim 3 and 21, Kuo further discloses a thin film lithium niobate chiplet 320 shown in Fig. 3D, wherein the index of refraction of lithium niobate is 2.3. Claim 8, Kuo further discloses the electro-optical material is patterned to form a waveguide (thin film lithium niobate, TFLN chiplets 320 resulting in stack 330) and Fig. 6A shows in more detail of the patterning of the tapered waveguide(s). Claim 9, Kuo further discloses in Fig. 2 a dielectric waveguide (224) that is positioned between the passivation layer (212) and the electro-optical material (InP stack 214) such that the dielectric waveguide and the electro-optical material operates as two cores of a hybrid waveguide (as visible the dotted circular shape notates as optical mode 227 shows the coupling of the optical mode from the InP layers through the substrate (not labeled) and coupled into waveguide 226 (Para [0034]). Claim 11, Kuo further discloses the dielectric waveguide is made of silicon nitride (Para [0020], [0033]). Claim 15. Kuo further discloses the absorption region comprises germanium (230). Claim 16. Kuo further discloses in Fig. 3D the chiplet 320 is a thin film lithium niobate (104 in Fig. 1A, 320 in Fig. 3D, Para [0020] and [0043]). Regarding claims 17 and 22, Kuo / Kamineni teach the electro-optical material can be lithium niobate or indium phosphide, however, Kuo / Kamineni do not teach the electro-optical material can be BaTiO 3 . However, these are known materials and known properties of electro-optic, and the use thereof would have been predictable to one of ordinary skill in the art before the effective filing date of the claimed invention. The benefits of BaTiO 3 as an electro-optical material is its ultra-fast, highly efficient optical manipulation due to its high Pockels coefficients. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIN D CHIEM/Examiner, Art Unit 2874 /THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874 Application/Control Number: 18/520,056 Page 2 Art Unit: 2874 Application/Control Number: 18/520,056 Page 3 Art Unit: 2874 Application/Control Number: 18/520,056 Page 4 Art Unit: 2874 Application/Control Number: 18/520,056 Page 5 Art Unit: 2874 Application/Control Number: 18/520,056 Page 6 Art Unit: 2874 Application/Control Number: 18/520,056 Page 7 Art Unit: 2874 Application/Control Number: 18/520,056 Page 8 Art Unit: 2874 Application/Control Number: 18/520,056 Page 9 Art Unit: 2874
Prosecution Insights