DETAILED ACTION
1. This office action is in response to communication filed on 03/02/2026. Claims 4-5 have been amended. Claims 1-20 are pending on this application.
Response to Arguments
2. Applicant's arguments filed 03/02/2026 have been fully considered but they are not persuasive. A) With respect to claim 1 applicant argued “Zhang also fails to disclose, in response to determining that no most significant bit (MSB) is equal to one, setting a flag and truncating each of a first, second and third channel values, as required by claim 1. Thus, combining Zhang's mapping of prefix codes with Ito's sub-pixel conversion would still fail to result in the claimed invention”.
Examiner respectful disagrees from the following”.
Fig. 2 and Fig. 4 of Zhang discloses truncation of 32-bits data (200) into 11-bits data (203) based on no most significant bit (201) is equal to one (most significant bits 201 equal 0); setting a flag (prefix code generation 405 in Fig. 4); wherein the prefix code is an indication a number of most significant bits of 32-bit data not equal to one for truncation (truncation of Col. 3 lines 61-62; and 410 in Fig. 4) 32 bits into 11 bits data.
Fig. 1 and Fig. 3 of Ito et al. discloses a method of converting 10-bit pixel data (10 Bits) into 8-bit pixel data (8 BITs), the method comprising: in response to determining that two least significant bits (two lower significant bits 40 in Fig. 3) is equal to "11", "10", "01" and "00" (paragraph 0014), setting a flag (control signals for multiplexers 42, from comparator 44 in F3) and truncating (truncation of 11, 1C, 1B; paragraph 0014) each of a first, second and third channel values (1R “Red”, 1G “Green”, 1B “Blue” channels).
Fig. 1 and Fig. 3 of Ito et al. discloses every limitation for truncation of 10-bit to 8-bits conversion for each of a first, second and third channel values (1R “Red”, 1G “Green”, 1B “Blue” channels) except for based on most significant bits not equal to 1 as claimed.
Fig. 2 of Zhang discloses a truncation for truncate of 32-bits input data (200) into 11-bits output data based on no most significant bit is equal to 1 (most significant bits 201 not equal 1) as claimed.
Thus, combining truncation of bits-conversion based on most significant bit not equal 1 of Zhang into truncation of bits conversion for each channel of Ito et al. disclosed every limitation of applicant.
B) With respect to claim 14 applicant argued “Van Mourik is there any disclosure or mention of a flag at all. Van Mourik is there any disclosure or mention of a flag at all. The Office action appears to intimate that "RIN (7,6), GIN (7,6), BIN (7,6)" have "flags." This is incorrect. As clearly disclosed in col. 3, RIN, GIN and BIN are 8-bit input color signals (ie. red, green and blue), which are inputted into lookup tables to supply 8-bit gamma table signals. There are no "flags" set anywhere in these color signals”).
Examiner respectful disagrees from the following”
From the broadest interpretation in view of applicant’s specification “flag” is a bit indication for a converter to convert 8-bit input data to 10-bit output data for RED, GREEN, and BLUE channels.
Fig. 1 of Van Mourik discloses 8-bit to 10 bit converters (20, 22, 24) for three channel (Red 20, Green 22, Blue 24) by receive 8 bits input data (RCLUT(7-0), GCLU (7, 0), BCLU (7-0) for each channel (Red 20, Green 22, Blue 24), each channel (each of Red 20, Green 22, Blue 24) received an indication (RIN (7,6), GIN (7,6), BIN (7,6); see TABLE 2 on Col. 3), respectively, to generate 10-bit output data ROUT (9-0), GOUT (9-0), BOUT (9-0).
TABLE 2 on Col. 4 Van Mourik discloses the 10-bit output data ROUT (9-0) based on indication “00”, “01”, ”10”, “11” of RIN (7,6) and input data RCLUT (7-0).
Thus, Fig. 1 and TABLE 2 of Van Mourik discloses a flag (bit indicator of RIN (7,6)) for red channel; and Funamoto cure the deficiency of Claim 19 with respect to claim 14 anticipated by Fig. 1 and TABLE 2 of Van Mourik.
From explained above, the rejections of claims 1-4, and 8-20 are sustain for the same references applied to obvious office action.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 4, 8, 10-13, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. Pub. No. 2004/0189679 in view of Zhang U.S. patent No. 8,593,310.
Regarding claim 1. Fig. 1 and Fig. 4 of Ito et al. discloses a method of converting 10-bit pixel data (10 Bits) into 8-bit pixel data (8 BITs), the method comprising: in response to determining that two least significant bit (LSB) is equal to "11", "10", "01" and "00" (paragraph 0014), setting a flag (control signals for multiplexers 21, 23, 25 from controller 31 in Fig. 2) and truncating (truncation of 11, 1C, 1B; paragraph 0014) each of a first, second and third channel values (Red, Green, Blue channels).
However, Ito et al. do not disclose determining that no most significant bit (MSB) is equal to one for truncation.
Fig. 2 and Fig. 4 of Zhang discloses truncation of 32-bits data (200) into 11-bits data (203) comprising determining that no most significant bit (201) is equal to one (most significant bits 201 equal 0); setting a flag (prefix code generation 405 in Fig. 4) for truncation (truncation of Col. 3 lines 61-62; and 410 in Fig. 4).
Ito et al. and Zhang are common subject matter of truncation for bit length reduction; therefore, it would have been obvious before the effective filing date of claim invention to one ordinary skill in the art to which the claimed invention pertains to incorporate truncation based on most significant bits not equal 0 of Zhang et al. into truncation of Ito et al. for the purpose of providing high compression speed and high decompression speed for in storing system and serving real-time--websites, social networking systems, games (Col. 1 lines (32-35 of Zhang).
Regarding claim 4. Ito et al. and Zhang applied to claim 1 above, Fig. 1 of Ito further discloses method of converting the 10-bit pixel data (10 Bits) into 8-bit pixel data (8 bits) according to claim 1; and compressing (paragraph 0004 discloses “compresses the number of bits”) the RGB (11, 1G, 1B) data using a lossy compression technique (reduces 10 bits size by discarding 2 bits data to generate 8 bits size).
Regarding claim 8. Fig.1 and Fig. 4 of Ito et al. discloses hardware logic (hardware logic of bit rate converter 11; see Fig. 2 for discloses hardware logic of 11) arranged to convert 10-bit pixel data (10 BITS) into 8-bit pixel data (8 BITS), the hardware logic (11; see Fig 2) comprising: hardware logic (11; see Fig. 2) arranged in response to determining that two LSB is equal to "11", "10", "01" and "00" (paragraph 0014), setting a flag (generate a control signal of controller 31 for Multiplexer in Fig. 2) and truncating (11, 1C, 1B; paragraph 0014) each of a first, second and third channel values (Red, Green, Blue).
However, Ito et al. do not disclose determining that no most significant bit (MSB) is equal to one for truncation.
Fig. 2 and Fig. 4 of Zhang discloses 32-bits data (200) into 11-bits data (200) comprising determining that no most significant bit (201) is equal to one (most significant bits 201 equal 0); setting a flag (prefix code generation step 405 in Fig. 4) for truncation (truncation of Col. 3 lines 61-62; and step 410 in Fig. 4).
Ito et al. and Zhang are common subject matter of truncation for bit length reduction; therefore, it would have been obvious before the effective filing date of claim invention to one ordinary skill in the art to which the claimed invention pertains to incorporate truncation based on most significant bits is not equal 0 of Zhang et al. into truncation of Ito et al. for the purpose of providing high compression speed and high decompression speed for in storing system and serving real-time--websites, social networking systems, games (Col. 1 lines (32-35 of Zhang).
Regarding claim 10. Ito et al. and Zhang applied to claim 1 above, Fig. 1 and Fig. 2 of Ito et al. further discloses: Hardware logic (11; see Fig. 2) configured to perform the method as set forth in claim 1 (Ito and Zhang applied to claim 1 above).
Regarding claim 11. Ito et al. and Zhang applied to claim 1 above, Fig. 1 and Fig. 2 of Ito et al. further discloses: wherein the hardware logic (11; see Fig. 2) is embodied in hardware on an integrated circuit (integrated circuit of Bit Rate converter 11).
Regarding claim 12. Ito et al. and Zhang applied to claim 1 above, Zhang further discloses a non-transitory computer readable storage medium having stored thereon computer readable code configured to cause (Col. 7 lines 55-62 of Zhang) the method as set forth in claim 1 (Ito and Zhang applied t claim 1 above) to be performed when the code is run (Col. 7 lines 55-62 of Zhang).
Regarding claim 13. Ito et al. and Zhang applied to claim 1 above, Fig. 1 and Fig. 2 of Ito et al. further discloses: an integrated circuit manufacturing system (integrated circuit 11 manufacturing system of Fig. 1) configured to manufacture hardware logic (hardware logic of 1; see Fig. 2) as set forth in claim 10 (Ito et al. and Zhang applied to claim 10 above).
Regarding claim 18. Ito et al. and Zhang applied to claim 1 above, Zhang further discloses a non-transitory computer readable storage medium having stored thereon computer readable code (Col. 7 lines 46-62 of Zhang) configured to cause the method as set forth in claim 1 (Ito et al. and Zhang applied to claim 1 above) to be performed when the code is run on at least one processor (Col. 7 lines 46-62 of Zhang).
Regarding claim 20. Ito et al. and Zhang applied to claim 1 above, Fig. 1 of Ito et al. further discloses n integrated circuit manufacturing system (integrated system of Fig. 1) configured to manufacture hardware logic (hardware logic of 11, 1G, 1C; see Fig. 2) as set forth in claim 8 (Ito and Zhang applied to claim 8 above).
5. Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. and Zhang applied to claim 1 above in further view of Wyatt et al. U.S. patent No. 8,823,725.
Regarding claim 2. Ito et al. and Zhang applied to claim 1 above, Fig. 1 of Ito et al. further disclose 10-bit pixel data comprising RED GREEEN BLUE 10:10:10 but does not disclose 2 alpha bits for format pixel data RGBX10:10:10:2 as claimed.
Fig. 1 of Wayatt et al. discloses pixel data comprising RGBX 10:10:10:2 (Col. 2 lines 3-5 discloses “2 bits of alpha or unused, followed by 10 bits of red, 10 bits of green, and 10 bits of blue”).
Ito et al. and Wayatt et al. are common subject matter of pixel data; therefore; it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Wayatt et al. into Ito et al. for the purposed of providing 32 bits pixel data for RED, GREEN and BLUE for display (Col. 2 lines 1-6 of Wayatt et al.).
Regarding claim 3. Ito et al. and Zhang applied to claim 1 above, Fig. 1 of Ito et al. further discloses wherein the 8-bit pixel data comprises RGBX888 format pixel data (8 bits of RED: 8 bits of GREEN: 8 bis of BLUE); but does not disclose 8 alpha bits X for format pixel data RGBX8888 as claimed.
Fig. 1 of Wayatt et al. discloses pixel data comprising RGBX8888(Col. 2 lines 1-3 discloses “(e.g. a 32 bits pixel may contain 8 bits of alpha or unused, including 8 bits of red, 8 bits of green, and 8 bits of blue”).
Ito et al. and Wayatt et al. are common subject matter of pixel data; therefore; it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Wayatt et al. into Ito et al. for the purposed of providing 32 bits pixel data for RED, GREEN and BLUE for display (Col. 2 lines 1-6 of Wayatt et al.).
8. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ito et al. and Zhang applied to claim 1 above in further view of Miyagi et al. Pub. No. 2005/0207661.
Ito et al. and Zhang applied to claim 8 above do not disclose a data compression element arranged to compress the 8-bit pixel data output by the hardware logic using a lossy compression technique.
Fig. 1A of Miyai et al. discloses a hardware logic (Filtering Process) ) arranged to convert 10-bit pixel data (10bit) into 8-bit pixel data (8bit), a data compression element (JPEG Compression Unit 6) arranged to compress the 8-bit pixel data (8bit) output by the hardware logic (4) using a lossy compression technique (paragraph 0042).
Ito et al. and Miyai et al. are common subject matter compression of pixel data; therefore; it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Miyai et al. into Ito et al. for the purposed of providing less memory and less power for gamma correction while retaining the gray levels of the input video signal (paragraph 0005 of Miyai et al.).
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 14 -17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Van Mourik U.S. patent No. 6,215,468.
Regarding claim 14. Fig. 1 of Van Mourik discloses a method (8 bits to 10 bits conversion of 20, 22, 24) of decompressing 8-bit pixel data (RCLUT (7-0), GCLUT (7-0), BCLUT (7-0)) into 10-bit pixel data, (ROUT (9-0), GOUT (9-0), BOUT (9-0)) the method (20, 22, 24) comprising: in response to a flag (flag of RIN (7,6) GIN (7,6), B IN (7,6)) adding two bits (TABLE 2 Col. 3) to each of a first, second and third channel values (bits of RCLUT (7-0), GCLUT (7-0), BCLUT (7-0)) , such that the most significant bit (MSB) of each channel values is a zero (Col. 2lines 8-9 discloses “the most significant bits (MSB's) of the output are always 0”).
Regarding claim 15. The method of claim 14, Van Mourik further discloses wherein the flag (flag of RIN (7,6) GIN (7,6), B IN (7,6) is a flag value (Col. 2 lines 25-30 disclose append two bits value 00 or 01 of flag value Vin (7,6) to bits of VLUT (7-0) to each of a first, second and third channel values (RCLUT (7-0), GCLUT (7-0), BCLUT (7-0)).
Regarding claim 16. Fig. 1 of Van Mourik further disclose s Hardware logic (hardware logic 8 bits to 10 bits converter 20, 22, 24) configured to perform the method of claim 14 (method of Fig. 1).
Regarding claim 17. The hardware logic of claim 16, Van Mourik further discloses wherein the hardware logic (hardware logic 8 bits to 10 bits converter 20, 22, 24) is embodied in hardware on an integrated circuit (hardware integrated circuit 1).
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Van Mourik applied to claim 14 above, in further view of Funamoto U.S. patent No. 8,964,073.
Van Mourik applied to claim 14 above disclose the method (8 bits to 10 bits conversion of 20, 22, 24) as set forth claim 14 (applied to claim 14 above); but does not disclose a non-transitory computer readable storage medium having stored thereon computer readable code configured to cause conversion of 8 bits to 10 bits method to be performed when the code is run on at least one processor.
Fig. 1 of Funamoto discloses a non-transitory computer readable storage medium having stored thereon computer readable code configured to cause conversion of 8 bits to 10 bits method (44) to be performed when the code is run on at least one processor (Col. 16 lines 32-36).
Van Mourik and Funamoto are common subject matter of 8 bits to 10 conversion; therefore; it would have been obvious before the effective filing date of claimed invention to one ordinary skill in the art to which the claimed invention pertains to incorporate Funamoto into Van Mourik for the purposed of providing a non-transitory computer-readable storage medium storing computer-readable instructions thereon, which, when executed by an image outputting apparatus including one or more integrated circuits, cause the image outputting apparatus to perform a method (Col. 16 lines 32-36 of Funamoto).
Allowable Subject Matter
10. Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if overcome insufficient antecedent basis rejection above and rewritten in independent form including all of the limitations of the base claim and any intervening claims. wherein compressing the RGBX data using a lossy compression technique comprises: dividing a block of pixels into a plurality of sub-blocks; and for each sub-block: analyzing an alpha channel value for each pixel in the sub-block to select a lossy compression mode from a set of candidate lossy compression modes, wherein the set of candidate lossy compression modes comprises three compression modes which each use a different fixed alpha channel value for all pixels in the sub-block; and compressing the sub-block using the selected lossy compression mode.
Conclusion
11. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
04/30/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845
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