DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1-2, 6, 15, 18, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feste et al. (US 5,710,729).
Regarding claim 1, Feste teaches that a radio frequency transmitter (column 1, lines 9 – column 2, lines 9 and Fig. 1). Feste teaches that a filtering circuit (Fig. 6), the filtering circuit comprising: a shift register (Fig. 1) comprising a binary input and N number of binary outputs (Fig. 1, 3 and column 2, lines 25 – column 3, lines 55, where teaches the coefficients and the input samples are memorized in memories, then for each output sample L additional addressing and L additional readings in memory are necessary), N being an integer greater than or equal to M, M being an integer greater than or equal to 2 (Fig. 1, 3 and column 2, lines 25 – column 3, lines 55, where teaches advantageous to choose the oversampling factor equal to a submultiple of the length L of the filter, i.e. equal to a power of 2. Then of 2 N samples only 2 M are other than zero and the oversampling factor is equal to 2 (N-M), and the number of products and sums to be performed is only 2 M), each binary output having an index identifier ranging from 0 to N-1, the shift register configured to: receive a binary data signal at a first frequency on the binary input (Fig. 1, 3 and column 2, lines 25 – column 3, lines 55, where teaches advantageous to choose the oversampling factor equal to a submultiple of the length L of the filter, i.e. equal to a power of 2. Then of 2 N samples only 2 M are other than zero and the oversampling factor is equal to 2 (N-M). In this case the number of products and sums to be performed is only 2 M), and implement shifts on the binary outputs at a second frequency equal to the first frequency multiplied by M, the shift register being a series to parallel shift register (Fig. 1, 4 and column 3, lines 16 – column 4, lines 63, where teaches loading a new sample in memory M2 during a period of the clock signal CLK and at the same time the blocking of the second counter CO2 generating the addresses of the memory M2 of the samples and resetting the counter CO1 generating the addresses of the memory M1 of the coefficients so as to phase shift the two counters by one clock stroke, and insertion of a new sample is done simply and without losing any clock strokes and is thus transparent to the flow of output samples at the filter), a first circuit implemented as a function of N number of coefficients, the first circuit configured to, for each non-zero coefficient of the N number of coefficients (Fig. 1, 3 and column 2, lines 25 – column 3, lines 55, where teaches configuring for each non-zero coefficient of N number of coefficients), deliver a respective analog signal determined by the associated coefficient and a binary state of a respective output (Fig. 1, 3 and column 3, lines 16 – column 4, lines 63, where teaches make address generation for the coefficients simple and efficient, there are two possibilities, practicable only if the power oversampling factor is 2, and an input I and an output O and a first memory M1 for memorization of the coefficients, and the input I is connected to the data input of a second memory M2, the data outputs of the two memories M1 and M2 are connected to a multiplier MU, the output of the multiplier MU is connected to an accumulator AC by means of its data input), and an adder circuit configured to deliver an analog output signal at an output of the filtering circuit, the analog output signal being equal to the sum of the respective analog signal for each non-zero coefficient of the N number of coefficients (Fig. 1, 4, 6, column 1, lines 42 – column 2, lines 60, and column 3, lines 16 – column 4, lines 63, where teaches a filter FIR with four coefficients with parallel architecture having input IS and output OS made up of four identical blocks connected in cascade and each one comprising a delay element T, an adder S, and a multiplier K. Each multiplier K multiplies the value at the input for a different fixed coefficient, respectively K0, K1, K2, K3, and oversampling factor equal to a submultiple of the length L of the filter, i.e. equal to a power of 2. Then of 2 N samples only 2 M are other than zero and the oversampling factor is equal to 2 (N-M), and the number of products and sums to be performed is only 2 M).
Regarding claim 2, Feste teaches that the coefficients are determined by an impulse response of an interpolation filter of a raised cosine type (Fig. 1, 6 and column 1, lines 37 – column 2, lines 60, where teaches filtering method which would permit satisfaction of requisites of said amount by means of a filter having a serial architecture with finite impulse response having a simple control unit, and a corresponding filter).
Regarding claim 6, Feste teaches that the shift register comprises N number of synchronous D-type flip-flops controlled by a clock signal at the second frequency, the N number of synchronous D-type flip-flops being series-connected, and the binary outputs corresponding to outputs of the N number of synchronous D-type flip-flops (Fig. 1, 4, 6 and column 3, lines 16 – column 5, lines 10).
Regarding claim 15, Feste teaches all the limitation as discussed in claim 1. Furthermore, Feste further teaches that receiving a binary data signal at a first frequency on a binary input of a shift register (Fig. 1, 3 and column 2, lines 25 – column 3, lines 55, where teaches advantageous to choose the oversampling factor equal to a submultiple of the length L of the filter, i.e. equal to a power of 2. Then of 2 N samples only 2 M are other than zero and the oversampling factor is equal to 2 (N-M). In this case the number of products and sums to be performed is only 2 M), the shift register being a series to parallel shift register of a filtering circuit of a radio frequency transmitter (Fig. 1, 4 and column 3, lines 16 – column 4, lines 63, where teaches loading a new sample in memory M2 during a period of the clock signal CLK and at the same time the blocking of the second counter CO2 generating the addresses of the memory M2 of the samples and resetting the counter CO1 generating the addresses of the memory M1 of the coefficients so as to phase shift the two counters by one clock stroke, and insertion of a new sample is done simply and without losing any clock strokes and is thus transparent to the flow of output samples at the filter), implementing shifts on N number of binary outputs of the shift register at a second frequency equal to a first frequency multiplied by M, N being an integer greater than or equal to M, M being an integer greater than or equal to 2, each binary output having an index identifier ranging from 0 to N-1 (Fig. 1, 3 and column 2, lines 25 – column 3, lines 55, where teaches advantageous to choose the oversampling factor equal to a submultiple of the length L of the filter, i.e. equal to a power of 2. Then of 2 N samples only 2 M are other than zero and the oversampling factor is equal to 2 (N-M), and the number of products and sums to be performed is only 2 M), delivering, by a first circuit of the filtering circuit implemented as a function of N number of coefficients, for each non-zero coefficient of the N number of coefficients, a respective analog signal determined by the associated coefficient and a binary state of a respective output (Fig. 1, 3, column 2, lines 25 – 67, and column 3, lines 16 – column 4, lines 63, where teaches make address generation for the coefficients simple and efficient, there are two possibilities, practicable only if the power oversampling factor is 2, and an input I and an output O and a first memory M1 for memorization of the coefficients, and the input I is connected to the data input of a second memory M2, the data outputs of the two memories M1 and M2 are connected to a multiplier MU, the output of the multiplier MU is connected to an accumulator AC by means of its data input, and oversampling factor equal to a submultiple of the length L of the filter, i.e. equal to a power of 2. Then of 2 N samples only 2 M are other than zero and the oversampling factor is equal to 2 (N-M), and the number of products and sums to be performed is only 2 M), and delivering, by an adder circuit of the filtering circuit, an analog output signal at an output of the filtering circuit, the analog output signal being equal to the sum of the respective analog signal for each non-zero coefficient of the N number of coefficients (Fig. 1, 4, 6, column 1, lines 42 – column 2, lines 60, and column 3, lines 16 – column 4, lines 63, where teaches a filter FIR with four coefficients with parallel architecture having input IS and output OS made up of four identical blocks connected in cascade and each one comprising a delay element T, an adder S, and a multiplier K. Each multiplier K multiplies the value at the input for a different fixed coefficient, respectively K0, K1, K2, K3, and oversampling factor equal to a submultiple of the length L of the filter, i.e. equal to a power of 2. Then of 2 N samples only 2 M are other than zero and the oversampling factor is equal to 2 (N-M), and the number of products and sums to be performed is only 2 M).
Regarding claim 18, Feste teaches all the limitation as discussed in claims 1 and 6.
Regarding claim 21, Feste teaches all the limitation as discussed in claims 1 and 15.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Feste in view of Huang (US 2022/0052718).
Regarding claim 14, Feste does not disclose the limitation “the radio frequency transmitter is configured to transmit in the 60-GHz band”. However, Huang teaches the limitation “the radio frequency transmitter is configured to transmit in the 60-GHz band” (Fig. 1, 2 and pages 4, paragraphs 33 – 34, where teaches radio-frequency transmitter communicating new radio frequency range 2 (FR2) bands between 20 and 60 GHz). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of the Feste’s communication frequency band of wireless communication circuitry as taught by Huang, provide the motivation to using efficient frequency band in communication circuitry for improving communication performance.
Allowable Subject Matter
5. Claims 3-5, 7-13, 16-17, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to disclose the limitation “the shift register comprises N synchronous latches controlled by a clock signal at a third frequency equal to the first frequency multiplied by M/2, the N synchronous latches coupled in series by alternating latches active on a first level of the clock signal and latches active on a second level of the clock signal, the binary outputs corresponding to outputs of the N synchronous latches, and deliver a first analog signal in response to an associated binary output being in a first binary state and the coefficient being positive or the associated binary output being in a second binary state and the coefficient being negative, and deliver a second signal complementary to the first signal in response to the associated binary output being in a second binary state and the coefficient being positive or the associated binary output being in a first binary state and the coefficient being negative” as specified the claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Magdeburger et al. (US 2007/0052557) discloses Shared Memory and Shard Multiplier Programmable Digital-Filter Implementation.
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J.L
April 2, 2026
John J Lee
/JOHN J LEE/
Primary Examiner, Art Unit 2649
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