Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to Applicant' s communication filed 2/3/26 in response to the Office action dated 11/6/25. Claims 1, 11, and 20 have been amended. Claims 1-7, 10-17, and 20 are pending in this application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 8-14, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Fujii et al. (US 5553307 A), hereinafter Fujii, in view of Agrawal et al. (US 20220405253 A1), hereinafter Agrawal, and further in view of Kim et al. (US 20220179573 A1), hereinafter Kim.
Regarding claim 1, Fujii teaches an apparatus, comprising: a non-volatile memory device comprising a first controller (Col. 4, lines 38-44; Fig. 1, disk drive 140, HDC 120 [first controller]);
and a second controller coupled with the non-volatile memory device (DMAC 110 [second controller]), wherein the second controller is configured to cause the apparatus to:
issue, to the first controller, a first command to sense data stored at one or more planes of the non-volatile memory device (Col. 6, lines 60-62; Fig. 6, step 504, HDC 120 reads the data in disk segment 141 [plane] of disk drive 140);
transfer, in response to the first command, the data from the one or more planes to an interface between the one or more planes and the second controller (Col. 6, lines 60-63; Figs. 1 and 6, step 504, transfers data from disk segment 141 through bus 5 [interface]);
issue, to the first controller, a second command to transfer one or more portions of the data to the second controller (Col. 6, lines 58-60; Fig. 6, step 503, data transfer from HDC [first controller] to DMAC 110 [second controller] is indicated),
the second command comprising a bitmap that indicates the one or more portions of the data to transfer to the second controller (Col. 6, lines 10-12; Fig. 5 disk-read bit-map 151 determines which data to transfer);
wherein the second command is issued over a plurality of unit intervals (Col. 9, lines 1-8; Fig. 11, 8 bits of the bit-map (two sets of 4 bits [unit intervals]) is sent to HDC [first controller] via write gate signal on signal line 2106),
a set of bits of the second command issued over a unit interval of the plurality of unit intervals (Col. 6, lines 29-39, Col. 9, lines 15-27; Figs. 1 and 11, transmitting 8 bits of the bit-map, which are issued as 2 4-bit unit intervals via the write gate signal); and
transfer, in response to the second command, the one or more portions of the data to the second controller via the interface in accordance with the bitmap (Col. 4, lines 45-48; Col. 6, lines 63-67; Figs. 1 and 6, step 505, data is transferred to the cache managed by DMAC 110 [second controller] via bus 2 [interface] according to bit-map 151).
Fujii does not expressly disclose that the write gate signal in Fig. 11 is split into separate 4-bit unit intervals. However, Fujii discloses a 1-to-1 correspondence between a plurality of bits in the bit-map and a plurality of signal values/intervals in the write gate signal (Col. 9, lines 15-27; Fig. 11). Before the effective filing date of the claimed invention, it would have been an obvious design choice to one of the ordinary skill in the art to separate the write gate signal into 4-bit intervals, since it has been held that constructing a formerly integral structure into various elements involves only routine skill in the art. The mere fact that a given structure is integral does not preclude its consisting of various elements. Nerwin v. Erlichman, 168 USPQ 177, 179.
Furthermore, Fujii does not explicitly teach wherein each bit of the bitmap indicates whether a respective portion of the data is valid or invalid based at least in part on a mapping between a logical address associated with the respective portion of the data and a physical address associated with the respective portion of data, and the second command comprising a first set of four bits of the bitmap corresponding to a first set of four portions of the one or more portions included in a first plane of the one or more planes and comprising a second set of four bits of the bitmap corresponding to a second set of four portions of the one or more portions included in a second plane of the one or more planes, the first plane different from the second plane.
However, Agrawal teaches wherein each bit of the bitmap indicates whether a respective portion of the data is valid or invalid based at least in part on a mapping between a logical address associated with the respective portion of the data and a physical address associated with the respective portion of data (Paragraphs 71, 83; Fig. 1, element M1, bits of the bitmap BMP indicate whether a given data portion contains valid data, wherein the data portion is represented by a logical block address LBA which is associated [mapped] with a physical location in storage).
Fujii and Agrawal are analogous art because they are in the same field of endeavor, that being non-volatile memory data migration. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Fujii to further include the mapping of logical and physical locations within the bitmap according to the teachings of Agrawal. The motivation for doing so would have been to reduce host processing overhead (Agrawal, Paragraphs 122-123).
Fujii in view of Agrawal does not explicitly teach the second command comprising a first set of four bits of the bitmap corresponding to a first set of four portions of the one or more portions included in a first plane of the one or more planes and comprising a second set of four bits of the bitmap corresponding to a second set of four portions of the one or more portions included in a second plane of the one or more planes, the first plane different from the second plane.
However, Kim teaches the second command comprising a first set of four bits of the bitmap corresponding to a first set of four portions of the one or more portions included in a first plane of the one or more planes (Paragraphs 43-48; Figs 3 and 4, performing an internal copy operation using a second bitmap table which contains a number of bits (Fig. 4 showing 4 or more bits corresponding to 4 or more page groups within die 0) that indicate whether a corresponding page group [portion] in die 0 [containing a first plane] is valid or not) and
comprising a second set of four bits of the bitmap corresponding to a second set of four portions of the one or more portions included in a second plane of the one or more planes, the first plane different from the second plane (Paragraphs 43-48; Figs 3 and 4, performing an internal copy operation using a second bitmap table which contains a number of bits (Fig. 4 showing 4 or more bits corresponding to 4 or more page groups within die 1) that indicate whether a corresponding page group [portion] in die 1 [containing a second plane] is valid or not).
Fujii, Agrawal, and Kim are analogous art because they are in the same field of endeavor, that being non-volatile memory data migration. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Fujii in view of Agrawal to further include the multi-page bitmap command according to the teachings of Kim. The motivation for doing so would have been to improve operational speed and access time (Kim, Paragraphs 52-53).
Regarding claim 2, Fujii in view of Agrawal, further in view of Kim teaches the apparatus of claim 1, wherein, to transfer the one or more portions of the data from the interface to the second controller, the second controller is configured to cause the apparatus to: transfer a first portion of the data to the second controller in accordance with the bitmap (Fujii, Col. 7, lines 18-24; Fig. 8, steps 703 and 704, writing data in the i-th bit of bit-map 151 [indicated portion] to disk cache 130 managed by DMAC 110 [second controller]);
and skip the transfer of a second portion of the data to the second controller in accordance with the bitmap (Fujii, Col. 7, lines 25-32, steps 703, 705, and 706, inhibiting the writing of the i-th data block if the bitmap reads “0” and moving to the next block).
Regarding claim 3, Fujii in view of Agrawal, further in view of Kim teaches wherein the second controller is further configured to cause the apparatus to: generate the second command comprising the bitmap in accordance with a validity of the data transferred to the interface (Fujii, Col. 5, lines 49-53; Col. 6, lines 8-12; Fig. 5, data is transferred based on generated bit-map 150 which indicates the dirtiness [validity] of the data),
the bitmap indicating to transfer valid portions of the data and to skip transferring invalid portion of the data (Fujii, Col. 5, lines 52-53; Col. 6, lines 63-67; Fig. 6, step 505, data is transferred based on whether bit-map 151 has a value of “1” or “0”, indicating whether a respective data block is dirty or clean [valid or invalid], respectively),
wherein the one or more portions of the data indicated by the bitmap correspond to the valid portions of the data (Fujii, Col. 5, lines 51-59; Fig. 1, dirty [valid] data blocks are shown as “1” bits on bit-map 151).
Regarding claim 4, Fujii in view of Agrawal, further in view of Kim teaches the apparatus of claim 1, wherein, to transfer the one or more portions of the data from the interface to the second controller, the second controller is configured to cause the apparatus to: set a position of a cursor to a first portion of the data indicated by the bitmap for transfer to the second controller (Fujii, Col. 7, lines 13-14 and 17-18; Fig. 8, steps 701 and 703, the index ‘I’ [cursor] is set to 1, indicating the reading of the first block of data represented in the bit-map);
transfer the first portion of the data based at least in part on setting the position of the cursor to the first portion of the data (Fujii, Col. 7, lines 18-24; Fig. 8, steps 703 and 704, if the bit value of the current index’s [cursor’s] block is “1”, then the block is written),
wherein the position of the cursor is at a second portion of the data after transferring the first portion of the data (Fujii, Col. 7, lines 31-34; Fig. 8, step 705, after the block is transferred/not transferred, the index is incremented by one, moving on to read the next bit [second portion of data]);
set the position of the cursor to a third portion of the data indicated by the bitmap for transfer to the second controller (Fujii, Col. 7, lines 31-34; Fig. 8, step 705, the index moves to the next bit [third portion of data])
based at least in part on the bitmap indicating to skip transferring the second portion of the data (Fujii, Col. 7, lines 25-31; Fig. 8, steps 703 and 706, if the bit reads “0”, then the block [second portion] is skipped);
and transfer the third portion of the data based at least in part on setting the position of the cursor to the third portion of the data (Fujii, Col. 7, lines 17-24; Fig. 8, steps 703 and 704, if the bit value of the current index’s [cursor’s] block is “1”, then the block is written).
Regarding claim 6, Fujii in view of Agrawal, further in view of Kim teaches the apparatus of claim 1, wherein, to transfer the one or more portions of the data from the interface to the second controller, the second controller is configured to cause the apparatus to: determine to skip transferring a first portion of the data in accordance with the bitmap (Fujii, Col. 7, lines 25-31; Fig. 8, steps 703 and 706, if the bit reads “0”, then the block [first portion] is skipped);
set a position of a cursor to a second portion of the data indicated by the bitmap for transfer to the second controller (Fujii, Col. 7, lines 31-34; Fig. 8, step 705, the index moves to the next bit [second portion of data]),
wherein the first portion of the data is skipped from being transferred based at least in part on setting the position of the cursor to the second portion of the data (Fujii, Col. 7, lines 25-33; Fig. 8, steps 705 and 706, writing from the block is inhibited and the index [cursor] is moved to the next block [second portion]);
and transfer the second portion of the data based at least in part on setting the position of the cursor to the second portion of the data (Fujii, Col. 7, lines 18-24; Fig. 8, steps 703 and 704, the i-th bit of bit-map 151 [pointer’s current portion of data] is written [transferred]).
Regarding claim 10, Fujii in view of Agrawal, further in view of Kim teaches the apparatus of claim 1, wherein each bit of the bitmap corresponds to the respective portion of the data (Fujii, Col. 5, lines 51-59; Fig. 1, bit-map 150 which indicates the dirtiness [validity] of the data blocks, wherein each bit corresponds with a respective data block [portion])
and indicates whether to transfer the respective portion of the data to the second controller (Fujii, Col. 6, lines 8-12; Fig 5, data blocks are transferred to cache memory 130 [managed by DMAC 110 (second controller)] in accordance with bit-map 150).
Regarding claim 11, this is a computer readable medium version of the claimed apparatus discussed above (claim 1, respectively), in which Fujii in view of Agrawal, further in view of Kim also teaches a non-transitory computer-readable medium (Fujii, Col. 4, lines 36-42; Fig. 1, disk subsystem)
storing code comprising instructions which are executed by a processor (Fujii, Col. 4, lines 57-59; Fig. 1, micro program 101 included in microprocessor 100).
The remaining claim limitations have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Fujii in view of Agrawal, further in view of Kim.
Regarding claim 12, this is a computer readable medium version of the claimed apparatus discussed above (claim 2, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Fujii in view of Agrawal, further in view of Kim.
Regarding claim 13, this is a computer readable medium version of the claimed apparatus discussed above (claim 3, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Fujii in view of Agrawal, further in view of Kim.
Regarding claim 14, this is a computer readable medium version of the claimed apparatus discussed above (claim 4, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Fujii in view of Agrawal, further in view of Kim.
Regarding claim 16, this is a computer readable medium version of the claimed apparatus discussed above (claim 6, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Fujii in view of Agrawal, further in view of Kim.
Regarding claim 20, this is a method version of the claimed apparatus discussed above (claim 1, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Fujii in view of Agrawal, further in view of Kim.
Claims 5, 7, 15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Fujii in view of Agrawal, further in view of Kim as applied to claims 1, 4, 11, and 14 above, and further in view of Danilak et al. (US 20140157078 A1), hereinafter Danilak.
Regarding claim 5, Fujii in view of Agrawal, further in view of Kim teaches the apparatus of claim 4, wherein the position of the cursor is set to the third portion of the data (Fujii, Col. 7, lines 31-34; Fig. 8, step 705, the index moves to the next bit [third portion of data]).
Fujii in view of Agrawal, further in view of Kim does not explicitly teach in accordance with a size of a portion of the data indicated by a host system.
However, Danilak teaches in accordance with a size of a portion of the data indicated by a host system. (Paragraphs 19, 30, and 43; Fig. 1A, TRIM command issued from a host may indicate the size of an E-Page [portion], the minimum unit of a data transfer. The size of the E-Pages affects the physical positioning of their encapsulating F-Page, which determines the address [position] the controller 102 needs to skip to in order to sequentially access the next F-Page in response to an invalid prior F-Page).
Fujii, Agrawal, Kim, and Danilak are analogous art because they are in the same field of endeavor, that being non-volatile memory data management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Fujii in view of Agrawal, further in view of Kim to further include the host indicating the size of a data portion according to the teachings of Danilak. The motivation for doing so would have been to accommodate the changing conditions of the memory blocks (Danilak, Paragraph 29).
Regarding claim 7, Fujii in view of Agrawal, further in view of Kim teaches the apparatus of claim 1, wherein each bit of the bitmap corresponds to a respective portion of the data having the data chunk size (Fujii, Col. 5, lines 51-59; Col. 5, line 3; Fig. 1, bit-map 150 indicates the dirtiness [validity] of data blocks, wherein each bit corresponds with a respective data block [chunk] having a size of S bytes).
Fujii in view of Agrawal, further in view of Kim does not explicitly teach wherein the second controller is further configured to cause the apparatus to receive, from a host system, a trim command comprising an indication of a data chunk size.
However, Danilak teaches wherein the second controller is further configured to cause the apparatus to receive, from a host system, a trim command comprising an indication of a data chunk size (Paragraphs 19 and 30, TRIM command issued from a host to a memory controller may indicate the size of an E-Page [data chunk], the minimum unit of a data transfer).
Fujii, Agrawal, Kim, and Danilak are analogous art because they are in the same field of endeavor, that being non-volatile memory data management. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Fujii in view of Agrawal, further in view of Kim to further include the TRIM command according to the teachings of Danilak. The motivation for doing so would have been to accommodate the changing conditions of the memory blocks (Danilak, Paragraph 29).
Regarding claim 15, this is a computer readable medium version of the claimed apparatus discussed above (claim 5, respectively), in which Fujii in view of Agrawal, further in view of Kim and Danilak also teaches a non-transitory computer-readable medium (Fujii, Col. 4, lines 36-42; Fig. 1, disk subsystem),
storing code comprising instructions which are executed by a processor (Fujii, Col. 4, lines 57-59; Fig. 1, micro program 101 included in microprocessor 100).
The remaining claim limitations have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Fujii in view of Agrawal, further in view of Kim and Danilak.
Regarding claim 17, this is a computer readable medium version of the claimed apparatus discussed above (claim 7, respectively), wherein all claim limitations also have been addressed and/or covered in cited areas as set forth above. Thus, accordingly, this claim is also obvious over Fujii in view of Agrawal, further in view of Kim and Danilak.
Response to Arguments
Applicant’s arguments (see pages 9-11 of the remarks) filed 2/3/26, with respect to the rejections of claims 1, 11, and 20 under 35 U.S.C 103 have been fully considered, and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection in made in view of Fujii, Agrawal, and Kim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Pinga whose telephone number is (571) 272-2620. The examiner can normally be reached on M-F 8:30am-6pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla, can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/J.M.P./Examiner, Art Unit 2137
/Arpan P. Savla/Supervisory Patent Examiner, Art Unit 2137