DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 and 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US PGPub 2021/0201818) in view of Yuan et al. (US PGPub 2024/0260343), and Zhou et al. (US PGPub 2023/0360579).
Regarding claim 1, Jang discloses a display device ([0058] and fig. 1, display apparatus) comprising:
a display panel (fig. 1, “light emitting display panel 10”) including a display area ([0060], “a display area (or active area) AA”) and a non-display area ([0089], “the substrate 100 can include a non-display area (or a non-display portion) corresponding to an area where the pad part 110 is provided”), the display area including at least one pixel ([0060], “a plurality of pixels P arranged at a first interval D1 on the display area AA of the substrate 100”);
a gate driver (figs. 2 & 6, gate driving circuit 150) in the display area of the display panel ([0060], “a gate driving circuit 150 disposed within the display area AA”), wherein the gate driver is configured to supply one or more gate signals to the at least one pixel ([0084], “The gate driving circuit 150 can be disposed within the display area AA to supply a scan signal (or a gate signal) to the pixels P disposed on the substrate 100”);
a set ofwherein the set of ([0189], gate control signals, gate control line group GCL);
([0189], first to third gate driving powers GVdd1, GVdd2, and GVdd3); and
one or more second power lines connected to the one or more first power lines ([0189], first to third gate common powers GVss1, GVss2 and GVss3),
While Jang teaches a display area and a non-display area and power lines for providing power that are not horizontal lines disposed in a horizontal line area in the non-display area, it has been known to make use of power lines either in a vertical or horizontal direction in the non-display area for providing power. In a similar field of endeavor of display devices, Yuan discloses a set of horizontal lines (Bus including CLK-Bus, CLKB-Bus) disposed in a horizontal line area in the non-display area (fig. 4, area below the display area), wherein at least a portion of the set of horizontal lines extends in a first direction (__); one or more first power lines disposed in the horizontal line area in the non-display area (fig. 4, VGL-Bus); wherein the one or more first power lines are electrically connected to the at least one pixel to supply one or more power voltages to the at least one pixel (fig. 4, VGL-Bus is electrically connected to the pixels in the pixels area for supplying power thereto); wherein at least a portion of the one or more first power lines also extends in the first direction (__); and one or more second power lines connected to the one or more first power lines (fig. 4, VGL-1 and VGL-2 connected to VGL-Bus), wherein the one or more second power lines intersect the set of horizontal lines (fig. 4, VGL-1 and VGL-2 each intersects Bus including CLK-Bus and CLKB-Bus).
In view of the teachings of Jang and Yuan, it would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include and arrange the needed signal and power lines as known and taught by Yuan within the system of Jang depending on space and manner of layout arrangements, for the purpose of increasing flexibility of layout arrangements.
While the combination of Jang and Yuan teaches use of a chip-on-film (COF) and a gate driver as known structures in a display panel (Jang: [0092]), it has been known to have a COF in a non-display area electrically connected to a gate driver. In a similar field of endeavor of display panels, Zhou similarly discloses wherein the set of horizontal lines are electrically connected to the gate driver to supply one or more gate control signals to the gate driver (fig. 2 and [0049], “As shown in FIG. 2, in order to further improve the full-screen effect, an ultra-narrow bezel display panel has been proposed in the related art, where a GOA circuit is arranged on the DP side of the panel. As compared to the aforementioned Normal panel, there is one more vertical scanning line (V Gate) extending in the column direction Y and passing through pixels in the display area, and this vertical scanning line is switched through a through-hole structure (the location of this through-hole structure is a joint point A shown in FIG. 2) to be connected with a horizontal scanning line (H Gate) extending in the row direction X, thus enabling row driving, and implementing ultra-narrow bezels on two opposite sides in the row direction X and on the DPO side. With respect to such panel, the CLK signal is input from COFs on the two opposite sides along the row direction X of the panel and introduced into the panel by the GOA circuit on the DP side, wherein the GOA scanning direction is from the DP side to the DPO side. The Data signal is input from the COF terminal on the DP side and extends to the DPO side. It should be understood that this accessing way of the Gate signal is understood to be an access method using a V-line (a thin single-dot chain line as shown in FIG. 2), and this ultra-narrow bezel display panel may be defined as a V-panel.”); and furthermore teaches a chip-on-film (COF) in the non-display area, wherein the COF is electrically connected to the gate driver ([0086], “The aforementioned gate drive circuit and source drive circuit may be integrated in the non-display area of the array substrate, or connected with the non-display area of the array substrate through a COF”); wherein the horizontal line area is disposed between the display area and the COF ([0049], “As shown in FIG. 2, in order to further improve the full-screen effect, an ultra-narrow bezel display panel has been proposed in the related art, where a GOA circuit is arranged on the DP side of the panel. As compared to the aforementioned Normal panel, there is one more vertical scanning line (V Gate) extending in the column direction Y and passing through pixels in the display area, and this vertical scanning line is switched through a through-hole structure (the location of this through-hole structure is a joint point A shown in FIG. 2) to be connected with a horizontal scanning line (H Gate) extending in the row direction X, thus enabling row driving, and implementing ultra-narrow bezels on two opposite sides in the row direction X and on the DPO side. With respect to such panel, the CLK signal is input from COFs on the two opposite sides along the row direction X of the panel and introduced into the panel by the GOA circuit on the DP side, wherein the GOA scanning direction is from the DP side to the DPO side. The Data signal is input from the COF terminal on the DP side and extends to the DPO side. It should be understood that this accessing way of the Gate signal is understood to be an access method using a V-line (a thin single-dot chain line as shown in FIG. 2), and this ultra-narrow bezel display panel may be defined as a V-panel. It should be noted that the V-line refers to the line that connects each joint point A in the panel in sequence. As shown in FIG. 2, the Date RC is gradually increased from the DP side to the DPO side, the CLK RC is gradually increased from the two opposite sides in the row direction X to the center, and the V Gate RC is gradually increased from the junction to the two opposite sides in the row direction X”).
In view of the teachings of Jang, Yuan and Zhou, it would have been obvious to one of ordinary skill in the art to include the COF in the non-display area as taught by Zhou within the system of Jang and Yuan, for the purpose of implementing an ultra-narrow bezel display panel to improve user experience by increasing a display area relative to the size of the device (Zhou: [0049]).
Regarding claim 2, the combination of Jang, Yuan, and Zhou further discloses further comprising:
a set of data lines connected to the at least one pixel to supply one or more data signals to the at least one pixel (Jang: [0120], “The pixel circuit PC according to an embodiment can be disposed in a circuit area CA of the pixel area PA and can be connected to gate lines GLo and GLe adjacent thereto, data lines DLo and DLe adjacent thereto, and the pixel driving power line PL”),
wherein at least one of the set of data lines, one or more first power lines, and the set of horizontal lines are disposed on a different layer than another one of the set of data lines, one or more first power lines, and the set of horizontal lines (Jang: [0133], “one side of each of the plurality of line connection patterns LCP can be electrically connected to a portion of the secondary power line SPL through a first line contact hole formed in an insulation layer on the secondary power line SPL, and the other side of each of the plurality of line connection patterns LCP can be electrically connected to a portion of the pixel common power line CPL through a second line contact hole formed in an insulation layer on the pixel common power line CPL”).
Regarding claim 3, the combination of Jang, Yuan, and Zhou further discloses wherein the at least one pixel includes:
at least one first thin film transistor including a first active layer formed of polysilicon, a first source electrode, a first drain electrode, and a first gate electrode (Jang: [0145], “the driving TFT Tdr can be a TFT including a semiconductor layer (or an active layer) including low-temperature polysilicon (LTPS) having an excellent response characteristic”); and
at least one second thin film transistor including a second active layer formed of oxide semiconductor, a second source electrode, a second drain electrode, and a second gate electrode (Jang: [0145], “the other of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr can be a TFT including a semiconductor layer (or an active layer) including oxide which is good in off current characteristic”).
Regarding claim 4, the combination of Jang, Yuan, and Zhou further discloses further comprising a set of data lines connected to the at least one pixel (Jang: [0120], “The pixel circuit PC according to an embodiment can be disposed in a circuit area CA of the pixel area PA and can be connected to gate lines GLo and GLe adjacent thereto, data lines DLo and DLe adjacent thereto, and the pixel driving power line PL”), wherein a material of the set of horizontal lines is different from a material of the set of data lines and a material of the one or more first power lines (Jang: [0111], “he plurality of pixel driving power lines PL can have a ladder structure or a mesh structure, and thus, the voltage drop (IR drop) of the pixel driving power caused by a line resistance of each of the plurality of pixel driving power lines PL can be prevented or minimized” and [0335], “Each of data lines DL, pixel driving power lines PL, and reference power lines RL among the pixel driving lines GL, DL, PL, RL, CPL, PSL, RDL, and LCP can include the same material as that of the source/drain electrode SD1 and SD2, but is not limited thereto. Also, each line of a gate control line group GCL can include the same material as that of the source/drain electrode SD1 and SD2, but is not limited thereto”).
Regarding claim 5, the combination of Jang, Yuan, and Zhou further discloses wherein the set of horizontal lines is formed in a same layer as the second gate electrode or the second source electrode or the second drain electrode (Jang: [0133], “Each of the plurality of line connection patterns LCP can be disposed on the substrate 100 so that a pixel common power line CPL and a secondary power line SPL adjacent to each other intersect with each other and can electrically connect a pixel common power line CPL and a secondary power line SPL adjacent to each other by using a line jumping structure.”).
Regarding claim 6, the combination of Jang, Yuan, and Zhou further discloses wherein the one or more first power lines or the one or more second power lines is formed in a same layer as the second source electrode or the second drain electrode (Jang: [0335], “Each of data lines DL, pixel driving power lines PL, and reference power lines RL among the pixel driving lines GL, DL, PL, RL, CPL, PSL, RDL, and LCP can include the same material as that of the source/drain electrode SD1 and SD2, but is not limited thereto. Also, each line of a gate control line group GCL can include the same material as that of the source/drain electrode SD1 and SD2, but is not limited thereto”).
Regarding claim 7, the combination of Jang, Yuan, and Zhou further discloses wherein the at least one pixel includes an intermediate electrode electrically connected to the first source electrode or the first drain electrode, and wherein at least a portion of the one or more first power lines or the one or more second power lines is formed in a same layer as the intermediate electrode (Jang: [0133], “Each of the plurality of line connection patterns LCP can be disposed on the substrate 100 so that a pixel common power line CPL and a secondary power line SPL adjacent to each other intersect with each other and can electrically connect a pixel common power line CPL and a secondary power line SPL adjacent to each other by using a line jumping structure. For example, one side of each of the plurality of line connection patterns LCP can be electrically connected to a portion of the secondary power line SPL through a first line contact hole formed in an insulation layer on the secondary power line SPL, and the other side of each of the plurality of line connection patterns LCP can be electrically connected to a portion of the pixel common power line CPL through a second line contact hole formed in an insulation layer on the pixel common power line CPL”).
Regarding claim 8, the combination of Jang, Yuan, and Zhou further discloses wherein the one or more data lines is formed in a same layer as the first gate electrode (Jang: [0335], “Each of data lines DL, pixel driving power lines PL, and reference power lines RL among the pixel driving lines GL, DL, PL, RL, CPL, PSL, RDL, and LCP can include the same material as that of the source/drain electrode SD1 and SD2, but is not limited thereto”).
Regarding claim 9, the combination of Jang, Yuan, and Zhou further discloses wherein the at least one pixel further includes a storage capacitor including a first capacitor electrode and a second capacitor electrode, wherein the one or more data lines is formed in a same layer as the second capacitor electrode (Jang: [0157], “The storage capacitor Cst can include a first capacitor electrode connected to the gate electrode of the driving TFT Tdr, a second capacitor electrode connected to the source electrode of the driving TFT Tdr, and a dielectric layer formed in an overlap region between the first capacitor electrode and the second capacitor electrode. The storage capacitor Cst can be charged with a difference voltage between the gate electrode n1 and the source electrode n2 of the driving TFT Tdr, and then, can turn on or off the driving TFT Tdr on the basis of a charged voltage”).
Regarding claim 10, the combination of Jang, Yuan, and Zhou further discloses further comprising:
a data driver connected to the display panel to supply the set of gate control signals to the set of horizontal lines (Jang: [0091], “The driving circuit unit 30 according to an embodiment can include a plurality of flexible circuit films 31”), wherein the data driver is implemented as the chip-on-film (COF) including a film and the data driver is an integrated circuit on the film (Jang: [0092], “The flexible circuit film 31 according to an embodiment can be a tape carrier package (TCP) or a chip-on film (COF)”).
Regarding claim 11, the combination of Jang, Yuan, and Zhou further discloses
wherein at least a portion of the one or more second power lines is disposed on the film of the COF adjacent to the integrated circuit (Jang: [0470], “The driving IC 530 can be mounted on the flexible circuit film 510. The driving IC 530 can be connected to the plurality of data lines DL, the plurality of pixel driving power lines PL, the plurality of pixel common power lines CPL, and a plurality of reference power lines RL via the flexible circuit film 510, the third pad part 230, the link line portion 250, the second pad part 210, the routing portion 400, and the first pad part 110” where according to [0092] the flexible circuit film 31 can be a chip-on film).
Regarding claim 12, the combination of Jang, Yuan, and Zhou further discloses
wherein at least a portion of the one or more second power lines extends through the data driver (Cheng: fig. 3, VDD, VEE, Vref signals near the data signals).
Regarding claim 13, the combination of Jang, Yuan, and Zhou further discloses further comprising:
a set of data lines connected to the at least one pixel; a set of second gate control lines connected to the set of horizontal lines, wherein the set of data lines extends from a center of the integrated circuit, and wherein the set of second gate control lines extends from an edge portion of the integrated circuit (Jang: [0480], “in each of the plurality of display modules DM1 to DM4, a second interval D2 between a center portion CP of an outermost pixel Po and an outermost outer surface VL of the first substrate 100 can be implemented to be half or less of a first interval D1 between adjacent pixels. Accordingly, in two adjacent display modules connected to (or contacting) each other at side surfaces thereof in the first direction X and the second direction Y on the basis of a lateral coupling manner, an interval “D2+D2” between adjacent outermost pixels PAo can be equal to or less than the first interval D1 between two adjacent pixels”).
Regarding claim 14, the combination of Jang, Yuan, and Zhou further discloses wherein the gate driver includes a branch circuit configured to generate a gate signal, and components of the branch circuit are arranged along two or more columns in the display area (Jang: [0086], “The plurality of branch circuits BC can include at least one TFT (or a branch TFT) and can be disposed one by one between at least one pixels P (or pixel areas PA) within one horizontal line along the first direction X. Each of the plurality of stage circuit units can generate a scan signal according to driving of the plurality of branch circuits BC which responds to a gate control signal supplied from the driving circuit unit 30 through the gate control line group separately disposed (or distributedly disposed) between a plurality of pixels P in the display area AA and can supply the scan signal to pixels disposed in a corresponding horizontal line”).
Regarding claim 19, the combination of Jang, Yuan, and Zhou further discloses wherein a first power line and a second power line is configured to supply a high potential drive voltage EVDD, and another first power line and another second power line is configured to supply a low potential drive voltage (Jang: [0189], “first to third gate driving powers GVdd1, GVdd2, and GVdd3, and first to third gate common powers GVss1, GVss2 and GVss3”).
Regarding claim 20, the combination of Jang, Yuan, and Zhou further discloses further comprising a power supply unit configured to supply one or more drive voltages to the one or more first power lines and the one or more second power lines (Jang: [0105], “The power circuit unit 39 can be mounted on the PCB 35 and can generate various source voltages needed for displaying an image on the pixels P by using an input power supplied from the outside to provide the generated source voltage to a corresponding circuit. For example, the power circuit unit 39 can generate and output a logic source voltage needed for driving of each of the timing controller 37 and the driving ICs 33, the plurality of reference gamma voltages provided to the driving ICs 33, and at least one gate driving power and at least one gate common power needed for driving of the gate driving circuit 150. The gate driving power and the gate common power can have different voltage levels”).
Regarding claim 21, the combination of Jang, Yuan, and Zhou further discloses wherein the one or more second power lines intersect the set of horizontal lines in the non-display area (Yuan: fig. 4, VGL-Bus intersecting VGL-2).
Regarding claim 22, the combination of Jang, Yuan, and Zhou further discloses wherein the set of horizontal lines are disposed between the gate driver and the COF to electrically connect the gate driver and the COF (Zhou: [0063], “In addition, the CLK signal may be introduced through the COF on the upper side of the display panel as shown in FIG. 4. That is, the COF on the upper side of the display panel may be connected with each shift register unit group in a gate drive circuit through one or more CLK lines, and is introduced into the panel (e.g., in the display area with pixels) through each shift register unit group on the upper side. The cascading direction of the shift register unit groups is from the left and right sides of the display panel towards the center, and the scanning direction is from the lower side of the display panel to the upper side thereof. That is, the scanning direction is from the lower side of the display panel to the upper side thereof”).
Regarding claim 23, the combination of Jang, Yuan, and Zhou further discloses wherein the one or more second power lines intersect the set of horizontal lines in the horizontal line area (Yuan: fig. 4, VGL-Bus intersecting VGL-2).
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Jang, Yuan, and Zhou further in view of Cheng (US PGPub 2020/0202783).
Regarding claim 15, the combination of Jang, Yuan, and Zhou discloses a gate driver in general, however specific structures of gate drivers are known. In a similar field of endeavor of display devices, Cheng discloses wherein the gate driver includes at least a scan control driver and a light emission (EM) control signal driver, and wherein the scan control driver is configured to receive one or more scan control signals and the EM control signal driver is configured to receive one or more emission control signals ([0011], “The input module receives a reference level and a data signal, and generates a first signal in response to a light emission control signal and a scan signal. The reset module receives the reference level and generates a reset signal in response to a sub-light emission control signal and the scan signal. The data processing module receives the first signal, the reset signal and a first voltage, and generates a second signal in response to the scan signal. The switch module receives the second signal and generates a light emission signal in response to the light emission control signal”).
In view of the teachings of Jang, Yuan, Zhou and Cheng it would have been obvious to one of ordinary skill in the art to include the gate driver of Cheng within the system of Jang, Yuan, and Zhou, for the purpose of providing a specific gate driver structure which is known to increase display stability.
Regarding claim 16, the combination of Jang, Yuan, Zhou, and Cheng further discloses, wherein a number of the one or more scan control signals is different from a number of the one or more emission control signals (Cheng: [0015], “when a plurality of pixel compensation circuits are connected in series to form a scat of pixel compensation circuits, the light emission control signal of an (N+1)th level pixel compensation circuit is used as the sub-light emission control signal of an Nth level pixel compensation circuit, and N is a positive integer”).
Regarding claim 17, the combination of Jang, Yuan, Zhou, and Cheng further discloses
wherein the gate driver includes at least a second scan control driver configured to receive one or more second scan control signals, wherein the scan control driver is configured to generate at least one scan signal and the second control scan driver is configured to generate at least one second scan signal, and wherein a number of the one or more scan control signals is different from a number of the one or more second scan control signals (Cheng: [0015], “when a plurality of pixel compensation circuits are connected in series to form a scat of pixel compensation circuits, the light emission control signal of an (N+1)th level pixel compensation circuit is used as the sub-light emission control signal of an Nth level pixel compensation circuit, and N is a positive integer”).
Regarding claim 18, the combination of Jang, Yuan, Zhou, and Cheng further discloses
wherein the gate driver includes at least a second scan control driver configured to receive one or more second scan control signals, wherein the scan driver is configured to generate at least one scan signal and the second scan driver is configured to generate at least one second scan signal, and wherein a signal of the one or more scan control signals is different from a signal of the one or more second scan control signals (Jang: [0085], “The gate driving circuit 150 according to an embodiment can be implemented with a shift register including a plurality of stage circuit units. For example, the display apparatus according to the present disclosure can include a shift register which is disposed within the display area AA of the substrate 100 to supply the scan signal to the pixel P”).
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. As discussed in the interview of 02/05/2026, Applicants amendment overcomes the cited portions of the prior art of record but requires further consideration as it changes the scope of the claim since both at least a portion of the set of horizontal lines and one or more first power lines extend in a first direction. Based on the amendment as filed, Examiner updated citations of the Yuan reference where the CLK-Bus and CLKB-Bus serve as the set of horizontal lines, the VGL-Bus serves as the first power line(s) and the VGL-1 and BGL-2 serve as the second power lines. See above prior art rejection for full detail of how all claimed limitations are addressed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhou et al. (US PGPub 2021/0408057) discloses a structure diagram of another display panel (fig. 5).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY J FRANK whose telephone number is (571)270-7255. The examiner can normally be reached Monday-Thursday 8AM-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629
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