Prosecution Insights
Last updated: October 04, 2026
Application No. 18/520,843

SYSTEMS AND METHODS FOR TESTING THERMAL CONDITIONING OF AN INTEGRATED CIRCUIT (IC)

Non-Final OA §103
Filed
Nov 28, 2023
Examiner
RODAK, LEE E
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Smart Modular Technologies Inc.
OA Round
5 (Non-Final)
72%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
270 granted / 374 resolved
+4.2% vs TC avg
Strong +34% interview lift
Without
With
+34.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
36 currently pending
Career history
407
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
52.9%
+12.9% vs TC avg
§102
21.6%
-18.4% vs TC avg
§112
19.5%
-20.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 374 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/05/2026 has been entered. Response to Amendment The amendments filed on 06/05/2026 have been fully considered and are made of record. Claims 1, 3 and 9 have been amended. Claims 2, 4, 8 and 10-11 have been cancelled. Response to Arguments Applicant’s arguments filed on 06/05/2026, with respect to claims 1 and 9 have been fully considered and are moot because new ground(s) of rejection has been applied to amended limitations. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3, 9, 12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Co et al. (Patent NO. CN 1812199 A; hereinafter Co; translation attached) in view of KR et al. (KR 20210141027; hereinafter KR). Regarding claim 1, Co teaches a testing element, comprising: a riser card (see Fig. 5 - expansion card 12) comprising: an insertion blade configured to be inserted into a circuit board (expansion card 12 includes blade with contacts 24 configured to be inserted into slot 18 of main board 26) ; a socket configured to receive a chip under test (expansion card 12 includes memory module slot 38 configured to receive memory module 10, see para [0072]), wherein the chip under test comprises a memory card on which a plurality of memory chips are mounted (memory module 10 inherently include plurality of chips); and the riser card configured to: space the chip under test from the circuit board (see Fig. 5 - expansion card 12 spaces the memory module 10 away from board 26). Co teaches thermal testing of the memory module 10 by creating a heating chamber not shown (see para [0081]). Co is silent with respect to the heating mechanism and therefore does not explicitly teach the riser card comprising a heating element, the riser card configured to test thermal conditioning of an integrated circuit on the chip under test by applying heat to the chip under test with the heating element, and the riser card coupled to a power supply, as claimed. However KR teaches an expansion card with an on-board heating socket for testing. Specifically KR teaches the riser card (see Fig. 1 - assembly formed by 100, 200, 300) comprising a heating element (heating socket 300), the riser card configured to test thermal conditioning of an integrated circuit on the chip under test by applying heat to the chip under test with the heating element (300 used to heater integrated circuit 110 for testing, see para [0038] for example), and the riser card coupled to a power supply (see para [0080] - power supply connected to thermoelectric element 310 of the heating socket 300), as claimed. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the riser card taught by Co to include the heating element, be configured to test thermal conditioning of the integrated circuit on the chip under test by applying heat to the chip under test with the heating element, and be coupled to a power supply as taught by KR as not more than predictable use of prior art elements according to established functions. One would be motivated to make such a modification to position the heating mechanism in close proximity to the memory module to be able to more accurately and timely control the temperatures of the chip under test. Regarding Claim 3, KR teaches the testing element of claim 1. KR further teaches wherein the riser card further comprising a temperature sensor (See page 13) configured to report a temperature to a remote location (sever 400 sends to remote location 500 in Fig. 1 from temperature sensor; See page 4-6). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the riser card taught by Co to include the riser card further comprising a temperature sensor configured to report a temperature to a remote location as taught by KR as not more than predictable use of prior art elements according to established functions. One would be motivated to make such a modification to position the heating mechanism in close proximity to the memory module to be able to more accurately and timely control the temperatures of the chip under test. Regarding Claim 9, Co teaches a method for testing a chip for thermal conditioning, comprising: inserting a chip under test comprising a memory card into a socket (expansion card 12 includes memory module slot 38 configured to receive memory module 10, see para [0072]) on a riser card (see Fig. 5 - expansion card 12); inserting the riser card into a motherboard using an insertion blade (expansion card 12 includes blade with contacts 24 configured to be inserted into slot 18 of main board 26) on the riser card (see Fig. 5 - expansion card 12); Co teaches thermal testing of the memory module 10 by creating a heating chamber not shown (see para [0081]). Co is silent with respect to heating the chip using a heating element in the riser card; and measuring metrics associated with the chip under test, as claimed. However KR teaches an expansion card with an on-board heating socket for testing. Specifically KR teaches the riser card (see Fig. 1 - assembly formed by 100, 200, 300) comprising a heating element (heating socket 300), the chip using a heating element in the riser card (300 of riser card used to heater integrated circuit 110 for testing, see para [0038] for example), and measuring metrics associated with the chip under test (See table 1 is measuring metrics of the chip under test 110 in Fig. 1; See page 12-14), as claimed. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the riser card taught by Co to heat the chip using a heating element in the riser card; and measuring metrics associated with the chip under test as taught by KR as not more than predictable use of prior art elements according to established functions. One would be motivated to make such a modification to position the heating mechanism in close proximity to the memory module to be able to more accurately and timely control the temperatures of the chip under test. Regarding Claim 12, Co in view KR teaches the method of claim 9. KR further teaches wherein heating the chip under test comprises heating a memory module (See page 18). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the riser card taught by Co to include heating the chip under test comprises heating a memory module as taught by KR as not more than predictable use of prior art elements according to established functions. One would be motivated to make such a modification to position the heating mechanism in close proximity to the memory module to be able to more accurately and timely control the temperatures of the chip under test. Regarding Claim 15, Co in view KR teaches the method of claim 9. KR further teaches further comprising sensing a temperature in the riser card with a temperature sensor (See page 13). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the riser card taught by Co to include sensing a temperature in the riser card with a temperature sensor as taught by KR as not more than predictable use of prior art elements according to established functions. One would be motivated to make such a modification to position the heating mechanism in close proximity to the memory module to be able to more accurately and timely control the temperatures of the chip under test. 12. Claim(s) 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Co in view of KR in view of Norris et al. (Pub NO. US 2002/0118032 A1; hereinafter Norris). Regarding Claim 5, Co in view of KR teaches the testing element of claim 1. KR further teaches wherein the heating element (heating element 225-1 and 225-2 in Fig. 3B). KR silent about comprises a resistor. Norris teaches heating element of DUT comprises resistor (See [0022], [0031]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the heating element of Co and KR, by using resistor as heating element, as taught by Norris in order to provide thermal communication to DUT with resistor (Norris; [0022]). Regarding Claim 13, Co in view of KR teaches the method of claim 9. KR further teaches wherein heating the chip under test in riser card to heat the chip under test (heating chip under test 110 with riser card 300/200/100 in Fig. 1) Co in view of KR is silent about comprises using resistors. Norris teaches heating element of DUT comprises resistor (See [0022], [0031]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the heating element of Co and KR, by using resistor as heating element, as taught by Norris in order to provide thermal communication to DUT with resistor (Norris; [0022]. Claim(s) 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Co in view of KR further in view of Carlson. Regarding Claim 6, Co in view of KR teaches the testing element of claim 1. KR further teaches wherein the heating element (heating element 225-1 and 225-2 in Fig. 3B). KR Co in view of is silent about comprises a Peltier device. Carlson teaches heating element of DUT comprises a Peltier device (See [0015]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the heating element of Co and KR, by using Peltier device as heating element, as taught by Carlson in order to provide heat to DUT (Carlson; [0015]. Regarding Claim 14, Co in view of KR teaches the method of claim 9. KR further teaches wherein heating the chip under test in riser card (heating chip under test 110 with riser card 300/200/100 in Fig. 1). KR is silent about comprises using a Peltier device. Carlson teaches heating element of DUT comprises a Peltier device (See [0015]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the heating element of Co and KR, by using Peltier device as heating element, as taught by Carlson in order to provide heat to DUT (Carlson; [0015]. 15. Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over KR in view of Akers. Regarding Claim 7, KR teaches the testing element of claim 1, wherein the heating element (heating element 300 in Fig. 1). KR is silent about comprises an internal trace conductor. Akers teaches heating element comprises an internal trace conductor (heating element 110 comprises internal trace conductor 122 in Fig. 5; See [0032]-[0034]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the heating element of KR, by using heating element comprises an internal trace conductor, as taught by Akers in order to provide heat to DUT (Akers; [0015]). Conclusion 5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZANNATUL FERDOUS whose telephone number is (571)270-0399. The examiner can normally be reached on Monday Friday 8am-5pm est. 6. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Rodak Lee can be reached on 571 -270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZANNATUL FERDOUS/ Examiner, Art Unit 2858 /LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
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Prosecution Timeline

Show 6 earlier events
Mar 20, 2026
Response Filed
Apr 22, 2026
Final Rejection mailed — §103
May 11, 2026
Applicant Interview (Telephonic)
May 12, 2026
Response after Non-Final Action
May 14, 2026
Examiner Interview Summary
Jun 05, 2026
Request for Continued Examination
Jun 08, 2026
Response after Non-Final Action
Jul 27, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+34.1%)
2y 8m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 374 resolved cases by this examiner. Grant probability derived from career allowance rate.

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