Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments filed on 03/20/2026 have been considered but are not persuasive.
Regarding 102 rejection, applicant argued at page7-8 for independent claims 1and 9 that “claim 1 requires that the integrated circuit be spaced from a circuit board by the riser card. Page 6 of the Office Action asserts that the expansion card 200 is configured to connect with the motherboard, and therefore, the integrated circuit 110 would be spaced from the board into which the expansion card 200 is inserted. However, since page 6 also indicates that the riser card of the claim is element 300, for anticipation, the integrated circuit 110 has to be spaced from the "motherboard" by element 300, not the expansion card 200. That is, the expansion card 200 is not the riser card 300. Nothing in the Office Action explains how the IC 110 is spaced from any board by element 300. Thus, the Office Action does not establish anticipation for claim 1 for this additional reason”. Examiner respectfully disagrees.
Element 300 is part of element 200 and all are connected together. Therefore it is inherent property that if integrated circuit 110 is spaced apart from mother board by 200, it also spaced from mother board by element 300, because element 300 is part of element 200 and both are connected together with mother board.
Therefore the rejection stands.
Regarding 102 rejection, applicant argued at pages 8-9 for independent claim 8 that “Akers does not teach the loop around a chip under test…. Thus, heating loop 110 uses the PCM 122 to heat the thermally-conductive structure as described in paragraph 0030, but it is not around the chip under test. Thus, Akers does not anticipate claim 8”. Examiner respectfully disagrees.
Akers teaches heating loop 110 is paced around DUT of 103 in Fig. 2. Akers also teaches heating loop 110 contains fluid to control temperature of DUT via thermally conducting structure 108 and air mover 106 in Fig. 2 (See [0030]).
Therefore Akers teaches heating loop 112 is used to heat DUT.
Also Fig. 5 of claimed invention shows heating loop 502 is placed near DUT 310. Akers also teaches heating loop 110 is placed near DUT 103 in Fig. 2.
Therefore Akers teaches heating 110 is placed to heat DUT.
Therefore applicant’s arguments regarding 102 rejection are not persuasive.
Therefore the rejection stands.
Claim Rejections - 35 USC § 102
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
10. Claim(s) 1-4 and 9-12 are rejected under 35 U.S.C. 102(a1) as being anticipated by KR et al. (Pub NO. KR 20210141027 A; hereinafter KR; translation attached).
Regarding Claim 1, KR teaches a testing element (testing element in Fig. 1), comprising:
a riser card (300 in fig. 1; See page 3-10) comprising a heating element configured to
test thermal conditioning of an integrated circuit spaced from a circuit board by the riser card (300 is used to heat integrated circuit 110 and the expansion card 200 is considered to inherently be configured to connect with a mother board and therefore the integrated circuit 110 would be spaced from the board into which expansion card 200 is inserted fig. 1; See page 3-10); and
be coupled to a power supply (300 in Fig. 1 is connected to power supply in Fig. 8; See page 3-10).
Regarding Claim 2, KR teaches the testing element of claim 1, wherein the riser card further comprises a socket configured to receive a chip under test having the integrated circuit (See the socket of 200 to receive chip under test 110 in Fig. 1; See page 3-10).
Regarding Claim 3, KR teaches the testing element of claim 1, further comprising a temperature sensor (See page 13) configured to report a temperature to a remote location (sever 400 sends to remote location 500 in Fig. 1 from temperature sensor; See page 4-6).
Regarding Claim 4, KR taches the testing element of claim 1, wherein the riser card further comprises an insertion blade configured to be inserted into a motherboard (the insertion card is inherently connected with/ inserted in a motherboard (not shown)).
Regarding Claim 9, KR teaches a method for testing a chip for thermal conditioning (heating chip 110 for thermal conditioning in Fig. 1; See page 4-6), comprising:
heating a chip under test that is in a socket in a riser card (heating chip under test 110 is in a socket of 100 of riser card 300 in Fig. 1; See page 4-6) spaced from a motherboard (300 is used to heat integrated circuit 110 and the expansion card 200 is considered to inherently be configured to connect with a mother board and therefore the integrated circuit 110 would be spaced from the board into which expansion card 200 is inserted fig. 1; See page 3-10),
wherein the heating comprises using a heating element in the riser card (300 is heating element of riser card n Fig. 1; See page 3-10); and
measuring metrics associated with the chip under test (See table 1 is measuring metrics of the chip under test 110 in Fig. 1; See page 12-14).
Regarding Claim 10, KR teaches the method of claim 9, further comprising placing the riser card into a second socket on the motherboard (placing riser 223 into second socket 228-1/228-2 of mother board 212 in Fig. 3B; See page 3-10).
Regarding Claim 11, KR teaches the method of claim 10, further comprising placing the chip under test into the socket in the riser card (placing chip under test 110 into socket of 100 of riser card 300/200/100 in Fig. 1; See page 4-6).
Regarding Claim 12, KR teaches the method of claim 9, wherein heating the chip under test comprises heating a memory module (See page 18).
Regarding Claim 15, KR teaches the method of claim 9, further comprising sensing a temperature in the riser card with a temperature sensor (See page 13).
Claim Rejections - 35 USC § 103
11. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claim(s) 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over KR in view of Norris et al. (Pub NO. US 2002/0118032 A1; hereinafter Norris).
Regarding Claim 5, KR teaches the testing element of claim 1, wherein the heating element (heating element 225-1 and 225-2 in Fig. 3B).
KR silent about comprises a resistor.
Norris teaches heating element of DUT comprises resistor (See [0022], [0031]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the heating element of KR, by using resistor as heating element, as taught by Norris in order to provide thermal communication to DUT with resistor (Norris; [0022]).
Regarding Claim 13, KR teaches the method of claim 9, wherein heating the chip under test in riser card to heat the chip under test (heating chip under test 110 with riser card 300/200/100 in Fig. 1)
KR is silent about comprises using resistors.
Norris teaches heating element of DUT comprises resistor (See [0022], [0031]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the heating element of KR, by using resistor as heating element, as taught by Norris in order to provide thermal communication to DUT with resistor (Norris; [0022].
Claim(s) 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over KR further in view of Carlson.
Regarding Claim 6, KR teaches the testing element of claim 1, wherein the heating element (heating element 225-1 and 225-2 in Fig. 3B).
KR is silent about comprises a Peltier device.
Carlson teaches heating element of DUT comprises a Peltier device (See [0015]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the heating element of KR, by using Peltier device as heating element, as taught by Carlson in order to provide heat to DUT (Carlson; [0015].
Regarding Claim 14, KR teaches the method of claim 9, wherein heating the chip under test in riser card (heating chip under test 110 with riser card 300/200/100 in Fig. 1).
KR is silent about comprises using a Peltier device.
Carlson teaches heating element of DUT comprises a Peltier device (See [0015]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the heating element of KR, by using Peltier device as heating element, as taught by Carlson in order to provide heat to DUT (Carlson; [0015].
14. Claim(s) 8 is rejected under 35 U.S.C. 102(a1) as being anticipated by Akers et al. (Pub NO. US 2017/0322253 A1; hereinafter Akers).
Regarding Claim 8, Akers teaches a testing element (See Fig. 5; See [0032]-0040]) comprising:
a tubular loop configured to receive a heated fluid (See the loop 110 in Fig. 5; See [0032]-[0033]),
the tubular loop further configured to be placed around a chip under test (See [0032]-[0033]),
such that heat is added to the chip under test (heating loop 110 adds heat to DUT/chip under test in Fig. 5; See [0032]-[0034]).
15. Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over KR in view of Akers.
Regarding Claim 7, KR teaches the testing element of claim 1, wherein the heating element (heating element 300 in Fig. 1).
KR is silent about comprises an internal trace conductor.
Akers teaches heating element comprises an internal trace conductor (heating element 110 comprises internal trace conductor 122 in Fig. 5; See [0032]-[0034]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the heating element of KR, by using heating element comprises an internal trace conductor, as taught by Akers in order to provide heat to DUT (Akers; [0015]).
Conclusion
16. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZANNATUL FERDOUS whose telephone number is (571)270-0399. The examiner can normally be reached Monday through Friday 8am to 5pm (PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rodak Lee can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZANNATUL FERDOUS/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858