DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the filling of the Amendment on 12/05/2025.
Amendments to the claims, each claim has not been provided with the proper status identifier, and as such, the individual status of each claim cannot be identified. Note: the status of every claim must be indicated after its claim number by using one of the following status identifiers: (Original), (Currently amended), (Canceled), (Previously presented), (New), (Not entered), (Withdrawn) and (Withdrawn-currently amended). It should be noted that while the status identifier for claim 5 is currently listed as "Original", it is clear from the present underlined limitations, that the claim is actually "Canceled". For the purpose of examination, the claim has been treated as having been canceled.
Claim Objections
Claim 1 is objected to because of the following informalities: Claim 1, lines 12-13 recites “a voltage divider the differential amplifier circuit”, which appears a typographical error of -- a voltage divider, the differential amplifier circuit --. Claim 1, lines 18 recites “the reference node wherein”, which appears a typographical error of -- the reference node; wherein --. Claim 1, line 18 recites “the comparison logic”, which should be -- the comparison logic circuit-- because in this way was previously presented this term in the claim.
Appropriate correction is required.
Claim 10 is objected to because of the following informalities: Claim 10, line 25 recites “the comparison logic”, which should be -- the comparison logic circuit-- because in this way was previously presented this term in the claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 7, 8, 10, 11, 13, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Weimer et al. (US 5,914,542), hereinafter Weimer, in view of Langer (US 2018/0152017).
Regarding claim 1, claim 10 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 2, claim 11 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 4, claim 13 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 7, claim 16 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 8, claim 17 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 10, Weimer discloses (see figures 1-7) an aircraft power distribution system (figure 1, part 110) comprising: at least one engine mounted electric generator (figure 1, part engine mounted electric generator inside of 104) configured to convert rotational energy (figure 1, part engine mounted electric generator inside of 104) within the engine to electrical energy (figure 1, part electrical energy from engine mounted electric generator inside of 104); a power distribution controller (figure 1, part power distribution controller inside of 104) configured to receive the electrical energy from the electric generator (figure 1, part electrical energy from engine mounted electric generator inside of 104), convert (figure 1, part power distribution controller inside of 104) the electrical energy to direct current (DC) energy (figure 1, part power DC energy output to 126 from distribution controller inside of 104; through rectifier array) (column 6; lines 43-65; FIG. 1 in the drawings shows an aircraft electrical energy distribution system in which a super capacitor charging apparatus according to the present invention may be used… an electrical generator or alternator and rectifier array which are represented at 104 in FIG. 1), provide the DC energy (figure 1, part power DC energy output to 126 from distribution controller inside of 104; through rectifier array) to multiple electric subsystems within the aircraft (figure 1, part multiple electric subsystems connected to 126) (columns 6-8; lines 61-67 and 1-67, 1-39), wherein at least one of the electric subsystems (figure 1, parts 118/112 or 116/124) (figure 2a/b, parts 200, 202 and 204) is configured to convert the received DC power to a different DC voltage and current using a DC-DC converter (figure 2a/b, parts 200, 202 and 204; through boost DC/DC converter 204); wherein the DC-DC converter (figure 2a/b, parts 200, 202 and 204) comprises an input capacitor (figure 2a/b, part 202) connected across a positive input terminal (figure 2a/b, part upper positive + input terminal 202) and a return input terminal (figure 2a/b, part lower return - input terminal of 202); a DC-DC converter circuit (figure 2a/b, part 204) connected across the positive input terminal (figure 2a/b, part upper positive + input terminal at upper terminal of 202) and the return input terminal (figure 2a/b, part lower return - input terminal at lower terminal of 202); a current limiter (figure 2a/b, part current limiter inside of 200) (figure 5) comprising: a reference threshold portion (figure 5, part reference threshold portion generated by R1/D1) connected across the positive input terminal (figure 5, part upper positive + input terminal at upper terminal of R1) and the return input terminal (figure 5, part lower return - input terminal at upper terminal of D1) and including a reference node (figure 5, part reference node at middle point between R1 and D1); and a first comparison input of a comparison logic circuit (figure 5, part inverting input of comparison logic circuit generated by A1) via a voltage divider (figure 5, part feedback from voltage divider that connect output with inverting terminal of A1) (column 11; lines 12-16; A resistive voltage divider can be used in the negative feedback loop of the operational amplifier), a feedback output (figure 5, part feedback from voltage divider that connect output with inverting terminal of A1) dependent on a voltage differential (figure 5, part feedback from voltage divider that connect output with inverting terminal of A1) between the positive input terminal (figure 2a/b, part upper positive + input terminal at upper terminal of 202) and the return input terminal (figure 2a/b, part lower return - input terminal at lower terminal of 202; the comparison logic circuit (figure 5, part comparison logic circuit generated by A1) including a comparator (figure 5, part A1) having the first comparison input (figure 5, part inverting input of A1) and a second comparison input (figure 5, part non-inverting input of A1), and a second comparison input (figure 5, part non-inverting input of A1) connected to the reference node (figure 5, part voltage in the reference node at middle point between R1 and D1), wherein the comparison logic (figure 5, part comparison logic circuit generated by A1) is configured to generate a comparison output (figure 5, part output of A1) (column 11, lines 8-9; The operational amplifier A1, 314 is used as a voltage comparator); and an active current limiting portion (figure 5) including a current limiting transistor (figure 5, part Q1) connected to at least one of the positive input terminal or the return input terminal (figure 5, part upper positive + input terminal at upper terminal of 202), and configured to limit a current (figure 5, part through Q1 and Rs) on the at least one of the positive input terminal or the return input terminal (figure 5, part upper positive + input terminal at upper terminal of 202) (figures 4a-4d and 7a-7c) (columns 4 and 5; lines 8-67 and 1-17).
Weimer does not expressly disclose a difference amplifier circuit including a connection to the positive input terminal, a connection to the return input terminal, a first operational amplifier (op-amp) including an inverting input connected to the return input terminal and a non-inverting input connected to the positive input terminal, and wherein an output of the first op-amp is connected to a first comparison input of a comparison logic circuit, the difference amplifier circuit being configured to generate a feedback output dependent on a voltage differential between the positive input terminal and the return input terminal.
Langer teaches (see figures 1-3) a difference amplifier circuit (figure 2, part 30) including a connection to the positive input terminal (figure 2, part positive input terminal at upper terminal of CP), a connection to the return input terminal (figure 2, part return input terminal at lower terminal of CP), a first operational amplifier (op-amp) (figure 2, part 70) including an inverting input (figure 2, part 70; inverting input) connected to the return input terminal (figure 2, part return input terminal at lower terminal of CP) and a non-inverting input (figure 2, part 70; non-inverting input) connected to the positive input terminal (figure 2, part positive input terminal at upper terminal of CP), and wherein an output of the first op-amp (figure 2, part 70; output) is connected to a first comparison input of a comparison logic circuit (figure 2, part inverting input of 20), the difference amplifier circuit (figure 2, part 30) being configured to generate a feedback output (figure 2, part VINN_OA2) dependent on a voltage differential (figure 2, part 30) between the positive input terminal (figure 2, part positive input terminal at upper terminal of CP) and the return input terminal (figure 2, part return input terminal at lower terminal of CP); the comparison logic circuit (figure 2, part 20) including a comparator (figure 2, part 20) having the first comparison input (figure 2, part inverting input of 20) and a second comparison input (figure 2, part non-inverting input of 20), wherein the comparison logic (figure 2, part 20) is configured to generate a comparison output (figure 2, part 20; output).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to incorporate the difference amplifier circuit stage as taught by Langer to the feedback loop of the current limiter of Weimer (more specific: incorporate the difference amplifier circuit stage 30 as taught by Langer to feedback loop of Weimer between upper/lower connections of input capacitor 202 and the voltage divider that connect output with inverting terminal of A1) and obtain an aircraft power distribution system comprising: at least one engine mounted electric generator configured to convert rotational energy within the engine to electrical energy; a power distribution controller configured to receive the electrical energy from the electric generator, convert the electrical energy to direct current (DC) energy, provide the DC energy to multiple electric subsystems within the aircraft, wherein at least one of the electric subsystems is configured to convert the received DC power to a different DC voltage and current using a DC-DC converter; wherein the DC-DC converter comprises an input capacitor connected across a positive input terminal and a return input terminal; a DC-DC converter circuit connected across the positive input terminal and the return input terminal; a current limiter comprising: a reference threshold portion connected across the positive input terminal and the return input terminal and including a reference node; a difference amplifier circuit including a connection to the positive input terminal, a connection to the return input terminal, a first operational amplifier (op-amp) including an inverting input connected to the return input terminal and a non-inverting input connected to the positive input terminal, and wherein an output of the first op-amp is connected to a first comparison input of a comparison logic circuit via a voltage divider, the difference amplifier circuit being configured to generate a feedback output dependent on a voltage differential between the positive input terminal and the return input terminal; the comparison logic circuit including a comparator having the first comparison input and a second comparison input, and a second comparison input connected to the reference node, wherein the comparison logic is configured to generate a comparison output; and an active current limiting portion including a current limiting transistor connected to at least one of the positive input terminal or the return input terminal, and configured to limit a current on the at least one of the positive input terminal or the return input terminal, because it provides more accurate feedback detection in order to obtain more efficient current limiter control (paragraph [0022]).
Regarding claim 11, Weimer and Langer teach everything claimed as applied above (see claim 10). Further, Weimer discloses (see figures 1-7) the active current limiting portion (figure 5) is a high side current limiter (figure 5), is connected to the positive input terminal (figure 5, part upper positive + input terminal at upper terminal of 202), and the current limiting transistor (figure 5, part Q1) is configured to interrupt the positive input terminal (figure 5, part upper positive + input terminal at upper terminal of 202).
Regarding claim 13, Weimer and Langer teach everything claimed as applied above (see claim 10). Further, Weimer discloses (see figures 1-7) the positive input terminal (figures 2a/b and 5, part upper positive + input terminal at upper terminal of 202) and the return input terminal (figures 2a/b and 5, part lower return - input terminal at lower terminal of 202) corresponds to a charging state of the input capacitor (figures 2a/b and 5, part 202). However, Weimer does not expressly disclose the voltage differential.
Langer teaches (see figures 1-3) the voltage differential (figure 2, part 30) between the positive input terminal (figure 2, part positive input terminal at upper terminal of CP and the return input terminal (figure 2, part return input terminal at lower terminal of CP) corresponds to a charging state of the input capacitor (figure 2, part CP).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to incorporate the difference amplifier circuit stage as taught by Langer to the feedback loop of the current limiter of Weimer and obtain the voltage differential between the positive input terminal and the return input terminal corresponds to a charging state of the input capacitor, because it provides more accurate feedback detection in order to obtain more efficient current limiter control (paragraph [0022]).
Regarding claim 16, Weimer and Langer teach everything claimed as applied above (see claim 10). Further, Weimer discloses (see figures 1-7) the current limiter (figure 2a/b, part current limiter inside of 200) (figure 5) is configured to set current limiting transistor off (figure 5, part Q1; off state) when the comparison outputs a low signal (figure 5, part output of A1 is low signal) and wherein the current limiter (figure 5) is configured to set the current limiting transistor mode (figure 5, part Q1; at current limiting transistor mode) to follow a bias voltage of the active limiting circuit (figure 5) when the comparison outputs a high signal (figure 5, part output of A1 is high signal) (figures 4a-4d).
Regarding claim 17, Weimer and Langer teach everything claimed as applied above (see claim 10). Further, Weimer discloses (see figures 1-7) the comparison logic circuit (figure 5, part comparison logic circuit generated by A1) is configured to output low (figure 5, part output of A1 is low signal) in response to the first comparison input (figure 5, part inverting input of A1) exceeding the second comparison input (figure 5, part non-inverting input of A1) and configured to output high (figure 5, part output of A1 is high signal) in response to the second comparison input (figure 5, part non-inverting input of A1) exceeding the first comparison input (figure 5, part inverting input of A1) (figures 4a-4d).
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Weimer et al. (US 5,914,542), hereinafter Weimer, in view of Langer (US 2018/0152017), and further in view of Brereton et al. (US 2010/0171468), hereinafter Brereton.
Regarding claim 3, claim 12 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 12, Weimer and Langer teach everything claimed as applied above (see claim 10). Further, Weimer discloses (see figures 1-7) the active current limiting portion (figure 5) is a high side current limiter (figure 5), is connected to the positive input terminal (figure 5, part upper positive + input terminal at upper terminal of 202), and the current limiting transistor (figure 5, part Q1) is configured to interrupt the positive input terminal [based on objection presented above] (figure 5, part upper positive + input terminal at upper terminal of 202). However, Weimer does not expressly disclose the active current limiting portion is a low side current limiter, and the current limiting transistor is configured to interrupt the negative input terminal.
Brereton teaches (see figures 1-6) the active current limiting portion (figure 4, part active current limiting portion generated by 420/440) is a low side current limiter (figure 4, part active current limiting portion generated by 420/440), and the current limiting transistor (figure 4, part 420) is configured to interrupt the negative input terminal (figure 4, part negative terminal) (paragraphs [0048-[0050]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the active current limiting portion of Weimer with the low side current limiter features as taught by Brereton and obtain the active current limiting portion is a low side current limiter, and the current limiting transistor is configured to interrupt the negative input terminal, because it provides another efficient alternative of limiting current at negative side (paragraph [0048]).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Weimer et al. (US 5,914,542), hereinafter Weimer, in view of Langer (US 2018/0152017), and further in view of Miyazaki (US 2003/0184266).
Regarding claim 6, claim 15 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 15, Weimer and Langer teach everything claimed as applied above (see claim 10). Further, Weimer discloses (see figures 1-7) the reference threshold portion (figure 5, part reference threshold portion generated by R1/D1) comprises a resistor (figure 5, part R1) connecting the positive input terminal (figure 5, part upper positive + input terminal at upper terminal of R1) to the reference node (figure 5, part reference node at middle point between R1 and D1) and a diode (figure 5, part D1) connecting the reference node (figure 5, part reference node at middle point between R1 and D1) to the return input terminal (figure 5, part lower return - input terminal at upper terminal of D1). However, Weimer does not expressly disclose a capacitor.
Miyazaki teaches (see figures 1-17) the reference threshold portion (figure 5, part reference threshold portion generated by R1/C1) comprises a resistor (figure 5, part R1) connecting the positive input terminal (figure 5, part upper terminal of R1) to the reference node (figure 5, part lower terminal of R1) and a capacitor (figure 5, part C1) connecting the reference node (figure 5, part lower terminal of R1) to the return input terminal (figure 5, part lower terminal of C1).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the reference portion of Weimer with the reference portion features as taught by Miyazaki and obtain the reference threshold portion comprises a resistor connecting the positive input terminal to the reference node and a capacitor connecting the reference node to the return input terminal, because it provides more accurate reference voltage in order to improve the reliability and quality of the control (Abstract).
Response to Arguments
Applicant's arguments filed 12/05/2025 have been fully considered but they are not persuasive.
Applicant’s argues on pages 8-9 of the Applicant's Response (“First, the rationale relied on by the examiner is not established in the reference… Second, the claims include not only the difference amplifier, but particular connections of the difference amplifier to the other portions of the circuit. The examiner has not explained why it would have been obvious to connect the alleged difference amplifier to the remainder of the circuit in the claimed manner… For this reason as well, prima facie obviousness of the claimed features has not been established”).
The Examiner respectfully disagrees with Applicant’s arguments, because the 103 rejection of Weimer and Langer meet with the claimed limitation. First point, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the primary reference Weimer discloses almost all the stage of the DC-DC converter (figure 2a/b, parts 200, 202 and 204) with the comparison logic circuit (figure 5, part comparison logic circuit generated by A1) including a comparator (figure 5, part A1) having the first comparison input (figure 5, part inverting input of A1) and a second comparison input (figure 5, part non-inverting input of A1), and a second comparison input (figure 5, part non-inverting input of A1) connected to the reference node (figure 5, part voltage in the reference node at middle point between R1 and D1), and the first comparison input of a comparison logic circuit (figure 5, part inverting input of comparison logic circuit generated by A1) detect the voltage of the input capacitor (figure 5, part 202) via a voltage divider (figure 5, part feedback from voltage divider that connect output with inverting terminal of A1) (column 11; lines 12-16; A resistive voltage divider can be used in the negative feedback loop of the operational amplifier); wherein the comparison logic (figure 5, part comparison logic circuit generated by A1) is configured to generate a comparison output (figure 5, part output of A1) (column 11, lines 8-9; The operational amplifier A1, 314 is used as a voltage comparator); and an active current limiting portion (figure 5) including a current limiting transistor (figure 5, part Q1) connected to at least one of the positive input terminal or the return input terminal (figure 5, part upper positive + input terminal at upper terminal of 202), and configured to limit a current (figure 5, part through Q1 and Rs) on the at least one of the positive input terminal or the return input terminal (figure 5, part upper positive + input terminal at upper terminal of 202) (figures 4a-4d and 7a-7c) (columns 4 and 5; lines 8-67 and 1-17). Langer teaches the difference amplifier circuit stage (figure 2, part 30) that including a connection to the positive input terminal (figure 2, part positive input terminal at upper terminal of CP), a connection to the return input terminal (figure 2, part return input terminal at lower terminal of CP), a first operational amplifier (op-amp) (figure 2, part 70) including an inverting input (figure 2, part 70; inverting input) connected to the return input terminal (figure 2, part return input terminal at lower terminal of CP) and a non-inverting input (figure 2, part 70; non-inverting input) connected to the positive input terminal (figure 2, part positive input terminal at upper terminal of CP), and wherein an output of the first op-amp (figure 2, part 70; output) is connected to a first comparison input of a comparison logic circuit (figure 2, part inverting input of 20). It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to incorporate the difference amplifier circuit stage as taught by Langer to the feedback loop of the current limiter of Weimer (more specific: incorporate the difference amplifier circuit stage 30 as taught by Langer to feedback loop of Weimer between upper/lower connections of input capacitor 202 and the voltage divider that connect output with inverting terminal of A1), because it provides more accurate feedback detection in order to obtain more efficient current limiter control (paragraph [0022]). The difference amplifier circuit (figure 2, part 30), as taught Langer, provides more accurate feedback detection because this stage detects the voltage and amplify the detection in order to obtain better measurement accuracy. Second point, as discussed above, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to incorporate the difference amplifier circuit stage as taught by Langer to the feedback loop of the current limiter of Weimer (more specific: incorporate the difference amplifier circuit stage 30 as taught by Langer to feedback loop of Weimer between upper/lower connections of input capacitor 202 and the voltage divider that connect output with inverting terminal of A1), because it provides more accurate feedback detection in order to obtain more efficient current limiter control (paragraph [0022]). By the incorporation of the difference amplifier circuit stage 30 of Langer to the feedback loop of Weimer, the measurement of the voltage at the input capacitor 202 is provided with more precision that result in more efficient current limiter control. Furthermore, this difference amplifier circuit stage is very common in this type of current limiting circuits (for evidence about this statement see reference Warnes (US 2022/0149736; Figure 2, parts A201 and a202)). Therefore, it would have been obvious to one having ordinary skill in the art to combine Weimer and Langer and obtain the claimed limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838