DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-14) in the reply filed on 2-17-2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 10-11, and 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fuergut (US 2020/0013723).
[claim 1] A power semiconductor device (fig. 7), comprising: a semiconductor substrate (1110, fig. 7, [0108]); a signal routing structure (1132, fig. 7, [0211]) disposed above the semiconductor substrate, the signal routing structure comprising a specific metal (e.g. Cu, [0212]); a solderable power pad (1150, fig. 7, which is a source power pad, see fig. 7 which shows contact to source region 1121 [0116]) forming a power terminal of the power semiconductor device (fig. 7), the solderable power pad comprising the specific metal (e.g. Cu, [0134]) ; and an electrically insulating dielectric passivation layer (1140, fig. 7, [0119]) disposed between the solderable power pad and the signal routing structure.
[claim 2] The power semiconductor device of claim 1, wherein the specific metal is Cu [0134][0212].
[claim 3] The power semiconductor device of claim 1, wherein a cross section of the signal routing structure is partly or fully overlaid by the solderable power pad (fig. 7).
[claim 4] The power semiconductor device of claim 1, wherein the signal routing structure is a gate or sense signal connection structure (gate line, 1132, fig. 7, [0211]).
[claim 5] The power semiconductor device of claim 1, wherein the dielectric passivation layer is free of organic dielectric materials (silicon oxide, [0119]).
[claim 6] The power semiconductor device of claim 1, wherein the dielectric passivation layer comprises silicon nitride and/or silicon oxide (silicon oxide, [0119]) and/or silicon oxi-nitride.
[claim 7] The power semiconductor device of claim 1, wherein the signal routing structure is made of a layer stack comprising an adhesion layer and/or barrier layer and a layer of the specific metal arranged over the adhesion layer and/or barrier layer (e.g. [0211] allows for layer combinations of TiN and Cu such a stack of a Cu over TiN).
[claim 8] The power semiconductor device of claim 7, wherein the adhesion layer and/or barrier layer comprises a layer of TiW and/or Ti and/or W and/or TiN and/or Ta (e.g. [0211] allows for layer combinations of TiN and Cu such a stack of a Cu over TiN).
[claim 10] The power semiconductor device of claim 1, further comprising: a bottom insulating dielectric layer (1131, fig. 7, [0116]) disposed between the semiconductor substrate and the signal routing structure, wherein the dielectric passivation layer together with the bottom insulating dielectric layer hermetically enclose an edge section of the signal routing structure (fig. 7).
[claim 11] The power semiconductor device of claim 1, wherein the solderable power pad has a thickness of 1 to 20 um [0213].
[claim 13] The power semiconductor device of claim 1, wherein the power semiconductor device is a vertical device (fig. 7) or a lateral device.
[claim 14] The power semiconductor device of claim 1, wherein the power semiconductor device is an IGBT, MOSFET [0108], JFET, P-FET, N-FET, AFET, planar gate transistor, field plate trench transistor, or super junction transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fuergut (US 2020/0013723).
Fuergut discloses the semiconductor device of claim 7 but does not expressly disclose that the layer of the specific metal has a thickness of 0.2 to 5 um.
Nevertheless it would have been obvious to one of ordinary skill before the time of filing to have made the layer of the specific metal is 0.2 to 5 um, since it has been held that where the general conditions of a claim are disclosed in prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It also been held that the normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages. In re Peterson, 315 F.3d 1325, 1330 (Fed. Cir. 2003). The claimed range is a result-effective variable since the thickness of the specific metal layer affects the amount of space the device takes up.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fuergut (US 2020/0013723) in view of Cheng (US 2017/0317080).
Fuergut discloses the semiconductor device of claim 1 and that insulation 1140 comprising the silicon oxide dielectric passivation layer [0119], may be a multilayer stack layer of different materials with the bottom of the stack including silicon oxide [0119]. Fuergut, however, does not expressly disclose that one of the layer of the stack may be an organic dielectric layer.
Cheng discloses a semiconductor device wherein the ILD (72, fig. 13) over the gate electrode (38, fig. 13) and active area (22, fig. 13) is made of a organic dielectric and/or silicon oxide [0060].
It would have been obvious to one of ordinary skill in the art before the time of filing to made the ILD layer comprise an organic dielectric in order to make them biocompatible (e.g. for medical devices).
With this modification Feurgut discloses:
[claim 12] The power semiconductor device of claim 1, further comprising: an organic dielectric layer (upon modification) disposed over the dielectric passivation layer, wherein the organic dielectric layer does not significantly undercut the solderable power pad (the power pad would remain the same upon modification).
Conclusion
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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