DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to Applicant’s Amendment filed on 6/10/2026.
Claims 1-2, 4-9 and 11-14 are presented for examination. Claims 1 and 8 have been amended. Claims 3 and 10 have been cancelled.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Objections
Claims 1-2, 4-9 and 11-14 are objected to because of the following informalities:
“a number of NUMA nodes” at lines 6-7 of claim 1 and “Non-Uniform Memory Access (NUMA) nodes” at line 10 of claim 1 should be: a number of Non-Uniform Memory Access (NUMA) nodes and NUMA nodes respectively.
Claims 2 and 4-7 are objected for failing to cure the deficiency from their respective parent claim by dependency.
“Non-Uniform Memory Access (NUMA) nodes” at lines 6-7 of claim 8 should be: NUMA nodes.
Claims 9 and 11-14 are objected for failing to cure the deficiency from their respective parent claim by dependency.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Collier (US 20210374208 A1) in view of Shah et al. (US 20210342673 A1, hereafter Shah), Lo et al. (US 20200210839 A1, hereafter Lo), Singh et al. (US 20190102419 A1, hereafter Singh) and Meng et al. (CN110704542A-publication date: 1/17/2020 -English translation provided by Google Patents).
Regarding to claim 1, Collier discloses: A method for machine-learning parallelization using host CPUs of a multi-socket structure, performed by an apparatus for machine-learning parallelization using host CPUs of a multi-socket structure (see Fig. 1, [0025]; “the computer system 100 may perform processing to compute the product of two matrixes … the matrix-matrix multiplication may be used for a number of different applications, such as machine learning … As part of this execution, the computations are performed in a parallel fashion by the processing threads”. Also see [0021], [0023]; “a NUMA architecture-based computer system 100 includes processor sockets 110, NUMA nodes 114, and processing threads. More specifically, in accordance with some implementations, the computer system 100 may include multiple processor sockets 110, where, in this context, a “socket” refers to a CPU semiconductor package (or “chip”)” and “a given CPU core 120 may execute a processing thread in parallel with other CPU cores 120 that are executing other processing threads”), comprising:
performing a compile phase (see [0001], [0025]; “a specialized math library that provides programs to support arithmetic operations in a wide variety of engineering, data mining, numeric processing, data analytics and machine learning applications. One such program may implement a version of a generalized matrix-matrix multiplication (GEMM) algorithm for purposes of performing matrix-matrix multiplication” and “the computer system 100 may perform processing to compute the product of two matrixes … the matrix-matrix multiplication may be used for a number of different applications, such as machine learning”. It is understood that in order to actually execute or run a software program described by [0001] and [0025] at computing fields, there will be at least performing a compile phase),
a learning model is split at [a layer level] for respective pipeline stages and the learning model is allocated to Non-Uniform Memory Access (NUMA) nodes for respective CPU sockets (see [0017], [0019]-[0020]; “a matrix-matrix multiplication are partitioned in a way to divide up the processing workload of the matrix-matrix multiplication for better performance … The first phase involves considering different ways in which matrices involved in the matrix-matrix multiplication may be partitioned, with each way being considered a potential, or candidate, decomposition of matrices (also called a “candidate matrix decomposition” herein). The candidate matrix decompositions correspond to different workload distributions among the sockets”, “to determine how to distribute the workload among the NUMA nodes of each socket” and “to determine how to distribute the processing workload among processing threads”. Note: based on the feature of matrix-matrix multiplication can be used for machine learning application discussed at [0025], the splitting of matrix-matrix multiplication discussed at [0017] can be splitting a learning model of the machine-learning model); and
performing a runtime phase in which multiple threads generated in consideration of a policy of each parallelism algorithm are executed by being allocated to multiple cores included in the NUMA node (see [0020]; “to determine how to distribute the processing workload among processing threads … involve evaluating candidate thread decompositions and selecting the candidate thread decomposition that has the lowest processing cost according to a fitness function”. Also see [0016] and [0025]; “For matrix-matrix computations, the computer system may employ a generalized matrix-matrix multiplication (GEMM) algorithm that relies on different processing threads (on corresponding NUMA nodes and sockets)” and “As part of this execution, the computations are performed in a parallel fashion by the processing threads”).
Collier does not disclose: the compile phase in which:
the learning model is split at a layer level;
a default value for a number of pipeline stages is set to correspond to a number of NUMA nodes,
an equal number of model operations is distributed to each of the NUMA nodes, and
the learning model is allocated to NUMA nodes
(note: Collier actually does teach features of a compile phase, and splitting or partitioning learning model and allocating the partitioned learning model to NUMA nodes for CPU sockets, but Collier does not specify such splitting and allocating is performed within the compile phase);
performing a runtime phase in which parameters required for learning are initialized.
However, Shah discloses: performing a compile phase in which: a learning model is split at a layer level for respective pipeline stages, and the learning model is allocated to worker nodes for respective CPU resources (see [0022]-[0023]; “A compiler receives 110 a description of a machine learning network and generates the computer program that implements the machine learning network. The compiler allocates 112 computations to different processing elements in the MLA for execution such that different groups of processing elements implement different layers of the machine learning network”, “the compiler can determine which instructions are executed by which processing elements at what times”. Also see [0058]; “The compiler 320 may also optimize 324 the computer program 350 … Partitioning 328 concerns mapping the computations in the MLN to an implementation on the MLA. This includes determining which computations are allocated to which Tiles and how data flows through the mesh of Tiles during computation”)
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the compiling phase, task decomposition and allocation performed from Collier by including compiling phase to including allocating different layers of a machine learning workload to different processor resources from Shah, since it would provide a specific compilating phase to ensure data transfer instruction are not conflicting (see [0023] from Shah; “For each data transfer, the compiler analyzes all possible data transfer paths and generates a non-colliding data transfer path. Because the compiler can determine these at compile-time rather than at run-time, it can ensure that the data transfer instructions are not conflicting”).
In addition, Lo discloses: performing a runtime phase in which parameters required for learning are initialized (see [0091], “parameters, such as weights and biases, of the neural network can be initialized. As one example, the weights and biases can be initialized to random normal-precision floating-point values. As another example, the weights and biases can be initialized to normal-precision floating-point values that were calculated from an earlier training set”. Note: although the description of [0091] does not actually state that [0091] is performed during the runtime phase, according to the context of [0090]-[0100], it is understood that method 600 including the parameter initialization step is performed during the runtime phase of the neural network, i.e., the phase of training a neural network, instead of compiling phase of the neural network. Actually, “the weights and biases can be initialized to normal-precision floating-point values that were calculated from an earlier training set” from [0091] also implies that the parameter initialization step is performed during runtime phase).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the runtime phase performed from the combination of Collier and Shah by including runtime phase to initialize different parameter required for the neural network model from Lo, since it would provide a flexible system that is able initializing operation parameter via different initialization mechanisms (see [0091] from Lo; “As one example, the weights and biases can be initialized to random normal-precision floating-point values. As another example, the weights and biases can be initialized to normal-precision floating-point values that were calculated from an earlier training set”).
In addition, Singh discloses: performing a resource allocation determination phase in which: a default value for a number of parallelism stages is set to correspond to a number of [NUMA] nodes (see [0024]; “By applying a forced high degree of parallelism at steps 114 and 116, an embodiment of the present invention achieves increased and improved performance. The forced parallelism enables the system to distribute the processing to a full number of data nodes, as opposed to a small subset”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the parallelism level from the combination of Collier, Shah and Lo by including executing under a forced high degree of parallelism from Singh, since it would provide a mechanism of utilizing all of worker nodes for achieve highest parallelism (see [0024] from Singh).
In addition, Meng discloses: performing a partitioning phase in which: an equal number of model operations is distributed to each of the [NUMA] nodes (see [0105]; “In the data pre-partitioning stage, the default partitioning mode of the MemSql is that the number of partitions of each node is the same”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the initial workload distribution from the combination of Collier, Shah, Lo and Singh by including evenly distributing same amount of operations to each worker node from Meng, and thus the combination of Collier, Shah, Lo, Singh and Meng would disclose the missing limitations of Collier, since it would provide an default initial workload distribution method (see [0104]-[0105] from Meng).
Regarding to Claim 2, the rejection of Claim 1 is incorporated and further the combination of Collier, Shah, Lo, Singh and Meng discloses:
the NUMA node for each of the CPU sockets includes a CPU, including multiple cores, and memory (see Fig. 1, [0014]-[0015] and [0021] from Collier; “a NUMA architecture recognizes that processing nodes have faster access times to local memories than to non-local memory” and “a “socket” refers to a CPU semiconductor package (or “chip”) … The socket 110, or CPU semiconductor package, contains one or multiple CPU cores 120 (also called “processing cores” herein), as well as additional circuits, such as caches, interconnects, and a local memory 116”),
the multiple cores share the memory via an interconnect between the cores (see Fig. 1, [0014]-[0015] and [0021] from Collier; “The socket 110, or CPU semiconductor package, contains one or multiple CPU cores 120 (also called “processing cores” herein), as well as additional circuits, such as caches, interconnects, and a local memory 116”), and
the NUMA node for each of the CPU sockets shares memory of each NUMA node via an interconnect between the sockets (see [0044], [0051] from Collier; “the engine 140 assigns NUMA node masks for shared buffer allocations”, “the GEMM engine 134 uses shared data structures that are explicitly local to a given NUMA node 114, if possible, to help further improve data locality and reduce contention”).
Regarding to Claim 8, Claim 8 is a system claim corresponds to method Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above (note: also see Fig. 11 and [0054] of Collier for claimed “a processor” and “memory”).
Regarding to Claim 9, Claim 9 is a system claim corresponds to method Claim 2 and is rejected for the same reason set forth in the rejection of Claim 2 above.
Claims 4, 6-7 and 11 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Collier (US 20210374208 A1) in view of Shah et al. (US 20210342673 A1, hereafter Shah), Lo et al. (US 20200210839 A1, hereafter Lo), Singh et al. (US 20190102419 A1, hereafter Singh) and Meng et al. (CN110704542A-publication date: 1/17/2020 -English translation provided by Google Patents) and further in view of Zheng et al. (US 20220044112 A1, hereafter Zheng).
Regarding to Claim 4, the rejection of Claim 1 is incorporated, the combination of Collier, Shah, Lo, Singh and Meng does not disclose: wherein the parameters include global parameters for sharing data between the multiple threads and local parameters used individually by each of the multiple threads.
However, Zheng discloses: wherein the parameters include global parameters for sharing data between the multiple threads and local parameters used individually by each of the multiple threads (see [0005]; “the computing system may use the worker threads to perform training operations. The training operations may comprise generating, for each of the trainers, an updated local version of the parameters using the worker thread associated with that trainer. While the worker threads are performing training operations, the computing system may use the synchronization threads to perform synchronization operations. In particular embodiments, the synchronization operations may comprise generating a global version of the parameters based on the updated local versions of the parameters and generating, for each of the trainers, a synchronized local version of the parameters based on the global version of the parameters”. Note: the claim 4 now only requires there are global parameters that are shared among multiple threads and local parameters used by each individual thread. The current claimed language from claim 4 does not require the claimed global parameters and the claimed local parameters are different types of parameters indicating different meanings. Thereby, feature related to global version of parameters and local version of parameters from Zheng is still reasonable to teach what is claimed now under BRI. Also see [0002], [0044]; “In parallel computing, all processors may have access to a shared memory to exchange information between processors. In distributed computing, each processor has its own private memory (distributed memory)” and “The trainers are the workers who control the training loop. In particular embodiments, the trainers may be associated with a shared reader service. The shared reader service may convert a training example to a feature representation used for training the machine-learning model. Each trainer connects to a shared reader service. It has a local queue that fetches new batch of examples from the reader service. The reader service is a distributed system which consumes the raw data in the distributed storage, and then converts the raw data to feature tensors after the feature engineering step so that the trainers can focus on training without being bottlenecked on the data reading”, “In the model parallelism regime, the worker threads may access the shared parameters in the embedding PSs”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the runtime phase performed from the combination of Collier, Shah, Lo, Singh and Meng by including synchronizations of threads for different training stages/portions to update data or parameter among different training stages/portions from Zheng, and thus the combination of Collier, Shah, Lo, Singh, Meng and Zheng would disclose the missing limitations from the combination of Collier, Shah, Lo, Singh and Meng, since it would provide a mechanism of training complicated models to shorten the training time (see [0004] from Zheng).
Regarding to Claim 6, the rejection of Claim 4 is incorporated and further the combination of Collier, Shah, Lo, Singh, Meng and Zheng discloses:
synchronizing execution of the threads allocated to each of the NUMA nodes (see [0005] from Zheng; “While the worker threads are performing training operations, the computing system may use the synchronization threads to perform synchronization operations. In particular embodiments, the synchronization operations may comprise generating a global version of the parameters based on the updated local versions of the parameters and generating, for each of the trainers, a synchronized local version of the parameters based on the global version of the parameters”. Also see [0017], [0019]-[0020] from Collier; “The candidate matrix decompositions correspond to different workload distributions among the sockets”, “to determine how to distribute the workload among the NUMA nodes of each socket” and “to determine how to distribute the processing workload among processing threads”. At the combination system, the different training operations are distributed into different NUMA nodes, and thus after combining feature of thread synchronizations among trainers from Zheng into the combination of Collier, Shah and Lo, the thread synchronization among trainers is actually thread synchronization among NUMA nodes); and
updating the parameters for each of the NUMA nodes based on the global parameters (see [0005] from Zheng; “generating, for each of the trainers, a synchronized local version of the parameters based on the global version of the parameters”).
Regarding to Claim 7, the rejection of Claim 6 is incorporated and further the combination of Collier, Shah, Lo, Singh, Meng and Zheng discloses: wherein updating the parameters comprises updating the parameters using any one of a method in which the multiple threads synchronously update the parameters and a method in which the multiple threads asynchronously update the parameters (see [0005] from Zheng; “While the worker threads are performing training operations, the computing system may use the synchronization threads to perform synchronization operations … generating, for each of the trainers, a synchronized local version of the parameters based on the global version of the parameters”).
Regarding to Claim 11, Claim 11 is a system claim corresponds to method Claim 4 and is rejected for the same reason set forth in the rejection of Claim 4 above.
Regarding to Claim 13, Claim 13 is a system claim corresponds to method Claim 6 and is rejected for the same reason set forth in the rejection of Claim 6 above.
Regarding to Claim 14, Claim 14 is a system claim corresponds to method Claim 7 and is rejected for the same reason set forth in the rejection of Claim 7 above.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Collier (US 20210374208 A1) in view of Shah et al. (US 20210342673 A1, hereafter Shah), Lo et al. (US 20200210839 A1, hereafter Lo), Singh et al. (US 20190102419 A1, hereafter Singh), Meng et al. (CN110704542A-publication date: 1/17/2020 -English translation provided by Google Patents), and Zheng et al. (US 20220044112 A1, hereafter Zheng) and further in view of Cha et al. (US 20230153624 A1, hereafter Cha).
Regarding to Claim 5, the rejection of Claim 4 is incorporated, the combination of Collier, Shah, Lo, Singh, Meng and Zheng does not disclose: wherein the local parameters store a gradient for loss and a state of an optimizer for determining whether to apply the gradient, which are used in a backpropagation process of the learning model.
However, Cha discloses: wherein the local parameters store a gradient for loss (see [0097] and [0109]; “the backpropagation performing unit 184 may update the first parameter PAR1 and the second parameter PAR2 for each layer of the neural network by using a gradient (a differential value) of each loss function”) and a state of an optimizer for determining whether to apply the gradient, which are used in a backpropagation process of the learning model (see [0095]; “adjust a loss LS for the prediction value PVL so as to be a minimum value. When the loss LS becomes the minimum value, the prediction value PVL may be output as a tracking result for the object”. Also see [0097] and [0106]-[0109]; “perform backpropagation based on the loss LS adjusted by the loss adjusting unit 182. For example, the backpropagation performing unit 184 may update the first parameter PAR1 and the second parameter PAR2 for each layer of the neural network by using a gradient (a differential value) of the loss function”. The backpropagation operation discussed at [0097] and [0109] to apply the gradient for loss function is performed based on the adjusted loss LS, and thus the “minimum value” for the adjusted LS is reasonable to be considered as local parameter that indicates state of an optimizer for determining whether to apply the gradient used in a backpropagation process).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the local parameters of each trainer or layers and loss parameter determination from the combination of Collier, Shah, Lo, Singh, Meng and Zheng (note: see [0066]-[0078] from Zheng about determining loss values for the trainers) by including backpropagation operation based on gradient of loss function from Cha, and thus the combination of Collier, Shah, Lo, Singh, Meng, Zheng and Cha would disclose the missing limitations from the combination of Collier, Shah, Lo, Singh, Meng and Zheng, since it would provide a mechanism of continuing reduce loss function to achieve minimal loss (see [0095]-[0097] and [0106]-[0109] from Cha).
Regarding to Claim 12, Claim 12 is a system claim corresponds to method Claim 5 and is rejected for the same reason set forth in the rejection of Claim 5 above.
Response to Arguments
Applicant’s arguments, filed 6/10/2026, with respect to rejections of claims 1-2, 4-9 and 11-14 under 35 U.S.C. 103 have been full considered but they are not persuasive.
Applicant’s arguments at pages 6-9 are summarized as the following:
The independent claim 1 is amended to further includes the following limitations “performing a compile phase in which: a learning model is split at a layer level for respective pipeline stage, a default value for a number of pipeline stage is set to correspond to a number of NUMA nodes, an equal number of model operation is distributed to each of the NUMA nodes, and the learning model is allocated to non-Uniform Memory Access (NUMA) nodes for respective CPU sockets” (see page 7 from the Remarks). Applicant argued that “These distinct features are not disclosed or suggested by any of the cited references. Collier discloses distributing workloads among CPU sockets, NUMA nodes, and processing threads in a NUMA-based multi-socket system. However, Collier does not disclose or suggest setting the number of pipeline stages to correspond to the number of NUMA nodes or distributing an equal number of model operations to each NUMA node. Saha relates to compiler-based allocation of machine-learning computations to processing elements in a machine-learning accelerator. However, Shah does not disclose or suggest configuring pipeline stages based on NUMA nodes in a multi-socket host CPU environment. Shah therefore does not address the claimed features. Singh generally discloses increasing parallelism by utilizing available processing nodes. However, Singh does not disclose or suggest setting the number of pipeline stages to correspond to the number of NUMA nodes. Singh therefore does not teach the claimed architecture. Meng relates to distributing workloads among nodes in a distributed environment. Although Meng discloses distributing workloads evenly among nodes, Meng does not disclose setting the number of pipeline stages according to the number of NUMA nodes” (see page 8 from the Remarks).
The examiner respectively disagrees.
The related limitations are actually rejected by the combination of references instead of one particular reference alone. Applicant’s arguments are actually against each reference individually. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant admitted that Collier discloses feature of “distributing workloads among CPU sockets, NUMA nodes” and “Meng discloses distributing workloads evenly among nodes”, and thus the combination of Collier and Meng would at least teach feature of distributing workloads evenly, i.e., “equal number of model operations”, to each NUMA node. Applicant admitted that “Singh generally discloses increasing parallelism by utilizing available processing nodes”, and thus combining such parallelism feature into the combination of Collier and Shah, the new combination would teach feature of configuring pipeline stages based on available NUMA nodes, i.e., “setting the number of pipeline stages to correspond to the number of NUMA nodes”, to increase parallelism.
Therefore, Claims 1-2, 4-9 and 11-14 are rejected.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHI CHEN whose telephone number is (571)272-0805. The examiner can normally be reached on M-F from 9:30AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y Blair can be reached on 571-270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center and the Private Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from Patent Center or Private PAIR. Status information for unpublished applications is available through Patent Center and Private PAIR to authorized users only. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form.
/Zhi Chen/
Patent Examiner, AU2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
Prosecution Insights