Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Comments
The Examiner has cited particular columns and line numbers, paragraphs, or figures in the reference(s) as applied to the claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant, in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 4, 6-8, 10, 11, 13-15, and 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Mix et al. (US 2023/0402990 A1).
As per claim 1 (and as per method claim 8), Mix et al. (US 2023/0402990 A1) discloses a system (e.g. 200, 300 - see Fig. 3), comprising: an array of metal-oxide-semiconductor field effect transistors (MOSFETs) (e.g., see abstract with multiple transmitters, piezoelectric elements; 212, 312 - see, inter alia, Figs. 3, 4, etc.; see also, inter alia, paragraphs [0021, 0038, 0040]) being positioned on a semiconductor material (e.g., 204, 304) with each MOSFET (e.g. 212, 312) including a source region (e.g. 228, 342), a drain region (e.g., 232, 338), and a gate region (e.g., 224, 334) positioned between the source (e.g. 228, 342) and drain (e.g., 232, 338) regions, the gate region (e.g., 224, 334) including a conductive gate electrode and a hafnium silicon oxide (HfSiO) gate dielectric layer (e.g., 318 – see also paragraphs [074, 0075]) positioned between the conductive gate electrode and the semiconductor material (e.g., 204, 304) – see, inter alia, paragraphs [0074, 0075], the HfSiO gate dielectric layer having piezoelectric properties (e.g., see, inter alia, paragraphs [0021, 0040, 0041]); and an acoustic signal generator (e.g., including (208), (308)) coupled to the semiconductor material (e.g., 204, 304) for activating and deactivating (turning the transistor "on" or "off" via the gate) the array of MOSFETs through interaction between an acoustic signal produced by the acoustic signal generator (e.g., including (208), (308)) and the HfSiO gate dielectric layer of each MOSFET (e.g., see, inter alia, paragraphs [0042, 0059, 0074, 0075]).
As per claim 3 (and analogously, as per claim 10), wherein the acoustic signal generator (e.g., including (208), (308)) is coupled to a same side of the semiconductor material (e.g., 204, 304) as the gate region - see, inter alia, paragraphs [0047, 0054].
As per claim 4 (and analogously, as per claim 11), wherein the acoustic signal generator (e.g., including (208), (308)) is coupled to an opposite side of the semiconductor material (e.g., 204, 304) as the gate region see, inter alia, Figs. 2, 3.
As per claim 6 (and analogously, as per claim 13), wherein the MOSFETs are Gate-All-Around type transistors (e.g., see, inter alia, paragraphs [0044, 0068, 0069] - Figs. 11C, 11D).
As per claim 7 (and analogously, as per claim 14), wherein the MOSFETS are Fin field-effect type transistors (e.g., see, inter alia, paragraph [0044, 0058, 0069, 0071] - Fig. 11B).
Regarding claims 8, 10, 11, 13, and 14, the method steps set forth therein are drawn to the method of coupling the acoustic signal generator and applying signals to the system/device of claims 1, 3, 4, 6, and 7, with such method steps fully disclosed by Mix et al. (US 2023/0402990 A1). Therefore, method claims 8, 10, 11, 13, and 14 (as noted, supra) correspond to the corresponding system of claims 1, 3, 4, 6, and 7 and are rejected for the same reasons of anticipation as used above, with each step being met by the disclosure of Mix et al. (US 2023/0402990 A1).
As per claim 15, Mix et al. (US 2023/0402990 A1) discloses a Metal oxide semiconductor field effect transistor (MOSFET) (e.g., see, inter alia, paragraphs [0021, 0038, 0040]), comprising: a semiconductor substrate (e.g., 204, 304); a source region (e.g. 228, 342); a drain region (e.g., 232, 338); a gate region (e.g., 224, 334) between the source (e.g. 228, 342) and drain regions (e.g., 232, 338), the gate region (e.g., 224, 334) including a conductive gate electrode and a hafnium silicon oxide (HfSiO) gate dielectric layer (e.g., 318 – see also paragraphs [074, 0075]) positioned between the conductive gate electrode and the semiconductor substrate (e.g., 204, 304), the HfSiO gate dielectric layer exhibiting a piezoelectric effect (e.g., see, inter alia, paragraphs [0021, 0040, 0041]); and wherein the MOSFET is configured to receive an acoustic signal at the HfSiO gate dielectric layer, the acoustic signal interacting with the HfSiO gate dielectric layer to activate and deactivate (turning the transistor "on" or "off" via the gate) the MOSFET - through interaction between an acoustic signal produced by the acoustic signal generator (e.g., including (208), (308)) and the HfSiO gate dielectric layer of each MOSFET (e.g., see, inter alia, paragraphs [0042, 0059, 0074, 0075]).
As per claim 17, further including an input including material exhibiting a piezoelectric effect (e.g., including (208), (308)) having a second material exhibiting a piezoelectric effect (e.g., see abstract - "An acoustic transmitter comprises a layer of piezoelectric material that generates an acoustic wave in response to the piezoelectric layer being activated by a clock source signal applied to the acoustic transmitter."; see also paragraphs [0020, 0034, 0036, etc.]), the input being coupled to the semiconductor substrate (e.g., 204, 304) for receiving an acoustic signal e.g., see, inter alia, paragraphs [0042, 0059]), wherein the input (e.g., including (208), (308)) is for receiving the acoustic signal and is coupled to a same side of the semiconductor substrate (e.g., 204, 304) as the gate region - see, inter alia, paragraphs [0047, 0054].
As per claim 18, wherein the aforementioned input (e.g., including (208), (308)) for receiving the acoustic signal is coupled to an opposite side of the semiconductor material (e.g., 204, 304) as the gate region see, inter alia, Figs. 2, 3 as the gate region, inter alia, Figs. 2, 3..
As per claim 19, wherein the MOSFET is a Gate-All-Around type transistor (e.g., see, inter alia, paragraphs [0044, 0068, 0069] - Figs. 11C, 11D).
As per claim 20, wherein the MOSFET is a fin field-effect type transistor (e.g., see, inter alia, paragraph [0044, 0058, 0069, 0071] - Fig. 11B).
Response to Arguments
Applicant's arguments filed September 25, 2026 have been fully considered but they are not persuasive.
The Applicant alleges Mix provides “the acoustic-receiver function through a separately provided piezoelectric structure. Mix identifies exemplary piezoelectric materials in paragraph [0036], but that list does not include HfSiO . . . Accordingly, Mix's acoustic signal is received by either a replacement piezoelectric gate or an additional piezoelectric element, rather than by an HfSiO gate dielectric positioned beneath a conductive gate electrode as presently claimed in claim 1.” See page 10 of the Response.
Additionally, the Applicant opines:
Although Mix identifies hafnium silicon oxide in paragraph [0075], that paragraph merely lists hafnium silicon oxide as one possible high-k gate-dielectric material for a conventional transistor. Mix does not state that the HfSiO gate dielectric is being used as a piezoelectric, receiving an acoustic signal, or interacting with an acoustic signal to activate and deactivate the transistor. The rejection therefore combines Mix's generic disclosure of an HfSiO gate dielectric with an acoustic-receiver function that Mix assigns to materially different piezoelectric structures. Because Mix does not disclose the claimed combination in which the HfSiO gate dielectric itself serves as the piezoelectric acoustic receiver, Mix does not anticipate amended claim 1 or the claims depending therefrom.
See Response at pages 9-10.
The Examiner disagrees. More concretely, Mix expressly states that Fig. 10, and the paragraphs [0074, 0075], are applicable to the other circuits disclosed, including those of Figs. 2 and 3. “FIG. 10 is a cross-sectional side view of an integrated circuit device 1000 that may be included in any of the integrated circuit components disclosed herein.” See paragraph [0067]. Thus, Mix clearly discloses the elements set forth in the claimed invention, and arranged in the manner so claimed, in a single reference. The embodiment and the specific gate structure component (conductive gate electrode and the hafnium silicon oxide (HfSiO) of the embodiment of Fig. 10 of Mix), is applicable to Figs. 3 and 4, as noted by Mix.
Moreover, the material disclosed (i.e., the HfSiO gate dielectric of paragraph [0075]), is useable in the manner set forth by Mix in the other embodiments disclosed by Mix (including, inter alia, Figs. 2, 3). Mix further expressly states, “The gate 334 of the piezoelectric transistor 312 and the piezoelectric element 392 can comprise one or more of any of the piezoelectric materials described herein and/or any other suitable piezoelectric material,” (emphasis added) which includes, of course, the material set forth in paragraph [0075]] (HfSiO). See also, paragraph [0021] of Mix, “a metal-oxide-semiconductor field-effect transistor (MOSFET) in which the gate and gate oxide layers (or just the gate layer) are replaced by a piezoelectric layer that can convert bulk or surface acoustic waves into an electrical signal,” and paragraph [0074] of Mix, “a transistor 1040 may include a gate 1022 formed of at least two layers, a gate dielectric and a gate electrode.”
The Examiner is not combining mutually exclusive elements of one embodiment, and putting such elements into another embodiment, but is relying upon the express disclosure of Mix wherein materials/compositions of one specific integrated circuit/MOSFET, can be used in another integrated circuit MOSFET embodiment, based upon the Mix’s own text.
As such, the claims, as currently drafted, are still seen to be anticipated by Mix for the reasons articulated, supra.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William J Klimowicz whose telephone number is (571)272-7577. The examiner can normally be reached Monday-Thursday, 8:00AM-6PM, ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Lim can be reached at (571)270-1210. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM J KLIMOWICZ/ Primary Examiner, Art Unit 2688
