Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on November 28, 2023. These drawings are objected to as follows:
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: "back voltage 216" (see page 3, line 18 of paragraph [0014]).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
(i) The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
(ii) With regard to page 3 (line 1 of paragraph [0014]), the term "Fig. 1" should be changed to the term --Fig. 2--.
Appropriate correction is required.
Claim Objections
Claims 9, 14, 16, and 18 are objected to because of the following informalities:
(i) With regard to claim 9 (line 1), the term "piezoelectric film" should be changed to the term --piezoelectric material-- in order to remain consistent with preceding claim language.
(ii) Claim 14 should have its claim dependency changed from claim 8 to claim 12, in order to provide proper antecedent basis for the term "the MOSFETS".
(iii) With regard to claim 16 (line 2), the term "semiconductor material" should be changed to the term --semiconductor substrate-- in order to remain consistent with preceding claim language.
(iv) With regard to claim 18 (line 2), the term "semiconductor material" should be changed to the term --semiconductor substrate-- in order to remain consistent with preceding claim language.
Appropriate correction is required.
Examiner Comments
The Examiner has cited particular columns and line numbers, paragraphs, or figures in the reference(s) as applied to the claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant, in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Mix et al. (US 2023/0402990 A1).
As per claim 1 (and as per method claim 8), Mix et al. (US 2023/0402990 A1) discloses a system (e.g. 200, 300 - see Fig. 3), comprising: an array of transistors (e.g., see abstract with multiple transmitters, piezoelectric elements; 212, 312 - see, inter alia, Figs. 3, 4, etc.) being positioned on a semiconductor material (e.g., 204, 304) with each transistor (e.g. 212, 312) including a source region (e.g. 228, 342), a drain region (e.g., 232, 338), and a gate region (e.g., 224, 334) positioned between the source (e.g. 228, 342) and drain (e.g., 232, 338) regions, with the gate region (e.g., 224, 334) including a layer (e.g., 318) of material having piezoelectric properties (e.g., see, inter alia, paragraphs [0021, 0040, 0041]); and an acoustic signal generator (e.g., including (208), (308)) coupled to the semiconductor material (e.g., 204, 304) for activating and deactivating (turning the transistor "on" or "off" via the gate) the array of transistors through interaction between an acoustic signal produced by the acoustic signal generator (e.g., including (208), (308)) and the layer of material having the piezoelectric properties (e.g., see, inter alia, paragraphs [0042, 0059]).
As per claim 2 (and analogously, as per claim 9), wherein the piezoelectric material is an HfSiO dielectric layer between a doped polysilicon or a metal gate of the gate region and the semiconductor material - see paragraphs [0074, 0075].
As per claim 3 (and analogously, as per claim 10), wherein the acoustic signal generator (e.g., including (208), (308)) is coupled to a same side of the semiconductor material (e.g., 204, 304) as the gate region - see, inter alia, paragraphs [0047, 0054].
As per claim 4 (and analogously, as per claim 11), wherein the acoustic signal generator (e.g., including (208), (308)) is coupled to an opposite side of the semiconductor material (e.g., 204, 304) as the gate region see, inter alia, Figs. 2, 3.
As per claim 5 (and analogously, as per claim 12), wherein the array of transistors are Metal oxide semiconductor field effect transistors (MOSFETs) (e.g., see, inter alia, paragraphs [0021, 0038, 0040]).
As per claim 6 (and analogously, as per claim 13), wherein the MOSFETs are Gate-All-Around type transistors (e.g., see, inter alia, paragraphs [0044, 0068, 0069] - Figs. 11C, 11D).
As per claim 7 (and analogously, as per claim 14), wherein the MOSFETS are Fin field-effect type transistors (e.g., see, inter alia, paragraph [0044, 0058, 0069, 0071] - Fig. 11B).
Regarding claims 8-14, the method steps set forth therein are drawn to the method of coupling the acoustic signal generator and applying signals to the system/device of claims 1-7, with such method steps fully disclosed by Mix et al. (US 2023/0402990 A1). Therefore method claims 8-14 (as noted, supra) correspond to the corresponding system of claims 1-7 and are rejected for the same reasons of anticipation as used above, with each step being met by the disclosure of Mix et al. (US 2023/0402990 A1).
As per claim 15, Mix et al. (US 2023/0402990 A1) discloses a Metal oxide semiconductor field effect transistor (MOSFET) (e.g., see, inter alia, paragraphs [0021, 0038, 0040]), comprising: a semiconductor substrate (e.g., 204, 304); a source region (e.g. 228, 342); a drain region (e.g., 232, 338); a gate region (e.g., 224, 334) between the source (e.g. 228, 342) and drain regions (e.g., 232, 338), the gate region (e.g., 224, 334) including a first material exhibiting a piezoelectric effect (e.g., see, inter alia, paragraphs [0021, 0040, 0041]); and an input (e.g., including (208), (308)) having a second material exhibiting a piezoelectric effect (e.g., see abstract - "An acoustic transmitter comprises a layer of piezoelectric material that generates an acoustic wave in response to the piezoelectric layer being activated by a clock source signal applied to the acoustic transmitter."; see also paragraphs [0020, 0034, 0036, etc.]), the input being coupled to the semiconductor substrate (e.g., 204, 304) for receiving an acoustic signal (e.g., see, inter alia, paragraphs [0042, 0059]).
As per claim 16, wherein the first material is an HfSiO dielectric layer between a polysilicon/metal gate of the gate region and the semiconductor material - see paragraphs [0074, 0075]; note: the slash "/" between the terms "polysilicon" and "metal" is being considered to be equivalent to "and/or").
As per claim 17, wherein the input (e.g., including (208), (308)) for receiving the acoustic signal is coupled to a same side of the semiconductor substrate (e.g., 204, 304) as the gate region - see, inter alia, paragraphs [0047, 0054].
As per claim 18, wherein the input (e.g., including (208), (308)) for receiving the acoustic signal is coupled to an opposite side of the semiconductor material (e.g., 204, 304) as the gate region see, inter alia, Figs. 2, 3 as the gate region, inter alia, Figs. 2, 3..
As per claim 19, wherein the MOSFET is a Gate-All-Around type transistor (e.g., see, inter alia, paragraphs [0044, 0068, 0069] - Figs. 11C, 11D).
As per claim 20, wherein the MOSFET is a fin field-effect type transistor (e.g., see, inter alia, paragraph [0044, 0058, 0069, 0071] - Fig. 11B).
Citation of Prior or Relevant Art on enclosed PTO-892
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The cited art made of record (see the enclosed PTO-892), not applied to the rejection of the claims, supra, each disclose aspects of the claimed invention, including wherein transistor gates include piezoelectric materials. See attached PTO-892.
The best prior art has been applied to the claimed invention (see the rejection of the claims on the applied prior art, supra). However, if Applicant chooses to amend the claims in a manner to obviate the applied prior art, as noted in the rejection, supra, the Applicant is advised to not only carefully review the applied prior art for all it teaches and/or suggests, but also the cited prior art of record in order to obviate any potential rejections based on potential amendment(s); by doing so, compact prosecution on the merits can be enhanced.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William J Klimowicz whose telephone number is (571)272-7577. The examiner can normally be reached Monday-Thursday, 8:00AM-6PM, ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Lim can be reached at (571)270-1210. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM J KLIMOWICZ/Primary Examiner, Art Unit 2688
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