DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iwasaki et al. (US publication 2013/0140711 A1), hereinafter referred to as Iwasaki711.
Regarding claim 1, Iwasaki711 teaches an apparatus (fig. 1a-1c and related text), comprising a voltage dividing circuit including: a first resistor unit (R22/R13/R22 on top , fig. 1b); a second resistor unit (R21/R11/R21 on bottom , fig. 1b) parallel to the first resistor unit in a first direction (X or Y direction); and a bridge (R12) between the first resistor unit and the second resistor unit and configured to link a first middle portion (R13) of the first resistor unit to a second middle portion (R11) of the second resistor unit (fig. 1b), the first and second middle portions being middle portions of the first and the second resistor units in a second direction (Y or X direction) perpendicular to the first direction (fig. 1b).
Regarding claim 2, Iwasaki711 teaches wherein the first and second middle portions of the first and the second resistor units are spaced from end portions of the first and second resistor units in the second direction (fig. 1a-1c).
Regarding claim 3, Iwasaki711 teaches wherein the first and second middle portions of the first and the second resistor units are at or around lengthwise centers of the first and second resistor units in the second direction (fig. 1a-1c).
Claim 1 and 4-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hashimoto et al. (US publication 2021/0257443 A1), hereinafter referred to as Hashimoto443.
Regarding claim 1, Hashimoto443 teaches an apparatus (fig. 1-5 & fig. 7 and related text), comprising a voltage dividing circuit including: a first resistor unit (top half of fig. 5); a second resistor unit (bottom half of fig. 5) parallel to the first resistor unit in a first direction (X or Y direction); and a bridge (32_2, [0032]) between the first resistor unit and the second resistor unit and configured to link a first middle portion (31_2) of the first resistor unit to a second middle portion (31_1) of the second resistor unit (fig. 3-5), the first and second middle portions being middle portions of the first and the second resistor units in a second direction (Y or X direction) perpendicular to the first direction (fig. 3-5).
Regarding claim 4, Hashimoto443 teaches wherein each of the first and second resistor units includes: at least a first layer (31_1/31_2) and a second layer (41/42/43) on a semiconductor substrate, the first layer including a resistor, and the second layer including a wiring; and a plurality of contacts (44/45) between the first layer and the second layer (fig. 3-5).
Regarding claim 5, Hashimoto443 teaches wherein the first and second middle portions linked by the bridge are middle portions of at least the second layers of the first and second resistor units (fig. 3-5).
Regarding claim 6, Hashimoto443 teaches wherein in each of the first and second resistor units, at least one of the plurality of contacts is at a middle portion of the second layer (fig. 3-5).
Regarding claim 7, Hashimoto443 teaches wherein in each of the first and second resistor units, the bridge is positioned corresponding to at least one of the contacts at a middle portion of the second layer (fig. 3-5).
Regarding claim 8, Hashimoto443 teaches wherein the bridge includes: a first bridging portion between the first layers of the first and second resistor units; and a second bridging portion between the second layers of the first and second resistor units (fig. 3-5).
Regarding claim 9, Hashimoto443 teaches wherein the first bridging portion and the second bridging portion have portions overlapping with each other in a plan view (fig. 3-5).
Regarding claim 10, Hashimoto443 teaches wherein the voltage dividing circuit includes a plurality of selector switches ([0044], fig. 7) configured to selectively switch the first and second resistor units, and the first and second resistor units provide a plurality of internal reference potentials (fig. 7).
Regarding claim 11, Hashimoto443 teaches wherein the first and second resistor units form a pair, and the voltage dividing circuit includes more than two pairs (fig. 7).
Regarding claim 12, Hashimoto443 teaches further comprising an internal voltage generating circuit, wherein the internal voltage generating circuit including the voltage dividing circuit (fig. 1-2).
Regarding claim 13, Hashimoto443 teaches wherein the apparatus includes a memory device, and the voltage dividing circuit provides a plurality of internal reference potentials for a plurality of circuit elements of the memory device (fig. 1-2).
Regarding claim 14, Hashimoto443 teaches an apparatus (fig. 1-5 & fig. 7 and related text), comprising, a voltage dividing circuit including: a first resistor unit (top half of fig. 5) and a second resistor unit (bottom half of fig. 5), each including a resistor layer (31_1/31_2, [0032], fig. 3-5) and a wiring layer (33_1/33_2, [0032], fig. 3-5) on a semiconductor substrate (fig. 3-5), the second resistor unit parallel to the first resistor unit in a first direction (X or Y direction) in a plan view; and a bridge (32_2, [0032]) configured to link the first resistor unit to the second resistor unit (fig. 3-5), wherein the wiring layer of each of the first and second resistor units includes a middle portion (42, [0039]) at a predetermined distance from end portions of the wiring layer in a second direction (Y or X direction) perpendicular to the first direction, and the bridge links the middle portions of the wiring layers of the first and second resistor units (fig. 3-5).
Regarding claim 15, Hashimoto443 teaches wherein the middle portion of each of the first and the second resistor units is at or around a lengthwise center of each of the wiring layer in the second direction (fig. 5).
Regarding claim 16, Hashimoto443 teaches wherein each of the first and second resistor units further includes a plurality of contacts (45, [0039]) between the resistor layer and the wiring layer, the plurality of contacts include a middle contact at the middle portion of the wiring layer, and the bridge links the middle contacts of the first and second resistor units with each other (fig. 5).
Regarding claim 17, Hashimoto443 teaches wherein the voltage dividing circuit further includes a plurality of selector switches ([0044], fig. 7), and the wiring layers of the first and second resistor units are electrically coupled to the selector switches (fig. 7).
Regarding claim 18, Hashimoto443 teaches further comprising an internal voltage generating circuit, wherein the internal voltage generating circuit including the voltage dividing circuit (fig. 1-2).
Regarding claim 19, Hashimoto443 teaches an internal voltage generating circuit of a semiconductor device (fig. 1-5 & fig. 7 and related text), comprising a voltage dividing circuit, the voltage dividing circuit including: a plurality of selector switches ([0044], fig. 7); and a plurality of resistor units paired with the plurality of selector switches (fig. 7), the plurality of resistor units including a first resistor unit (top half of fig. 5) and a second resistor unit (bottom half of fig. 5), the second resistor unit parallel to the first resistor unit in a first direction (X or Y direction) in a plan view; and a bridge (32_2, [0032]) configured to link the first resistor unit to the second resistor unit (fig. 3-5), wherein each of the first and second resistor units include a resistor layer (31_1/31_2, [0032], fig. 3-5) and a wiring layer (33_1/33_2, [0032], fig. 3-5) on a semiconductor substrate (fig. 3-5), the wiring layer of each of the first and second resistor units includes a middle portion (42, [0039]) at a predetermined distance from end portions of the wiring layer in a second direction (Y or X direction) perpendicular to the first direction, and the bridge links the middle portions of the wiring layers of the first and second resistor units (fig. 3-5).
Regarding claim 20, Hashimoto443 teaches wherein the semiconductor device is a memory device (fig. 1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897
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