Office Action Predictor
Last updated: April 15, 2026
Application No. 18/521,570

METHOD AND APPARATUS FOR REDUCING STORAGE FOR PROPORTIONAL DATA

Non-Final OA §101§103
Filed
Nov 28, 2023
Examiner
SIDDIQUEE, ISMAAEEL ABDULLAH
Art Unit
3648
Tech Center
3600 — Transportation & Electronic Commerce
Assignee
Stmicroelectronics International N.V.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
3y 1m
To Grant
88%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allow Rate
102 granted / 131 resolved
+25.9% vs TC avg
Moderate +10% lift
Without
With
+10.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
48 currently pending
Career history
179
Total Applications
across all art units

Statute-Specific Performance

§101
3.1%
-36.9% vs TC avg
§103
74.9%
+34.9% vs TC avg
§102
3.7%
-36.3% vs TC avg
§112
15.6%
-24.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 131 resolved cases

Office Action

§101 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Examiner’s Note To help the reader, examiner notes in this detailed action claim language is in bold, strikethrough limitations are not explicitly taught and language added to explain a reference mapping are isolated from quotations via square brackets. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to judicial exception (i.e. a law of nature, a natural phenomenon, or abstract idea) without significantly more (see MPEP 2106). Applying Step 1 of the MPEP § 2106, the instant application includes the following independent claims: Claim 1 is directed towards “An apparatus comprising: a controller configured to generate a linear rate of change" Claim 8 is directed towards “A method, comprising: for each input value in a plurality of input values comprising at least a first input value and a second input value” Claim 15 is directed towards “A radar system comprising: a phase-locked loop comprising: a first circuit configured to receive an input value and generate an output value proportional to the input value” As such, claims 1, 8, 15 are directed to one of the four categories of patent eligible subject matter. Claims 8 and 15 are evaluated under the same basis and claim 1 because claims 8 and 15 have the same defects as those noted in claim 1 below: Regarding Step 2A, prong 1 of the MPEP § 2106: claim 1 presents the following steps which under a broadest reasonable interpretation of the claimed invention, constitute an abstract idea and recite a mathematical process: An apparatus comprising: a controller configured to generate a linear rate of change and a linear estimate based on a plurality of input values provided to a first circuit and a plurality of output values proportional to the plurality of input values received from the first circuit, wherein the plurality of input values comprise at least a first input value proportional to a first output value and a second input value proportional to a second output value, wherein the linear rate of change is determined based at least in part on the change from the first input value to the second input value and on the change from the first output value to the second output value, and wherein the linear estimate of the plurality of output values is determined based at least in part on the first output value and the linear rate of change; and a memory, configured to store a storage value that represents an offset of an output value of the plurality of output values from the linear estimate. Each of these steps can reasonably be performed by a general-purpose computer as indicated in Applicant’s specification (see para. 0044) and thus are reasonably mathematical concepts. Regarding Step 2A, prong 2 of the MPEP § 2106: Claims 1, 8, 15 do not integrate the claimed abstract idea into a practical application. Claims 1, 8, 15 similarly recite “store a storage value that represents an offset of an output value of the plurality of output values from the linear estimate” These limitations add insignificant extra-solution activity to the judicial exception – see MPEP 2106.05(g). Regarding Step 2B of the MPEP § 2106: Claims 1, 8, 15 do not recite additional elements, taken individually and in combination, that result in the claim as a whole, amounting to an inventive concept. The claim consists entirely of computing and outputting data in the form of an aggregating solution; thus, the claim generally links the use of the judicial exception to a particular mathematical calculation; and thus, fails to impose a meaningful limit on the judicial exception other than steps that would be considered well understood, routine and conventional. Claims 1, 8, 15 as a whole, looking at the additional elements individually and in combination, merely requires an expression of a mathematical concept and performing mathematical calculations (see MPEP 2106.04(a)(2)). As such claims 1, 8, 15 do not integrate the abstract idea into an inventive concept. Claims 2-7, 9-14, 16-20, when taken both individually and in combination, are directed to the judicial exception (i.e. a law of nature, a natural phenomenon, or abstract idea) without significantly more. Each of the additional cited claims add limitations can be performed by a general-purpose computer using math. As such, claims 2-7, 9-14, 16-20 as a whole, looking at the additional elements individually and in combination, merely requires an expression of a mathematical concept and performing mathematical calculations, with or without a simple calculator (see MPEP 2106.04(a)(2)). Finally, claims 2-7, 9-14, 16-20 do not integrate the abstract idea into a practical application. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 5-8, 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nassar et al. (US PAT 9791834 hereinafter Nassar) in view of Kuyel et al. (US 20030160713 hereinafter Kuyel). Regarding claim 1, Nassar teaches An apparatus comprising: a controller configured to generate a linear rate of change and a linear estimate based on a plurality of input values provided to a first circuit and a plurality of output values proportional to the plurality of input values received from the first circuit (2:37-42 “the set of measured phase outputs may be used to generate a piece-wise linear function that estimates the phase output for DTC inputs that were not in the measured set. In some exemplary implementations, functions other than a piece-wise linear function may be generated to determine DTC inputs corresponding to each phase output.”; 7:60-65 “The DTC calibration system 300 may be operatively coupled to a DTC 310. For example, the DTC calibration system 300 may provide DTC inputs to the DTC and receive an output to the DTC.”), wherein the plurality of input values comprise at least a first input value proportional to a first output value and a second input value proportional to a second output value (2:29-32 “To calibrate a DTC using a TDC that has a lower resolution than the DTC, the TDC may determine a DTC input corresponding to particular phase output at a number of phase outputs of the TDC.”), wherein the linear rate of change is determined based at least in part on the change from the first input value to the second input value and on the change from the first output value to the second output value (7:16-24 “to calibrate a DTC may be determine by the difference between the measured points 230A, 230B. Thus, that portion of a piecewise linear function may be defined by a slope of (8 ps−5 ps)/(28−18)=0.3, such that a phase offset of the DTC may be determined by the equation “Offset=0.3DTC.sub.input−0.4” between DTC inputs of 18 and 28. Similar equations may be generated between each of the measured points 230A-230I.”), and wherein the linear estimate of the plurality of output values is determined based at least in part on the first output value and the linear rate of change (7:16-24 “to calibrate a DTC may be determine by the difference between the measured points 230A, 230B. Thus, that portion of a piecewise linear function may be defined by a slope of (8 ps−5 ps)/(28−18)=0.3, such that a phase offset of the DTC may be determined by the equation “Offset=0.3DTC.sub.input−0.4” between DTC inputs of 18 and 28. Similar equations may be generated between each of the measured points 230A-230I.”); and a memory (4:35-38 “The processors may be coupled with and/or may include memory/storage and may be configured to execute instructions stored in the memory/storage to enable various applications and/or operating systems to run on the system.”), Nassar does not explicitly teach the strikethrough limitations. However, in a related field of endeavor, Kuyel teaches configured to store a storage value that represents an offset of an output value of the plurality of output values from the linear estimate (claim 12 “a memory containing sets of linearly varying values between adjacent pairs of selected digital input code values, wherein said sets approximate deviations of actual analog output values from desired analog output values”) Furthermore, it would have been obvious to one of ordinary skill in the art, at the time of filing of the instant application, to include the teachings of Kuyel with the teachings of Nassar. One would have been motivated to do so in order to advantageously improve linearity for circuits (Kuyel 0002). Further still, the Supreme Court in KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007) provides that combining prior art elements according to known methods to yield predictable results may render a claimed invention obvious over such combination. Here, Kuyel merely teaches that it is well-known to incorporate the particular circuit features. Since both Nassar and Kuyel disclose similar piecewise calibration systems for circuits, one of ordinary skill in the art would recognize that the combination of elements here has previously been executed according to known methods, thereby evidencing that such combination would yield predictable results. Regarding claim 5, the cited prior art teaches The apparatus of Claim 1, wherein the plurality of output values monotonically increase as the plurality of input values increase (Nassar table 1 [The DTC output phase increases monotonically as the DCT input also increases.]). Regarding claim 6, the cited prior art teaches The apparatus of Claim 1, wherein the linear estimate comprises a line that passes through a point representing the first input value and proportional first output value and comprising a slope correlated to the linear rate of change (Nassar 7:24-28 “Thus, that portion of a piecewise linear function may be defined by a slope of (8 ps−5 ps)/(28−18)=0.3, such that a phase offset of the DTC may be determined by the equation “Offset=0.3DTC.sub.input−0.4” between DTC inputs of 18 and 28. Similar equations may be generated between each of the measured points 230A-230I.”). Regarding claim 7, the cited prior art teaches The apparatus of Claim 1, wherein a first number of bits required to store the storage value is less than a second number of bits required to store the output value (Kuyel 0054 “Thus, the calibration DAC 19 uses seven bits of reference scaling and 12 bits of segmented R-2R. That is, the calibration DAC 19 has 19 bits of resolution and eight bit equivalent full-scale error.”). Furthermore, it would have been obvious to one of ordinary skill in the art, at the time of filing of the instant application, to include the teachings of Kuyel with the teachings of Nassar. One would have been motivated to do so in order to advantageously improve linearity for circuits (Kuyel 0002). Further still, the Supreme Court in KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007) provides that combining prior art elements according to known methods to yield predictable results may render a claimed invention obvious over such combination. Here, Kuyel merely teaches that it is well-known to incorporate the particular circuit features. Since both Nassar and Kuyel disclose similar piecewise calibration systems for circuits, one of ordinary skill in the art would recognize that the combination of elements here has previously been executed according to known methods, thereby evidencing that such combination would yield predictable results. Regarding claim 8, Nassar teaches A method, comprising: for each input value in a plurality of input values comprising at least a first input value and a second input value (9:34-37 “If there are additional TDC inputs to be tested, the DTC calibration system may return to block 410 and determine another DTC input that corresponds to the next TDC threshold.”): (1) transmitting the input value to a first circuit, wherein the first circuit is configured to generate an output value based at least in part on the input value, and (2) receiving an output value proportional to the input value (2:37-42 “the set of measured phase outputs may be used to generate a piece-wise linear function that estimates the phase output for DTC inputs that were not in the measured set. In some exemplary implementations, functions other than a piece-wise linear function may be generated to determine DTC inputs corresponding to each phase output.”; 7:60-65 “The DTC calibration system 300 may be operatively coupled to a DTC 310. For example, the DTC calibration system 300 may provide DTC inputs to the DTC and receive an output to the DTC.”); determining a linear rate of change based at least in part on the change from the first input value to the second input value and on the change from a first output value proportional to the first input value to a second output value proportional to the second input value (7:16-24 “to calibrate a DTC may be determine by the difference between the measured points 230A, 230B. Thus, that portion of a piecewise linear function may be defined by a slope of (8 ps−5 ps)/(28−18)=0.3, such that a phase offset of the DTC may be determined by the equation “Offset=0.3DTC.sub.input−0.4” between DTC inputs of 18 and 28. Similar equations may be generated between each of the measured points 230A-230I.”); determining a linear estimate of a plurality of output values based at least in part on the first output value and the linear rate of change (7:16-24 “to calibrate a DTC may be determine by the difference between the measured points 230A, 230B. Thus, that portion of a piecewise linear function may be defined by a slope of (8 ps−5 ps)/(28−18)=0.3, such that a phase offset of the DTC may be determined by the equation “Offset=0.3DTC.sub.input−0.4” between DTC inputs of 18 and 28. Similar equations may be generated between each of the measured points 230A-230I.”); and for each input value in the plurality of input values: Nassar does not explicitly teach the strikethrough limitations. However, in a related field of endeavor, Kuyel teaches computing a storage value representing an offset of a proportional output value from the linear estimate for a proportional input value, and storing the storage value in a memory at a location representing the proportional input value (claim 12 “a memory containing sets of linearly varying values between adjacent pairs of selected digital input code values, wherein said sets approximate deviations of actual analog output values from desired analog output values”). Furthermore, it would have been obvious to one of ordinary skill in the art, at the time of filing of the instant application, to include the teachings of Kuyel with the teachings of Nassar. One would have been motivated to do so in order to advantageously improve linearity for circuits (Kuyel 0002). Further still, the Supreme Court in KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007) provides that combining prior art elements according to known methods to yield predictable results may render a claimed invention obvious over such combination. Here, Kuyel merely teaches that it is well-known to incorporate the particular circuit features. Since both Nassar and Kuyel disclose similar piecewise calibration systems for circuits, one of ordinary skill in the art would recognize that the combination of elements here has previously been executed according to known methods, thereby evidencing that such combination would yield predictable results. Regarding claim 12, claim 12 recites substantially the same limitations as claim 5 and is therefore rejected for substantially the same reasons as claim 5. Regarding claim 13, claim 13 recites substantially the same limitations as claim 6 and is therefore rejected for substantially the same reasons as claim 6. Regarding claim 14, claim 14 recites substantially the same limitations as claim 7 and is therefore rejected for substantially the same reasons as claim 7. Claim(s) 2, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nassar et al. (US PAT 9791834 hereinafter Nassar) in view of Kuyel et al. (US 20030160713 hereinafter Kuyel) as applied to claim 1 and further in view of Saunders (US 20090195321). Regarding claim 2, the cited prior art teaches The apparatus of Claim 1, The cited prior art does not explicitly teach the strikethrough limitations. However, in a related field of endeavor, Kuyel teaches wherein the first circuit comprises a voltage-controlled oscillator and the plurality of input values correspond to a plurality of input voltages. (claim 1 “a phase lock loop (PLL) on the RF module, wherein the PLL provides a VCO input voltage to the VCO based on a reference frequency during the frequency calibration mode”). Furthermore, it would have been obvious to one of ordinary skill in the art, at the time of filing of the instant application, to include the teachings of Saunders with the cited prior art. One would have been motivated to do so in order to advantageously improve calibration of the system (Saunders 0008). Further still, the Supreme Court in KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007) provides that combining prior art elements according to known methods to yield predictable results may render a claimed invention obvious over such combination. Here, Saunders merely teaches that it is well-known to incorporate the particular circuit features. Since both the cited prior art and Saunders disclose similar circuitry, one of ordinary skill in the art would recognize that the combination of elements here has previously been executed according to known methods, thereby evidencing that such combination would yield predictable results. Regarding claim 9, claim 9 recites substantially the same limitations as claim 2 and is therefore rejected for substantially the same reasons as claim 2. Claim(s) 3-4, 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nassar et al. (US PAT 9791834 hereinafter Nassar) in view of Kuyel et al. (US 20030160713 hereinafter Kuyel) and further in view of Saunders (US 20090195321) as applied to claim 1 and further in view of Wu et al. (US 20130088302 hereinafter Wu). Regarding claim 3, the cited prior art teaches The apparatus of Claim 2, The cited prior art does not explicitly teach the strikethrough limitations. However, in a related field of endeavor, Wu teaches wherein the voltage-controlled oscillator is further configured to generate an output signal comprising an output frequency, and wherein the plurality of output values are proportional to the output frequency of the output signal (0004 “FIG. 1 schematically illustrates a block diagram of a conventional VCO 11. In the conventional VCO 11, an input voltage vin may be directly applied to an input of the VCO 11, and an output signal with an oscillation frequency f may be output from an output of the VCO 11”). Furthermore, it would have been obvious to one of ordinary skill in the art, at the time of filing of the instant application, to include the teachings of Wu with the cited prior art. One would have been motivated to do so in order to advantageously improve calibration of the system (Wu 0008). Further still, the Supreme Court in KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007) provides that combining prior art elements according to known methods to yield predictable results may render a claimed invention obvious over such combination. Here, Wu merely teaches that it is well-known to incorporate the particular circuit features. Since both the cited prior art and Wu disclose similar circuitry, one of ordinary skill in the art would recognize that the combination of elements here has previously been executed according to known methods, thereby evidencing that such combination would yield predictable results. Regarding claim 4, the cited prior art teaches The apparatus of Claim 2, The cited prior art does not explicitly teach the strikethrough limitations. However, in a related field of endeavor, Wu teaches wherein the first input value corresponds to a lowest input value of the plurality of input values comprising a lowest input voltage, and the second input value corresponds to a highest input value of the plurality of input values comprising a highest input voltage (0010 “FIG. 2 illustrates an ideal curve showing an input voltage vs. an oscillation frequency of the conventional VCO 11 as shown in FIG. 1. The linear range of the conventional VCO 11 is -vin.sub.max.ltoreq.vin.ltoreq.+vin.sub.max, wherein k is a constant only depending on electric characteristics of the VCO 11”). Furthermore, it would have been obvious to one of ordinary skill in the art, at the time of filing of the instant application, to include the teachings of Wu with the cited prior art. One would have been motivated to do so in order to advantageously improve calibration of the system (Wu 0008). Further still, the Supreme Court in KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007) provides that combining prior art elements according to known methods to yield predictable results may render a claimed invention obvious over such combination. Here, Wu merely teaches that it is well-known to incorporate the particular circuit features. Since both the cited prior art and Wu disclose similar circuitry, one of ordinary skill in the art would recognize that the combination of elements here has previously been executed according to known methods, thereby evidencing that such combination would yield predictable results. Regarding claim 10, claim 10 recites substantially the same limitations as claim 3 and is therefore rejected for substantially the same reasons as claim 3. Regarding claim 11, claim 11 recites substantially the same limitations as claim 4 and is therefore rejected for substantially the same reasons as claim 4. Claim(s) 15-16, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nassar et al. (US PAT 9791834 hereinafter Nassar) in view of Kuyel et al. (US 20030160713 hereinafter Kuyel) and further in view of Subburaj et al. (US 20170023663 hereinafter Subburaj). Regarding claim 15, claim 15 recites substantially the same limitations as claim 1 and is therefore rejected for substantially the same reasons as claim 1. Nassar in view of Kuyel does not explicitly teach a radar system comprising a phased locked loop. However, in a related field of endeavor, Subburaj teaches radar system comprising a phased locked loop (0090 “radar apparatus 100”; 0089 “The operation of the local oscillator 600 illustrated in FIG. 6 is explained now. The local oscillator 600 in one example is a closed loop PLL (phase locked loop)”). Furthermore, it would have been obvious to one of ordinary skill in the art, at the time of filing of the instant application, to include the teachings of Subburaj with the cited prior art. One would have been motivated to do so in order to advantageously reduce the power loss within the circuitry (Subburaj 0030). Further still, the Supreme Court in KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007) provides that combining prior art elements according to known methods to yield predictable results may render a claimed invention obvious over such combination. Here, Subburaj merely teaches that it is well-known to incorporate the particular circuit features. Since both the cited prior art and Subburaj disclose similar circuitry, one of ordinary skill in the art would recognize that the combination of elements here has previously been executed according to known methods, thereby evidencing that such combination would yield predictable results. Regarding claim 16, the cited prior art teaches The radar system of Claim 15, further comprising: a local oscillator electrically connected to the phase-locked loop (Subburaj 0089 “The local oscillator 600 in one example is a closed loop PLL (phase locked loop)”), wherein the phase-locked loop generates an output signal based at least in part on a reference signal generated by the local oscillator (Subburaj 0089 “The local oscillator 600 in another example is an open loop VCO (voltage controlled oscillator) or an open loop DCO (digital controlled oscillator). The oscillator 608 generates the transmit signal 610 which is provided as feedback to the controller 602.”); a transmit amplifier electrically connected to the phase-locked loop, wherein the transmit amplifier generates an amplified output signal based at least in part on the output signal (Subburaj 0085 “A power amplifier 506 is coupled to the conditioner 504. In an embodiment, the transmit unit 500 does not include the conditioner 504 and the power amplifier 506 receives the transmit signal 502.”); a transmit antenna electrically connected to the transmit amplifier (Subburaj fig 5), wherein the transmit antenna transmits a transmitted signal based at least in part on the amplified output signal (Subburaj 0085 “A power amplifier 506 is coupled to the conditioner 504. In an embodiment, the transmit unit 500 does not include the conditioner 504 and the power amplifier 506 receives the transmit signal 502.”); a receive antenna configured to receive a reflected signal resulting from one or more objects encountered by the transmitted signal (Subburaj fig 4); a receive amplifier electrically connected to the receive antenna, wherein the receive amplifier is configured to generate an amplified receive signal based at least in part on the reflected signal (Subburaj 0078 “he receive unit 400 includes a receive antenna unit 402. A low-noise amplifier (LNA) 404 is coupled to the receive antenna unit 402. A mixer 406 is coupled to the LNA 404 and also receive a transmit signal 408.”); a mixer electrically connected to the phase-locked loop and the receive amplifier, wherein the mixer is configured to produce a mixed signal based at least in part on the output signal and the amplified receive signal (Subburaj 0078 “A mixer 406 is coupled to the LNA 404 and also receive a transmit signal 408.”); a receive filter electrically connected to the mixer, wherein the receive filter is configured to generate a filtered signal based at least in part on the mixed signal (Subburaj 0036 “The conditioner 208 amplifies and filters an output of the mixer 202 to generate a filtered signal. The filtered signal is provided to an ADC (analog to digital converter) 210 for sampling.”); and a processor electrically connected to the receive filter, wherein the processor determines one or more characteristics of the one or more objects based at least in part on the filtered signal (Subburaj 0036 “The filtered signal is provided to an ADC (analog to digital converter) 210 for sampling. The filtered signal is converted to a digital signal by the ADC 210. The delay detect circuit 200 provides the digital signal from the ADC 210 to a digital signal processor (DSP) 212.”). Furthermore, it would have been obvious to one of ordinary skill in the art, at the time of filing of the instant application, to include the teachings of Subburaj with the cited prior art. One would have been motivated to do so in order to advantageously reduce the power loss within the circuitry (Subburaj 0030). Further still, the Supreme Court in KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007) provides that combining prior art elements according to known methods to yield predictable results may render a claimed invention obvious over such combination. Here, Subburaj merely teaches that it is well-known to incorporate the particular circuit features. Since both the cited prior art and Subburaj disclose similar circuitry, one of ordinary skill in the art would recognize that the combination of elements here has previously been executed according to known methods, thereby evidencing that such combination would yield predictable results. Regarding claim 20, the cited prior art teaches The radar system of Claim 15, wherein the linear estimate comprises a line that passes through a point representing the first input value and proportional first output value and comprising a slope correlated to the linear rate of change (Nassar 7:24-28 “Thus, that portion of a piecewise linear function may be defined by a slope of (8 ps−5 ps)/(28−18)=0.3, such that a phase offset of the DTC may be determined by the equation “Offset=0.3DTC.sub.input−0.4” between DTC inputs of 18 and 28. Similar equations may be generated between each of the measured points 230A-230I.”). Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nassar et al. (US PAT 9791834 hereinafter Nassar) in view of Kuyel et al. (US 20030160713 hereinafter Kuyel) and further in view of Subburaj et al. (US 20170023663 hereinafter Subburaj) as applied to claim 15 and further in view of Saunders (US 20090195321). Regarding claim 17, the cited prior art teaches The radar system of Claim 15, The cited prior art does not explicitly teach the strikethrough limitations. However, in a related field of endeavor, Kuyel teaches wherein the first circuit comprises a voltage-controlled oscillator and the plurality of input values correspond to a plurality of input voltages. (claim 1 “a phase lock loop (PLL) on the RF module, wherein the PLL provides a VCO input voltage to the VCO based on a reference frequency during the frequency calibration mode”). Furthermore, it would have been obvious to one of ordinary skill in the art, at the time of filing of the instant application, to include the teachings of Saunders with the cited prior art. One would have been motivated to do so in order to advantageously improve calibration of the system (Saunders 0008). Further still, the Supreme Court in KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007) provides that combining prior art elements according to known methods to yield predictable results may render a claimed invention obvious over such combination. Here, Saunders merely teaches that it is well-known to incorporate the particular circuit features. Since both the cited prior art and Saunders disclose similar circuitry, one of ordinary skill in the art would recognize that the combination of elements here has previously been executed according to known methods, thereby evidencing that such combination would yield predictable results. Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nassar et al. (US PAT 9791834 hereinafter Nassar) in view of Kuyel et al. (US 20030160713 hereinafter Kuyel), Subburaj et al. (US 20170023663 hereinafter Subburaj), and further in view of Saunders (US 20090195321) as applied to claim 17 and further in view of Wu et al. (US 20130088302 hereinafter Wu). Regarding claim 18, the cited prior art teaches The radar system of Claim 17, The cited prior art does not explicitly teach the strikethrough limitations. However, in a related field of endeavor, Wu teaches wherein the voltage-controlled oscillator is further configured to generate an output signal comprising an output frequency, and wherein the plurality of output values are proportional to the output frequency of the output signal (0004 “FIG. 1 schematically illustrates a block diagram of a conventional VCO 11. In the conventional VCO 11, an input voltage vin may be directly applied to an input of the VCO 11, and an output signal with an oscillation frequency f may be output from an output of the VCO 11”). Furthermore, it would have been obvious to one of ordinary skill in the art, at the time of filing of the instant application, to include the teachings of Wu with the cited prior art. One would have been motivated to do so in order to advantageously improve calibration of the system (Wu 0008). Further still, the Supreme Court in KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007) provides that combining prior art elements according to known methods to yield predictable results may render a claimed invention obvious over such combination. Here, Wu merely teaches that it is well-known to incorporate the particular circuit features. Since both the cited prior art and Wu disclose similar circuitry, one of ordinary skill in the art would recognize that the combination of elements here has previously been executed according to known methods, thereby evidencing that such combination would yield predictable results. Regarding claim 19, the cited prior art teaches The radar system of Claim 17 The cited prior art does not explicitly teach the strikethrough limitations. However, in a related field of endeavor, Wu teaches wherein the first input value corresponds to a lowest input value of the plurality of input values comprising a lowest input voltage, and the second input value corresponds to a highest input value of the plurality of input values comprising a highest input voltage (0010 “FIG. 2 illustrates an ideal curve showing an input voltage vs. an oscillation frequency of the conventional VCO 11 as shown in FIG. 1. The linear range of the conventional VCO 11 is -vin.sub.max.ltoreq.vin.ltoreq.+vin.sub.max, wherein k is a constant only depending on electric characteristics of the VCO 11”). Furthermore, it would have been obvious to one of ordinary skill in the art, at the time of filing of the instant application, to include the teachings of Wu with the cited prior art. One would have been motivated to do so in order to advantageously improve calibration of the system (Wu 0008). Further still, the Supreme Court in KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007) provides that combining prior art elements according to known methods to yield predictable results may render a claimed invention obvious over such combination. Here, Wu merely teaches that it is well-known to incorporate the particular circuit features. Since both the cited prior art and Wu disclose similar circuitry, one of ordinary skill in the art would recognize that the combination of elements here has previously been executed according to known methods, thereby evidencing that such combination would yield predictable results. Conclusion The prior art made of record and not relied upon is considered pertinent to application’s disclosure: Yamamoto et al. (US PAT 6424184) discloses “A frequency-voltage conversion circuit 21 receives a clock CLK as an input and provides a voltage IV.sub.dd in accordance with the frequency of the clock as an output. The input and output characteristic of the frequency-voltage conversion circuit 21 is adjusted to substantially match a given input and output characteristic (See abstract)” Any inquiry concerning this communication or earlier communications from the examiner should be directed to ISMAAEEL A. SIDDIQUEE whose telephone number is (571) 272-3896. The examiner can normally be reached on Monday-Friday 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kelleher can be reached on (571) 272-7753. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ISMAAEEL A. SIDDIQUEE/ Examiner, Art Unit 3648
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Prosecution Timeline

Nov 28, 2023
Application Filed
Dec 15, 2025
Non-Final Rejection — §101, §103
Mar 10, 2026
Applicant Interview (Telephonic)
Mar 12, 2026
Examiner Interview Summary
Apr 02, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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1-2
Expected OA Rounds
78%
Grant Probability
88%
With Interview (+10.4%)
3y 1m
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