DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/28/2023, 05/30/2024, 07/23/2024 and 07/10/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, 10, 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Oshima (U.S. Publication 20220188617) in view of Komeno (U.S. Publication 20190120158).
Regarding claim 1, Oshima teaches an anomaly detection device (an information processing device including a reservoir computer having a reservoir unit and an output layer (Fig. 4, reservoir unit 401 and output layer 402; [0005, 0060-0061])) comprising:
an input device configured to acquire a time-series input signal detected by observing an observation target device, and output a plurality of intermediate signals corresponding to the input signal (a plurality of analog input signals from outside are supplied to the reservoir unit, and each neuron circuit receives analog input signals from outside, analog output signals from another neuron circuit, or its own analog output signal; [0036, 0060]);
a reservoir device configured to acquire the plurality of intermediate signals, and output a plurality of output signals each having a waveform that has reproducibility for a waveform of the input signal (the reservoir unit includes a plurality of neuron circuits connected to each other, each neuron circuit updating its output based on received signals and providing outputs to other neuron circuits and the output layer, thereby retaining temporal characteristics associated with the input signal; [0033, 0060-0061]);
an output device configured to acquire the plurality of output signals, generate a plurality of multiplication signals by respectively multiplying the plurality of output signals by output weights set in advance,
wherein the output weights by which the plurality of output signals are respectively multiplied, each represent a positive predetermined value or a negative predetermined value, and are respectively set for the plurality of output signals (the weight coefficients assigned to the neuron outputs are predetermined and set in advance as part of the reservoir computer design; [0044-0046]).
Oshima does not explicitly teach an output unit configured to generate an integral signal obtained by time integration through adding up the plurality of multiplication signals, nor a determination unit configured to determine whether the observation target device is normal or abnormal based on a result of comparison between the integral signal and a threshold set in advance, and output a determination signal representing a determination result.
However, Komeno in a relevant art teaches an abnormality detection apparatus including an integration unit configured to calculate an integrated value by integrating a plurality of differences between measured values and target values over a period of time ([006, 0040-0044]). Komeno further teaches a determination unit configured to compare the integrated value with a threshold value and determine whether an abnormal condition exists based on the comparison, and an abnormality notification unit configured to output an abnormality determination result ([0045, 0059-0061]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reservoir computer of Oshima to generate an integrated value from the weighted output signals and determine whether an abnormal condition exists by comparing the integrated value with a threshold as taught by Komeno. Komeno teaches that abnormality determinations based on individual measurements may be susceptible to variations caused by operating conditions and environmental influences, and that integrating values over time and comparing the resulting integrated value with a threshold improves abnormality detection precision. Applying Komeno's known integration and threshold technique to the reservoir computing outputs of Oshima would have predictably improved the reliability of anomaly detection while utilizing the output information already generated by Oshima. Such modification merely involves applying a known signal evaluation technique to the known reservoir computing architecture of Oshima to obtain the predictable result of improved abnormality determination accuracy.
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Regarding claim 2, Oshima further teaches wherein the input signal is a signal such that a value determined in advance is obtained by averaging the input signal in a time direction (processing time-series sensing signals using a reservoir computer including a plurality of recurrently connected neuron circuits that receive analog input signals from outside and generate outputs based on present and past signal values. The reservoir unit retains temporal characteristics of the input signal through the interactions among the neuron circuits and the feedback of output signals, thereby generating signal values that reflect temporal aggregation of the input signal over time ([0033], [0036], [0060-0061])
Therefore, Oshima teaches or at least suggests wherein the input signal is a signal such that a value determined in advance is obtained by averaging the input signal in a time direction, because the reservoir computer processes time-series input signals and generates values representative of the temporal behavior of the input signal through accumulation and aggregation of information over time).
Regarding claim 3, Oshima does not explicitly teach wherein the determination device is configured to determine that the observation target device is abnormal in a case in which an absolute value of the integral signal is larger than the threshold.
However, Komeno in a relevant art teaches determining whether an abnormal condition exists by comparing an integrated value with a threshold value, wherein abnormality is determined when the integrated value exceeds the threshold value ([0045, 0059-0061]). The integrated value is generated based on a plurality of values accumulated over time and is used as the basis for the abnormality determination. Therefore, Komeno teaches or at least suggests determining that the observation target device is abnormal in a case in which the absolute value of the integral signal is larger than the threshold, because Komeno's abnormality determination is based on the magnitude of the integrated value relative to a predetermined threshold.
A person of ordinary skill in the art would have recognized that whether the integrated value exceeds the threshold in a positive or negative direction, the relevant consideration is that the magnitude of the integrated value indicates deviation from a normal condition.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reservoir computer of Oshima by Komeno to determine abnormality when the absolute value of the integral signal exceeds the threshold in order to detect abnormal conditions associated with deviations of either polarity while utilizing the same threshold based abnormality determination technique taught by Komeno.
Regarding claim 5, Oshima further teaches wherein the output device comprises: a plurality of multiplication circuits each configured to acquire any one of the plurality of output signals, and multiply the acquired output signal by a corresponding output weight to generate any one of the plurality of multiplication signals (the output layer receives outputs from the plurality of neuron circuits and performs a product sum calculation using weight coefficients assigned to the respective neuron outputs, wherein the weight coefficients are implemented by capacitance values and correspond to individual output signals [0044-0046]);
and an integrating circuit configured to generate the integral signal obtained by time integration through adding up the plurality of multiplication signals (the output layer performs a sum operation on the weighted neuron outputs as part of the product-sum calculation, and the reservoir computer utilizes analog signal processing circuitry including capacitive elements that accumulate signal contributions from the plurality of weighted outputs [0044-0046]). Therefore, Oshima teaches or at least suggests an output device including a plurality of multiplication circuits that respectively multiply output signals by corresponding output weights and an integrating circuit that generates an integrated signal by adding the weighted signal contributions.
Regarding claim 6, Oshima as modified further teaches wherein each of the multiplication circuits is configured to acquire a corresponding output signal of the plurality of output signals, and includes a polarity inversion circuit for which the output weight is set in advance, and the polarity inversion circuit is configured to: output a multiplication signal obtained by multiplying the output signal by a predetermined value without inverting a polarity of the output signal in a case in which the set output weight is the positive predetermined value; and output a multiplication signal obtained by multiplying the output signal by a predetermined value while inverting the polarity of the output signal in a case in which the set output weight is the negative predetermined value (wherein each of the multiplication circuits is configured to acquire a corresponding output signal of the plurality of output signals and includes circuitry corresponding to a weight coefficient assigned to the output signal, the weight coefficient being set in advance and used in the product-sum calculation performed by the output layer ([0044-0046]) further teaches that positive and negative weight coefficients are assigned to respective neuron outputs and are implemented in the analog output layer circuitry to control the contribution of each neuron output to the product-sum calculation ([0044-0046])). As implementation of positive and negative weight coefficients in an analog weighted summation circuit necessarily requires preserving the polarity of signals associated with positive weights and inverting the polarity of signals associated with negative weights prior to accumulation in the product-sum calculation It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the signed weight coefficients taught by Oshima using polarity preserving and polarity inverting signal paths because such circuitry represents a conventional and predictable manner of realizing positive and negative weights in analog neural-network and signal processing systems. Such implementation would have predictably enabled positive weight and negative weight contributions to be combined in the weighted summation performed by the output layer.
Regarding claim 7, Oshima further teaches wherein each of the plurality of multiplication signals is a voltage signal (the reservoir computer and output layer are implemented using analog signal processing circuitry, and the outputs of the neuron circuits are analog voltage signals that are subjected to weighted product-sum calculations [0036, 0044-0046]), and the integrating circuit comprises: an adding circuit configured to generate an addition signal obtained by voltage adding the plurality of multiplication signals (the output layer receives the plurality of weighted neuron outputs and performs a product sum calculation in which the weighted signal contributions are summed together [0044-0046]); and an accumulating circuit configured to accumulate an electric charge corresponding to a voltage of the addition signal (the weight coefficients and output layer computations are implemented using capacitance elements, which accumulate electric charge corresponding to the applied voltage signals as part of the analog computation process [0044-0046]). Therefore, Oshima teaches or at least suggests an integrating circuit including an adding circuit that generates an addition signal by voltage adding a plurality of multiplication signals and an accumulating circuit that accumulates electric charge corresponding to the voltage of the addition signal, because capacitive analog computing circuits inherently perform signal accumulation through storage of charge corresponding to applied voltages. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the summation and integration functions of Oshima using voltage summing circuitry and charge accumulating capacitive circuitry because such structures represent conventional and predictable implementations of analog product sum and integration operations. Such implementation would have predictably enabled weighted voltage signals to be summed and integrated through charge accumulation to produce the desired output signal.
Regarding claim 10, Oshima further teaches (“implementing the switches 219 and 220 using MOS transistors having a higher threshold voltage than the other switches” [0052]) but does not explicitly teach a setting device configured to set the threshold in accordance with information received from an external device.
However, Komeno teaches an abnormality detection apparatus that utilizes a threshold value for abnormality determination and teaches that the threshold value may be established and adjusted based on information associated with operation of the monitored system and information stored in the control apparatus ([0045, 0059-0061]). Komeno teaches an abnormality detection apparatus that utilizes a threshold value for abnormality determination and teaches that the threshold value may be established and adjusted based on information associated with operation of the monitored system and information stored in the control apparatus ([0045, 0059-0061]).
Regarding claim 14, the method recited is intrinsic to the apparatus recited in claim 1, as disclosed by Oshima (U.S. Publication 20220188617) in view of Komeno (U.S. Publication 20190120158) as the recited method steps will be performed during the normal operation of the apparatus, as discussed above with regard to claim 1.
Regarding claim 15, the structure recited is intrinsic to the apparatus recited in claim 1, as disclosed by Oshima (U.S. Publication 20220188617) in view of Komeno (U.S. Publication 20190120158) as the recited structure will be used during the normal operation, as discussed above with regard to claim 1. Oshima as modified further teaches a computer program product comprising a computer-readable medium including programmed instructions, the instructions causing an information processing device to function (“the storage unit 13 is a storage medium including ROM, RAM, a hard disk, and the like. The storage unit 13 stores programs executed by the control unit 14” [0036]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Oshima (U.S. Publication 20220188617), Komeno (U.S. Publication 20190120158) as applied to the rejection of claim 1 above and further in view of Cantrell (U.S. Patent 5502448).
Regarding claim 4, Oshima as modified does not explicitly teach wherein the determination device comprises: an absolute value circuit configured to generate an absolute value signal representing the absolute value of the integral signal; and a comparator circuit configured to compare the absolute value signal with the threshold, to output the determination signal.
However, Cantrell in a relevant art teaches an identification signal circuit comprising a circuit for providing the absolute value of a signal generated by a subtracter circuit (Fig. 4, absolute value circuit 88), wherein the absolute value circuit generates an absolute value signal representing the magnitude of the input signal. further teaches a comparator circuit configured to receive the absolute value signal and a threshold signal, compare the strength of the absolute value signal with the threshold signal, and provide an output signal when the absolute value signal exceeds the threshold value (Fig. 4, comparator 90 and threshold circuit 92; col. 3, line 35 - col. 4, line 5; claim 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the threshold based abnormality determination of Oshima as modified by Komeno using the absolute value circuit and comparator circuit taught by Cantrell because generating an absolute value signal and comparing that signal with a threshold is a known signal processing technique for determining whether a signal magnitude exceeds a threshold regardless of signal polarity. Applying the known circuit arrangement of Cantrell to the abnormality determination system of Oshima and Komeno would have predictably enabled determination of abnormality based on the absolute value of the integral signal and generation of a corresponding determination signal when the signal magnitude exceeds the threshold.
Claims 8-9, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Oshima (U.S. Publication 20220188617), Komeno (U.S. Publication 20190120158) as applied to the rejection of claim 1 above and further in view of Nishitani (U.S. Publication 20150178619).
Regarding claim 8, Oshima as modified by Komeno does not explicitly teach wherein each of the plurality of multiplication signals is a voltage signal, the integrating circuit comprises: an operational amplifier circuit; a capacitor connected between an output terminal and an inverting input terminal of the operational amplifier circuit; and a plurality of input resistors corresponding to the plurality of multiplication signals on a one-to-one basis, and each having one terminal connected to the inverting input terminal, and another terminal to which a corresponding multiplication signal is applied, and the output terminal of the operational amplifier circuit is configured to output the integral signal.
However, Nishitani in a relevant art teaches a neuron circuit including an analog integrating circuit 31 configured to compute a sum of currents flowing from a plurality of synapse circuits connected to the neuron circuit ([0093-0094]; Fig. 1), further teaches that the analog integrating circuit 31 includes an operational amplifier 35, a capacitor 36, and a resistive element 37, wherein the capacitor 36 and the resistive element 37 are connected in parallel between the negative input terminal of the operational amplifier 35 and the output terminal of the operational amplifier 35 ([0094]; Fig. 3), further teaches that the analog integrating circuit charges the capacitor 36 with current input from the synapse circuits and outputs an integrated voltage representing a result of temporal integration of the input currents ([0095]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the integrating function of Oshima as modified using the operational amplifier based integrating circuit taught by Nishitani because Nishitani teaches a conventional analog integrator that sums a plurality of input signals and performs temporal integration using an operational amplifier and a feedback capacitor. It would have been further obvious to provide a plurality of input resistors corresponding to the plurality of multiplication signals because separate input resistors connected to the summing node of an operational amplifier integrator represent a well known and predictable implementation for summing multiple input signals prior to integration. Such modification would have predictably enabled weighted output signals of Oshima as modified to be summed and integrated using a conventional analog summing integrator while producing the integral signal at the output terminal of the operational amplifier.
Regarding claim 9, Oshima as modified by Komeno does not explicitly teach wherein each of the plurality of multiplication signals is a voltage signal, the integrating circuit comprises: an operational amplifier circuit; a delay circuit connected between an output terminal and an inverting input terminal of the operational amplifier circuit; and a plurality of input resistors corresponding to the plurality of multiplication signals on a one-to-one basis, and each having one terminal connected to the inverting input terminal, and another terminal to which a corresponding multiplication signal is applied, and the output terminal of the operational amplifier circuit is configured to output the integral signal.
However, Nishitani in a relevant art teaches a neuron circuit including an analog integrating circuit 31 configured to compute a sum of currents flowing from a plurality of synapse circuits connected to the neuron circuit ([0093-0094]; Figs. 1-3). Nishitani further teaches that the analog integrating circuit 31 includes an operational amplifier 35 and a feedback path extending between the output terminal of the operational amplifier 35 and the negative input terminal of the operational amplifier 35 through resistive element 37 and capacitor 36 ([0094]; Fig. 3). Nishitani further teaches that the feedback arrangement causes temporal integration of the input signals and outputs an integrated voltage representing accumulated signal information over time ([0095]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement the integrating function of Oshima as modified using the operational amplifier based feedback circuit taught by Nishitani because Nishitani teaches a feedback structure that stores and feeds back prior signal information to realize temporal integration. It would have been further obvious to implement the feedback function using a delay circuit connected between the output terminal and the inverting input terminal of the operational amplifier, as recited, because delay elements and feedback elements are known equivalent techniques for retaining and feeding back prior signal states in analog signal processing and reservoir computing systems. It would have been further obvious to provide a plurality of input resistors corresponding to the plurality of multiplication signals because separate input resistors connected to the summing node of an operational amplifier feedback circuit represent a well known and predictable implementation for summing multiple input signals prior to integration. Such modification would have predictably enabled weighted output signals of Oshima as modified to be summed and temporally integrated while producing the integral signal at the output terminal of the operational amplifier.
Regarding claim 11, Oshima as modified by Komeno does not explicitly teach a setting device configured to set the output weights by which the plurality of output signals is respectively multiplied, in accordance with a random number generated by a random number generator.
However, Nishitani in a relevant art teaches a neural network including a plurality of interconnected neural network circuit elements having weighted signal connections between circuit elements, wherein the weighting of signal paths is used to determine the influence of signals within the neural network ([0091-0094]; Figs. 1-2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to set the output weights of Oshima as modified in accordance with random numbers generated by a random number generator because random initialization of weights is a well known technique in neural networks and reservoir computing systems for generating diverse signal propagation characteristics and reducing undesirable symmetry among weighted connections. Such modification would have predictably enabled the reservoir computer of Oshima as modified to generate a richer set of dynamic responses while utilizing conventional weight initialization techniques commonly employed in neural network systems.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Oshima (U.S. Publication 20220188617), Komeno (U.S. Publication 20190120158) as applied to the rejection of claim 1 above and further in view of Keuninckx (WO2017102972A1).
Regarding claim 12, the structure recited is intrinsic to the method recited in claim 1, as disclosed by Oshima (U.S. Publication 20220188617) in view of Komeno (U.S. Publication 20190120158) as the recited structure will be used during the normal operation, as discussed above with regard to claim 1. Oshima as modified does not explicitly teach N reservoir devices, N being an integral number equal to or larger than 2; wherein a first reservoir device of the N reservoir devices is configured to acquire, as the input signal, a time-series signal detected by observing an observation target device; wherein an n-th reservoir device of the N reservoir devices is configured to acquire, as the input signal, the integral signal generated by an (n-1 )-th reservoir device of the N reservoir devices, n being an integral number that is equal to or larger than 2 and equal to or smaller than N; and wherein the determination device is configured to determine whether the observation target device is normal or abnormal based on a result of comparison between the integral signal generated by an N-th reservoir device of the N reservoir devices and a threshold set in advance.
However, Keuninckx in a relevant art teaches reservoir computing device comprising a cascade of at least two reservoir computing blocks (Abstract [0028]). Keuninckx further teaches that, in each subsequent reservoir computing block of the cascade, the block input signal includes an output signal generated by the previous reservoir computing block ([0028]). Keuninckx additionally teaches that the input of each subsequent computing block receives an output signal coming from the preceding computing block for further processing ([0030]). Thus, Keuninckx teaches a plurality of reservoir computing blocks arranged in series, wherein the output of a preceding reservoir computing block is supplied as an input to a subsequent reservoir computing block. Keuninckx further teaches that cascading two or more reservoir computers was a known solution for improving processing capability in reservoir computing systems ([0019]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reservoir computer of Oshima as modified to include a plurality of cascaded reservoir devices as taught by Keuninckx because cascading reservoir processing stages was known to provide hierarchical processing of temporal information and enhanced nonlinear feature extraction. Such modification would have predictably enabled outputs generated by a preceding reservoir stage to be supplied as inputs to a subsequent reservoir stage while preserving the anomaly detection functionality of Oshima as modified, thereby allowing the abnormality determination to be based on the output generated by the final reservoir stage of the cascade.
Regarding claim 13, the structure recited is intrinsic to the method recited in claim 1, as disclosed by Oshima (U.S. Publication 20220188617) in view of Komeno (U.S. Publication 20190120158) as the recited structure will be used during the normal operation, as discussed above with regard to claim 1. Oshima as modified does not explicitly N reservoir devices, N being an integral number equal to or larger than 2; wherein each of the N reservoir devices is configured to acquire the plurality of intermediate signals and output a plurality of output signals each having a waveform that has reproducibility for a waveform of the input signal; and wherein the output device is configured to acquire the plurality of output signals from each of the N reservoir devices, generate a plurality of multiplication signals by respectively multiplying the plurality of acquired output signals by output weights set in advance, and generate an integral signal obtained by time integration through adding up the plurality of multiplication signals.
However, Keuninckx in a relevant art teaches a reservoir computing device comprising a plurality of reservoir computing blocks, specifically a cascade of at least two reservoir computing blocks (Abstract [0028]). Keuninckx further teaches that multiple reservoir computing blocks may be employed within a single reservoir-computing architecture to improve processing capability for temporal signals and system-identification tasks ([0019], [0028]-[0030]). Thus, Keuninckx teaches the use of a plurality of reservoir computing blocks for processing a common time varying input signal.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the reservoir computer of Oshima as modified to employ a plurality of reservoir devices as taught by Keuninckx because the use of multiple reservoir processing blocks was known to increase the dimensionality of reservoir states and improve extraction of temporal features from time-series signals. It would have been further obvious to provide the output layer of Oshima as modified with outputs from the plurality of reservoir devices because Oshima as modified already teaches an output layer that receives reservoir outputs and performs weighted product sum calculations on those outputs ([0044-0046]). Supplying outputs from multiple reservoir devices to the known output layer of Oshima as modified would merely involve applying the known weighted summation operation to additional reservoir outputs to obtain a combined integrated signal, yielding the predictable result of enhanced processing of the input signal while utilizing known reservoir-computing techniques.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nakano (U.S. Publication 20180285728) discloses RESERVOIR COMPUTING SYSTEM.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAQI R NASIR whose telephone number is (571)270-1425. The examiner can normally be reached 9AM-5PM EST M-F.
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/TAQI R NASIR/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
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