DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This communication is in response to the Applicant’s submission filed 28 November 2023, where:
Claims 1-16 are pending.
Claims 1-16 are rejected.
Foreign priority is claimed to JP2023-031023, filed 01 March 2023. A certified copy of this paper has been filed 26 December 2023. Accordingly, receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
3. Information disclosure statements were submitted on 29 November 2023 and 14 August 2025. The submissions comply with the provisions of 37 CFR 1.97. Accordingly, the Examiner considered the information disclosure statements.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. § 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
5. Claim 16 is rejected under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 16 recites both an apparatus and a process of using the apparatus. Claim 16 recites, inter alia,
A synaptic weight update method implemented by a computer as a neural network device, the neural network device including:
* * *
(claim 16, lines 1-2 (emphasis added by Examiner)).
When both an apparatus and a method are claimed in the same claim it is unclear whether direct infringement arises when the method is performed or when the apparatus is used. Therefore the claim has an indefinite scope.
Claim Rejections – 35 U.S.C. § 103
6. The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. § 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the Examiner to consider the applicability of 35 U.S.C. § 102(b)(2)(C) for any potential 35 U.S.C. § 102(a)(2) prior art against the later invention.
9. Claims 1-6 and 8-16 are rejected under 35 U.S.C. § 103 as being unpatentable over US Published Application 20120259804 to Brezzo et al. [hereinafter Brezzo] in view of US Published Application 20200302274 to Marukame et al. [hereinafter Marukame].
Regarding claim 1, Brezzo teaches [a] neural network device (Brezzo ¶ 0035 teaches a reconfigurable neural network circuit 100)
comprising:
a plurality of neuron circuits (Brezzo, Fig. 1, teaches a synapse array having neurons and synapse circuits [Examiner annotations in dashed-line text boxes]:
PNG
media_image1.png
609
854
media_image1.png
Greyscale
Brezzo ¶ 0027 teaches the “circuit provides a reconfigurable compact and low-power digital CMOS spiking network implementing binary stochastic STDP on a static random access memory (SRAM) synapse array interconnecting digital neurons [(that is, a plurality of neuron circuits)]”);
a plurality of synapse circuits (Brezzo ¶ 0027 & Fig. 1 teaches the “circuit provides a reconfigurable compact and low-power digital CMOS spiking network implementing binary stochastic STDP on a static random access memory (SRAM) synapse array interconnecting digital neurons”; Brezzo ¶ 0034 teaches “binary synapses {(that is, a plurality of synapse circuits)] are implemented using transposable 1-bit SRAM cells”); and
a plurality of random number circuits, wherein
each of the neuron circuits is configured to receive an output signal output from each of one or more of the synapse circuits and output a firing signal in accordance with the received output signal (Brezzo ¶ 0032 teaches “neurons 14 and 16 will “fire” (transmit a pulse) when the inputs they receive from axonal input connections (not shown) [(that is, receive an output signal output from each of one or more of the synapse circuits)] exceed a threshold [(that is, each of the neuron circuits is configured to receive an output signal output from each of one or more of the synapse circuits and output a firing signal in accordance with the received output signal)]”),
each of the random number circuits is configured to output a random signal representing a random number periodically changed (Brezzo ¶ 0028 teaches a “linear feedback shift register (LFSR) generates a new random number (e.g., pseudo random number) during every programming phase [(that is, each of the random number circuits is configured to output a random signal representing a random number periodically changed)]. A comparator provides a digital signal that determines whether or not a connected synapse is updated (i.e., programmed). This implements probabilistic updates of synapses according to the learning rule specified in the decay rate of the counter),
each of the synapse circuits includes:
a storage circuit configured to store a synaptic weight (Brezzo ¶ 0027 teaches “The circuit provides a reconfigurable compact and low-power digital CMOS spiking network implementing binary stochastic STDP on a static random access memory (SRAM) synapse array interconnecting digital neurons. A priority encoder sequentially grants array access to all simultaneously spiking neurons to implement communication of synaptic weights for programming of synapses [(that is, a “SRAM” is a storage circuit configured to store a synaptic weight)]”);
a transmission circuit (Brezzo ¶ 0036 teaches “[d]river circuits 103 receive digital inputs from neurons 5 and programs the synapses 31 in the synapse array 12 using learning rules [(that is, “driver circuits” are a transmission circuit)]”) configured to
receive an input signal being the firing signal output from a pre-neuron circuit being one of the neuron circuits (Brezzo ¶ 0027 & Fig. 2B teaches “[p]erform neuron spiking by pulsing a row (or axon) of the synapse array 12 [(that is, the “axon neuron” is receive an input signal being the firing signal output from a pre-neuron circuit being one of the neuron circuits)]”), and
output an output signal to a post-neuron circuit being one of the neuron circuits (continuing, Brezzo ¶ 0036 teaches “[r]ead value of each synapse 31 in the row and pass the value to a connected neuron 5 [(that is, output an output signal to a post-neuron circuit being one of the neuron circuits)]”), the output signal being obtained by adding influence of the synaptic weight to the received input signal (Brezzo ¶ 0047 teaches “[t]he synapses 31 are binary memory devices, wherein each synapse can have a weight “0” indicating it is non-conducting, or a weight “1” indicating it is conducting [(that is, such “indicating” is the output signal being obtained by adding influence of the synaptic weight to the received input signal )]”);
a probability control circuit (Brezzo, Fig. 3, teaches a digital neuron 5 includes a learning module 7 [Examiner annotations in dashed-line text boxes]:
PNG
media_image2.png
609
1064
media_image2.png
Greyscale
Brezzo ¶ 0043 teaches that “synapses 31 are updated probabilistically according to a learning rule specified in the decay rate of a counter (i.e., counters 7A and 7B) [(that is, “probabilistically” is a probability control circuit )]”)
configured to
receive the random signal from one of the random number circuits (Brezzo ¶ 0043 & Fig. 3 teaches “[d]uring every synapse programming phase, the LFSR 7C generates a new random number. A comparator circuit 7D compares the random number [(that is, receive the random signal from one of the random number circuits)] with a counter value (i.e., from counters 7A and 7B via a multiplexer 7E) to provide a digital signal that determines whether or not a synapse 31 is updated (i.e., programmed)”; as noted above, Brezzo ¶ 0028 teaches “linear feedback shift register (LFSR) generates a new random number (e.g., pseudo random number) during every programming phase”),
permit update of the synaptic weight with a probability generated based on the received random signal (Brezzo, Fig. 8, teaches probabilistic updates [(that is, a probability)] of synapses according to the learning rule specified in the decay rate of the counter [Examiner annotations in dashed-line text boxes]:
PNG
media_image3.png
586
931
media_image3.png
Greyscale
Brezzo ¶ 0043 teaches “causal counter 7B is used for pre-synaptic updates, and the anti-causal counter 7A is used for post-synaptic update (pre-synaptic and post-synaptic updates may utilize different learning rules)”; Brezzo ¶ 0053 teaches “learning mode processes 141, 143, 145 for learning rules STDP, Anti-STDP (A-STDP) and Hebbian, respectively, in the circuit 100 without constant, according to an embodiment of the invention. The learning mode processes are performed in conjunction with neuron circuit 5 in FIG. 2A for probabilistic synapse updates [(that is, for example, “if (tau+ >= LFSR): update ‘1’” is permit update of the synaptic weight with a probability generated based on the received random signal)]”), and
prohibit update of the synaptic weight unless the synaptic weight is permitted to be updated (Brezzo ¶ 0043 teaches the “learning mode processes are performed in conjunction with neuron circuit 5 in FIG. 2A for probabilistic synapse updates [(that is, for example, in causal counter 7B, “if (tau+ < LFSR): no update” is prohibit update of the synaptic weight)]”) . . . . A synapse update may occur regardless of the value of τ [(that is, unless the synaptic weight is permitted to be updated)]”); and
an update circuit configured, when the input signal is received from the pre-neuron circuit, to update the synaptic weight (Brezzo, Fig. 3, teaches a causal counter for pre-synaptic updates [Examiner annotations in dashed-line text boxes]:
PNG
media_image4.png
632
1047
media_image4.png
Greyscale
Brezzo ¶ 0036 teaches that “[e]ach synapse interconnects an axon of a pre-synaptic neuron via a row of the array 12, with a dendrite of a post-synaptic neuron via a column of the array 12; Brezzo ¶ 0043 teaches “causal counter 7B is used for pre-synaptic updates, and the anti-causal counter 7A is used for post-synaptic update (pre-synaptic and post-synaptic updates may utilize different learning rules) [(that is, an update circuit configured, when the input signal is received from the pre-neuron circuit, to update the synaptic weight)]”) . . . ,
the synapse circuits are divided into synapse groups (Brezzo ¶ 0004 teaches “, the point of contact between an axon of a neuron and a dendrite on another neuron is called a synapse, and with respect to the synapse, the two neurons are respectively called pre-synaptic and post-synaptic [(that is, the synapse circuits are divided into synapse groups)]”),
two or more synapse circuits are each configured to receive the random signal output from a first random number circuit out of the random number circuits, the two or more synapse circuits belonging to a first synapse group out of the synapse groups (Brezzo ¶ 0043 teaches “[d]ring every synapse programming phase, the LFSR 7C generates a new random number [(that is, the random signal output from a first random number circuit out of the random number circuits)]. A comparator circuit 7D compares the random number with a counter value (i.e., from counters 7A and 7B via a multiplexer 7E) to provide a digital signal that determines whether or not a synapse 31 is updated (i.e., programmed). As such, synapses 31 [(that is, “synapses 31” is two or more synapse circuits belonging to a first synapse group out of the synapse groups)] are updated probabilistically according to a learning rule specified in the decay rate of a counter (i.e., counters 7A and 7B) [(that is, two or more synapse circuits are each configured to receive the random signal output from a first random number circuit out of the random number circuits, the two or more synapse circuits belonging to a first synapse group out of the synapse groups)]”), and
two or more synapse circuits, each outputting the output signal to a first neuron circuit out of the neuron circuits, belong to a synapse group differing from a synapse group to which other synapse circuits, each outputting the output signal to the first neuron circuit, belong (Brezzo, Fig. 1, teaches dendrite and axon synapse groups [Examiner annotations in dashed-line text boxes]:
PNG
media_image5.png
687
861
media_image5.png
Greyscale
Brezzo ¶ 0032 teaches “[e]ach connection between dendrites 26, 28 [(that is, a synapse group differing from a synapse group differing from a synapse group)] and axons 34, 36 [(that is, a synapse group to which other synapse group . . . belong)] are made through a digital synapse device 31 (synapse). The junctions where the synapse devices are located may be referred to herein as “cross-point junctions”. In general, in accordance with an embodiment of the invention, neurons 14 and 16 will “fire” (transmit a pulse) when the inputs they receive from axonal input connections (not shown) exceed a threshold. Neurons 18 and 20 will “fire” (transmit a pulse) when the inputs they receive from dendritic input connections (not shown) exceed a threshold. [(that is, two or more synapse circuits, each outputting the output signal to a first neuron circuit out of the neuron circuits, belong to a synapse group differing from a synapse group to which other synapse circuits, each outputting the output signal to the first neuron circuit, belong)]”).
Though Brezzo teaches a firing signal representing where a synaptic weight is updated in relation to a STDP update rule, Brezzo, however, does not explicitly teach –
* * *
[an update circuit configured to update the synaptic weight] in accordance with a feedback signal on condition that the synaptic weight is permitted to be updated, the feedback signal representing operation of the post-neuron circuit or a state of the post-neuron circuit,
* * *
But Marukame teaches -
* * *
[an update circuit configured to update the synaptic weight] in accordance with a feedback signal on condition that the synaptic weight is permitted to be updated, the feedback signal representing operation of the post-neuron circuit or a state of the post-neuron circuit (Marukame ¶ 0027 teaches “[e]ach of the neuron circuits 30 updates coefficients assigned to the corresponding synapse circuits 40 [(that is, synaptic weight)] by internally providing feedback of a timing of the pulse signal [(that is, in accordance with a feedback signal on condition that the synaptic weight is permitted to be updated, the feedback signal representing operation of the post-neuron circuit or a state of the post-neuron circuit)]. Specifically, upon generating a pulse signal, the neuron circuit 30 updates a coefficient of a specified synapse circuit 40, which is one of the corresponding synapse circuits 40 and has given the input signal to this neuron circuit 30”),
* * *
Brezzo and Marukame are from the same or similar field of endeavor. Brezzo teaches reconfigurable and customizable general-purpose circuits for neural networks. Marukame teaches a neural network apparatus capable of feeding back a timing of the neuron firing without feedback paths apart from the neurons.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the claimed invention to modify Brezzo pertaining to a reconfigurable and customizable neural network circuits with the feedback without feedback paths apart from the neurons of Marukame.
The motivation to do so is for a “neural network apparatus 10 according to the embodiment is capable of holding energy sources in a form similar to neurons of a human body. Furthermore, the neural network apparatus 10 according to the embodiment is capable of feeding back a timing of the neuron firing without feedback paths apart from the neurons.” (Marukame ¶ 0014).
Regarding claim 2, the combination of Brezzo and Marukame teaches all of the limitations of claim 1, as described above in detail.
Brezzo teaches -
wherein
the random signal represents a random number in a numerical range from a predetermined lower limit value to a predetermined upper limit value (Brezzo ¶ 0036 teaches “probabilistically change a connected synapse value using a pseudo random number generator such as said LFSR [(that is, the random signal represents a random number )]”; Brezzo, Table 1, teaches a fifteen bit LFSR. Accordingly, “000000000000000” is a predetermined lower limit value to “111111111111111” is a predetermined upper limit value)]), and
the probability control circuit is configured to
permit update of the synaptic weight when a` value of the random signal falls within a range corresponding to a predetermined first probability (Brezzo, fig. 9, teaches a constant limit of an update probability [Examiner annotations in dashed-line text boxes]:
PNG
media_image6.png
674
1030
media_image6.png
Greyscale
Brezzo ¶ 0054 teaches “when a constant is involved in the learning process, once τ reaches 0, the constant is compared with a random number from LFSR [(that is, a range corresponding to a predetermined first probability)] and update is performed with a certain probability”), and
prohibit update of the synaptic weight when the value of the random signal falls outside the range corresponding to the first probability (see above, Brezzo, Fig. 9, above, and STDP learning rules, for example, if (tau- becomes 0, . . . if (const < LFSR) : no update [(that is, {that is, prohibit update of the synaptic weight when the value of the random signal falls outside the range corresponding to the first probability)]).
Regarding claim 3, the combination of Brezzo and Marukame teaches all of the limitations of claim 1, as described above in detail.
Brezzo teaches -
wherein each of the two or more synapse circuits belonging to the first synapse group is configured to receive the input signal output from a second neuron circuit out of the neuron circuits (Brezzo ¶ 0036 teaches that “[e]ach synapse interconnects an axon of a pre-synaptic neuron via a row of the array 12, with a dendrite of a post-synaptic neuron via a column of the array 12 [(that is, each of the two or more synapse circuits belong to the first synapse group is configured to receive the input signal output from a second neuron circuit out of the neuron circuits)]”).
Regarding claim 4, the combination of Brezzo and Marukame teaches all of the limitations of claim 1, as described above in detail.
Though Brezzo teaches that a number of LFSRs is “one,” which is used twice to generate the random number for causal and anti-causal update, Brezzo, however, does not explicitly teach -
further comprising a plurality of additional random number circuits (Brezzo ¶ 0028 teaches “[e]ach digital neuron further comprises a learning module including two digital counters . . . . A linear feedback shift register (LFSR) [(that is, for “each digital neuron” is a plurality of additional random number circuits)] generates a new random number (e.g., pseudo random number) during every programming phase”), wherein
each of the additional random number circuits is configured to output an additional random signal representing a random number periodically changed (Brezzo ¶ 0041 teaches, with regard to each digital neuron [(and accordingly, an additional random signal)], “probabilistically change a connected synapse value using a pseudo random number generator such as said LFSR”; Brezzo ¶ 0043 teaches “A LFSR 7C generates sequences that are maximally random. During every synapse programming phase [(that is, periodically)], the LFSR 7C generates a new random number [(that is, each of the additional random number circuits is configured to output an additional random signal representing a random number periodically changed)]”), and
the probability control circuit is configured to:
receive the additional random signal from one of the additional random number circuits (Brezzo ¶ 0043 & Fig. 3 teaches “[d]uring every synapse programming phase, the LFSR 7C generates a new random number. A comparator circuit 7D compares the random number [(that is, receive the additional random signal from one of the additional random number circuits)] with a counter value (i.e., from counters 7A and 7B via a multiplexer 7E) to provide a digital signal that determines whether or not a synapse 31 is updated (i.e., programmed)”; as noted above, Brezzo ¶ 0028 teaches “linear feedback shift register (LFSR) generates a new random number (e.g., pseudo random number) during every programming phase”); and
permit update of the synaptic weight with a probability obtained by multiplying a first probability by a predetermined second probability, the first probability being generated based on the random signal, the second probability being generated based on the additional random signal (Brezzo, Fig. 8, teaches probabilistic updates [(that is, a first probability and a predetermined second probability)] of synapses according to the learning rule specified in the decay rate of the counter [Examiner annotations in dashed-line text boxes]:
PNG
media_image3.png
586
931
media_image3.png
Greyscale
Brezzo ¶ 0043 teaches “causal counter 7B is used for pre-synaptic updates, and the anti-causal counter 7A is used for post-synaptic update (pre-synaptic and post-synaptic updates may utilize different learning rules)”; Brezzo ¶ 0053 teaches “learning mode processes 141, 143, 145 for learning rules STDP, Anti-STDP (A-STDP) and Hebbian, respectively, in the circuit 100 without constant, according to an embodiment of the invention. The learning mode processes are performed in conjunction with neuron circuit 5 in FIG. 2A for probabilistic synapse updates [(that is, for example, “if (tau+ >= LFSR): update ‘1’” is permit update of the synaptic weight with a probability obtained by multiplying a first probability by a predetermined second probability, the first probability being generated based on the random signal, the second probability being generated based on the additional random sign)]”; with regard to “multiplying,” Brezzo ¶ 0034-35 teaches the “Digital neurons . . . receive spike inputs and integrate them. The neurons include comparator circuits that generate spikes when the integrated input exceeds a threshold. . . . [F]ully connected synapse array 12 stores the strength of connection between each neuron 5 (e.g., integrate and fire electronic neuron). Each digital neuron 5 receives spike inputs from one or more other neurons and integrates them, such that when the integrated input exceeds a threshold, the digital neuron 5 spikes [(that is, “integrating” is multiplying a first probability by a predetermined second probability)]”’
[Examiner notes that plain meaning of “multiplying” is the finding of products of numbers, such as probabilities. The broadest reasonable interpretation of the term “multiplying” covers the teachings of Brezzo pertaining to integrating spikes, where integration is a continuous or generalized form of multiplication that works when one or both quantities involved are changing, which pertains to the claimed “a probability obtained by multiplying a first probability by a predetermined second probability”]).
Regarding claim 5, the combination of Brezzo and Marukame teaches all of the limitations of claim 4, as described above in detail.
Brezzo teaches -
wherein
the additional random signal represents a random number in a numerical range from a predetermined lower limit value to a predetermined upper limit value (Brezzo ¶ 0036 teaches “probabilistically change a connected synapse value using a pseudo random number generator such as said LFSR [(that is, the additional random signal represents a random number )]”; Brezzo, Table 1, teaches a fifteen bit LFSR. Accordingly, “000000000000000” is a predetermined lower limit value to “111111111111111” is a predetermined upper limit value)]), and
the probability control circuit is configured to:
permit update of the synaptic weight when a value of the random signal falls within a range corresponding to the first probability (Brezzo, fig. 9, teaches a constant limit of an update probability [Examiner annotations in dashed-line text boxes]:
PNG
media_image6.png
674
1030
media_image6.png
Greyscale
Brezzo ¶ 0054 teaches “when a constant is involved in the learning process, once τ reaches 0, the constant is compared with a random number from LFSR [(that is, a range corresponding to a predetermined first probability)] and update is performed with a certain probability”) and a value of the additional random signal falls within a range corresponding to the second probability (Brezzo ¶ 0041 teaches, with regard to each digital neuron [(and accordingly, an additional random signal)]; Brezzo ¶ 0054 teaches “when a constant is involved in the learning process, once τ reaches 0, the constant is compared with a random number from LFSR [(that is, a value of the additional random signal falls within a range corresponding to the second probability)] and update is performed with a certain probability”); and
prohibit update of the synaptic weight when the value of the random signal falls outside the range corresponding to the first probability (see above, Brezzo, Fig. 9, above, and STDP learning rules, for example, if (tau- becomes 0, . . . if (const < LFSR) : no update [(that is, {that is, prohibit update of the synaptic weight when the value of the random signal falls outside the range corresponding to the first probability)]), or when the value of the additional random signal falls outside the range corresponding to the second probability.
Regarding claim 6, the combination of Brezzo and Marukame teaches all of the limitations of claim 4, as described above in detail.
Brezzo teaches -
wherein
the additional random number circuits are provided to have a one-to-one correspondence with the neuron circuits (Brezzo ¶ 0028 teaches “[e]ach digital neuron further comprises a learning module including two digital counters . . . . A linear feedback shift register (LFSR) [(that is, for “each digital neuron” is the additional random number circuits)] generates a new random number (e.g., pseudo random number) during every programming phase”; Brezzo ¶ 0042 teaches that each “(Brezzo ¶ 0028 teaches “[e]ach digital neuron further comprises a learning module including two digital counters . . . . A linear feedback shift register (LFSR) [(that is, for “each digital neuron” is the additional random number circuits are provided to have a one-to-one correspondence with the neuron circuits)] generates a new random number (e.g., pseudo random number) during every programming phase”), and
each of the synapse circuits is configured to receive the additional random signal from one of the additional random number circuits corresponding to a neuron circuit to which the output signal is output (Brezzo ¶ 0046 & Fig. 3 teaches “circuit 100 comprises a first learning module for an axonal, pre-synaptic, neuron, and a second learning module for a dendritic, post-synaptic neuron [(that is, “the second learning module has a LFSR for a random number generator,” which is each of the synapse circuits is configured to receive the additional random signal from one of the additional random number circuits corresponding to a neuron circuit to which the output signal is output)]”).
Regarding claim 8, the combination of Brezzo and Marukame teaches all of the limitations of claim 1, as described above in detail.
Marukame teaches -
wherein
the feedback signal is represented by a first value or a second value (Marukame ¶ 0027 teaches “[e]ach of the neuron circuits 30 updates coefficients assigned to the corresponding synapse circuits 40 [(that is, synaptic weight)] by internally providing feedback of a timing of the pulse signal [(that is, the feedback signal is represented by a first value or a second value)]”),
* * *
Brezzo teaches –
* * *
the update circuit is configured to:
when the input signal is received in a state where the feedback signal has the first value, change the synaptic weight in an increment direction on condition that the synaptic weight is permitted to be updated (Brezzo, fig. 9, teaches mode processes for STDP learning rules [Examiner annotations in dashed-line text boxes]:
PNG
media_image7.png
901
1231
media_image7.png
Greyscale
Brezzo ¶ 0004 teaches “[t]he STDP rule increases [(that is, an increment direction)] the conductance of a synapse if its post-synaptic neuron fires after its pre-synaptic neuron fires [(that is, a feedback signal)]”; Brezzo, fig. 9, above, teaches anti-STDP 148 [(that is, when the input signal is received in a state where the feedback signal has the first value, change the synaptic weight in an increment direction on condition that the synaptic weight is permitted to be updated)]); and,
when the input signal is received in a state where the feedback signal has the second value, change the synaptic weight in a decrement direction on condition that the synaptic weight is permitted to be updated (Brezzo ¶ 0004 teaches “[t]he STDP rule . . . decreases [(that is, a decrement direction)] the conductance of a synapse if the order of the two firings is reversed [(that is, a feedback signal)]; Brezzo, Fig. 9, above, teaches a STDP 147 [(that is, when the input signal is received in a state where the feedback signal has the second value, change the synaptic weight in a decrement direction on condition that the synaptic weight is permitted to be updated)]), and
the probability control circuit is configured to:
when the synaptic weight is changed in the increment direction, permit update of the synaptic weight with a predetermined first increase probability generated based on the random signal (Brezzo, Fig. 9, above, teaches anti-STDP 148 having associated STDP learning rules relating to changes in synaptic weight in an increment direction [(that is, when the synaptic weight is changed in the increment direction, permit update of the synaptic weight with a predetermined first increase probability generated based on the random signal)]); and,
when the synaptic weight is changed in the decrement direction, permit update of the synaptic weight with a predetermined first decrease probability generated based on the random signal (Brezzo, Fig. 9, above, teaches STDP 147 having associated STDP learning rules relating to changes in synaptic weight in a decrement direction [(that is, when the synaptic weight is changed in the increment direction, permit update of the synaptic weight with a predetermined first increase probability generated based on the random signal))]).
Regarding claim 9, the combination of Brezzo and Marukame teaches all of the limitations of claim 4, as described above in detail.
Marukame teaches -
wherein
the feedback signal is represented by a first value or a second value (Marukame ¶ 0027 teaches “[e]ach of the neuron circuits 30 updates coefficients assigned to the corresponding synapse circuits 40 [(that is, synaptic weight)] by internally providing feedback of a timing of the pulse signal [(that is, the feedback signal is represented by a first value or a second value)]”),
* * *
Brezzo teaches –
* * *
the update circuit is configured to:
when the input signal is received in a state where the feedback signal has the first value, change the synaptic weight in an increment direction on condition that the synaptic weight is permitted to be updated (Brezzo, Fig. 9, teaches mode processes for STDP learning rules [Examiner annotations in dashed-line text boxes]:
PNG
media_image7.png
901
1231
media_image7.png
Greyscale
Brezzo ¶ 0004 teaches “[t]he STDP rule increases [(that is, an increment direction)] the conductance of a synapse if its post-synaptic neuron fires after its pre-synaptic neuron fires [(that is, a feedback signal)]”; Brezzo, fig. 9, above, teaches anti-STDP 148 [(that is, when the input signal is received in a state where the feedback signal has the first value, change the synaptic weight in an increment direction on condition that the synaptic weight is permitted to be updated)]”), which is ); and,
when the input signal is received in a state where the feedback signal has the second value, change the synaptic weight in a decrement direction on condition that the synaptic weight is permitted to be updated (Brezzo ¶ 0004 teaches “[t]he STDP rule . . . decreases [(that is, a decrement direction)] the conductance of a synapse if the order of the two firings is reversed [(that is, a feedback signal)]; Brezzo, Fig. 9, above, teaches a STDP 147 [(that is, when the input signal is received in a state where the feedback signal has the second value, change the synaptic weight in a decrement direction on condition that the synaptic weight is permitted to be updated)]), and
the probability control circuit is configured to:
when the synaptic weight is changed in the increment direction, permit update of the synaptic weight with a probability obtained by multiplying a predetermined first increase probability by a predetermined second increase probability, the first increase probability being generated based on the random signal, the second increase probability being generated based on the additional random signal (Brezzo, Fig. 9, above, teaches probabilistic updates [(that is, a first probability and a predetermined second probability)] of synapses according to the learning rule specified in the decay rate of the counter [(that is, when the synaptic weight is changed in the increment direction, permit update of the synaptic weight with a probability obtained by multiplying a predetermined first increase probability by a predetermined second increase probability, the first increase probability being generated based on the random signal, the second increase probability being generated based on the additional random signal)]; with regard to “multiplying,” Brezzo ¶ 0034-35 teaches the “Digital neurons . . . receive spike inputs and integrate them [(that is, multiplying)]. The neurons include comparator circuits that generate spikes when the integrated input exceeds a threshold. . . . [F]ully connected synapse array 12 stores the strength of connection between each neuron 5 (e.g., integrate and fire electronic neuron). Each digital neuron 5 receives spike inputs from one or more other neurons and integrates them, such that when the integrated input exceeds a threshold, the digital neuron 5 spikes [(that is, “integrating” is multiplying a first probability by a predetermined second probability)]”’
[Examiner notes that plain meaning of “multiplying” is the finding of products of numbers, such as probabilities. The broadest reasonable interpretation of the term “multiplying” covers the teachings of Brezzo pertaining to integrating spikes, where integration is a continuous or generalized form of multiplication that works when one or both quantities involved are changing, which pertains to the claimed “a probability obtained by multiplying a first probability by a predetermined second probability”]); and
when the synaptic weight is changed in the decrement direction, permit update of the synaptic weight with a probability obtained by multiplying a predetermined first decrease probability by a predetermined second decrease probability, the first decrease probability being generated based on the random signal, the second decrease probability being generated based on the additional random signal (Brezzo, Fig. 9, above, teaches probabilistic updates [(that is, a first probability and a predetermined second probability)] of synapses according to the learning rule specified in the decay rate of the counter; with regard to “multiplying,” Brezzo ¶ 0034-35 teaches the “Digital neurons . . . receive spike inputs and integrate them [(that is, multiplying)]. The neurons include comparator circuits that generate spikes when the integrated input exceeds a threshold. . . . [F]ully connected synapse array 12 stores the strength of connection between each neuron 5 (e.g., integrate and fire electronic neuron). Each digital neuron 5 receives spike inputs from one or more other neurons and integrates them, such that when the integrated input exceeds a threshold, the digital neuron 5 spikes [(that is, “integrating” is multiplying a first probability by a predetermined second probability)]”).
Regarding claim 10, the combination of Brezzo and Marukame teach all of the limitations of claim 8, as described above in detail.
Brezzo teaches -
wherein
the synaptic weight is changed in a predetermined numerical range (Brezzo ¶ 0043 teaches “learning module 7 includes digital counters 7A and 7B, which decay at a pre-specified rate each time step and are reset to a pre-defined value when the neuron spikes. A LFSR 7C generates sequences that are maximally random. During every synapse programming phase, the LFSR 7C generates a new random number. . . . As such, synapses 31 are updated probabilistically according to a learning rule specified in the decay rate [(that is, a predetermined numerical range)] of a counter (i.e., counters 7A and 7B)), and
the storage circuit is configured not to change the synaptic weight to become equal to or larger than an upper limit value of the numerical range, and not to change the synaptic weight to become equal to or smaller than a lower limit value of the numerical range (Nishi at p. 2, paragraph 4, teaches “Weight change in standard STDP models generally depends not only on tpre − tpost but also on the present weight value of the target synapse. This is originated from the fact that the dynamic range of a synaptic weight is not unlimited and has its upper and lower bounds [(that is, the storage the storage circuit is configured not to change the synaptic weight to become equal to or larger than an upper limit value of the numerical range, and not to change the synaptic weight to become equal to or smaller than a lower limit value of the numerical range)]”).
Regarding claim 11, the combination of Brezzo and Marukame teaches all of the limitations of claim 8, as described above in detail.
Brezzo teaches -
wherein the feedback signal has the first value for a given period of time after firing of the post-neuron circuit and has the second value for a period of time other than the given period (Brezzo ¶ 0004 teaches the “synaptic conductance changes with time as a function of the relative spike times of presynaptic and post-synaptic neurons, as per spike-timing dependent plasticity (STDP). The STDP rule increases the conductance of a synapse if its post-synaptic neuron fires after its pre-synaptic neuron fires [(that is, the first value for a given period of time after firing of the post-neuron circuit)], and decreases the conductance of a synapse if the order of the two firings is reversed [(that is, the second value for a period of time other than the given period)]”).
Regarding claim 12, the combination of Brezzo and Marukame teaches all of the limitations of claim 8, as described above in detail.
Brezzo teaches -
wherein
each of the neuron circuits is configured to
hold an inner potential varied with a level or duration of the received output signal (Brezzo ¶ 0041 teaches “[e]ach neuron 5 checks a column (or dendrite) of the synapse array 12 for synapses 31 in their “pulsed” state and reads the synapse values [(that is, a level or duration of the received output signal)], and integrates the synapse (excitatory/inhibitory) inputs as external input to the neuron potential [(that is, hold an inner potential varied with a level or duration of the received output signal)]”), and
output the firing signal when the inner potential is larger than a preset firing threshold (Brezzo ¶ 0042 teaches the “value in the adder circuit 6B represents the potential of the neuron 5 (e.g., voltage potential V based on accumulated input spikes). A comparator circuit 6C is used to check if the current value in the adder 6B is above a threshold value. The output of the comparator 6C is used to signal neuron spiking [(that is, output the firing signal when the inner potential is larger than a preset firing threshold)]”), and
the feedback signal has the first value when the inner potential held by the post-neuron circuit is equal to or larger than a predetermined value and has the second value when the inner potential is smaller than the predetermined value (Brezzo ¶ 0042 & Fig. 3 teaches “[i]n the integration and spike module 6, a multiplexer circuit 6A is used to select all the inputs arriving at the neuron 5 to integrate to a value held at an adder circuit 6B. The value in the adder circuit 6B represents the potential of the neuron 5 (e.g., voltage potential V based on accumulated input spikes). A comparator circuit 6C is used to check if the current value in the adder 6B is above a threshold value. The output of the comparator 6C is used to signal neuron spiking. This spike signal is then sent to the priority encoder 101 which then grants the neuron 5 access to the crossbar synapse array 12 in a sequential manner”).
Regarding claim 13, the combination of Brezzo and Marukame teaches all of the limitations of claim 1, described above in detail.
Brezzo teaches -
wherein the synaptic weight is represented by a discrete value (Brezzo ¶ 0027 teaches “[d]river module [of the reconfigurable neural network circuit 100] receives digital inputs from neurons for programming the synapse array using programming phases. Sense amplifiers measure the state of each synapse and convert it to binary data [(that is, “binary data” is a discrete value)], representing data stored in the synapse [(that is, wherein the synaptic weight is represented by a discrete value)]”).
Regarding claim 14, the combination of Brezzo and Marukame teaches all of the limitations of claim 13, described above in detail.
Brezzo teaches -
wherein the synaptic weight is represented in binary (Brezzo ¶ 0027 teaches “[d]river module [of the reconfigurable neural network circuit 100] receives digital inputs from neurons for programming the synapse array using programming phases. Sense amplifiers measure the state of each synapse and convert it to binary data, representing data stored in the synapse [(that is, wherein the synaptic weight is represented in binary)]”).
Regarding claim 15, the combination of Brezzo and Marukame teaches all of the limitations of claim 1, described above in detail.
Brezzo teaches -
wherein at least one of the synapse circuits is configured to supply the output signal to the pre-neuron circuit in the neuron circuits or to a neuron circuit disposed in a stage previous to a synapse circuit from which the output signal is supplied to the pre-neuron circuit (Brezzo, Fig. 1, teaches synapse circuits providing the output signal to a pre-synaptic neuron circuit [Examiner annotations in dashed-line text boxes]:
PNG
media_image8.png
569
799
media_image8.png
Greyscale
Brezzo ¶ 0036 teaches “[e]ach synapse interconnects an axon of a pre-synaptic neuron via a row of the array 12, with a dendrite of a post-synaptic neuron via a column of the array 12 [(that is, wherein at least one of the synapse circuits is configured to supply the output signal to the pre-neuron circuit in the neuron circuits . . .)]”).
Regarding claim 16, Brezzo teaches [a] synaptic weight update method implemented by a computer as a neural network device (Brezzo ¶¶ 0035-36 teaches “a reconfigurable neural network circuit 100 . . . . [T]he circuit 100 goes through the following sequence of phases for synapse updating (programming) based on signals from the global finite state machine [(that is, a synaptic weight update method implemented by a computer as a neural network device)]”), the neural network device including:
a plurality of neuron circuits (Brezzo, Fig. 1, teaches a synapse array having neurons and synapse circuits [Examiner annotations in dashed-line text boxes]:
PNG
media_image1.png
609
854
media_image1.png
Greyscale
Brezzo ¶ 0027 teaches the “circuit provides a reconfigurable compact and low-power digital CMOS spiking network implementing binary stochastic STDP on a static random access memory (SRAM) synapse array interconnecting digital neurons [(that is, a plurality of neuron circuits)]”);
a plurality of synapse circuits (Brezzo ¶ 0027 & Fig. 1 teaches the “circuit provides a reconfigurable compact and low-power digital CMOS spiking network implementing binary stochastic STDP on a static random access memory (SRAM) synapse array interconnecting digital neurons”; Brezzo ¶ 0034 teaches “binary synapses {(that is, a plurality of synapse circuits)] are implemented using transposable 1-bit SRAM cells”); and
a plurality of random number circuits, wherein
each of the neuron circuits is configured to receive an output signal output from each of one or more of the synapse circuits and output a firing signal in accordance with the received output signal (Brezzo ¶ 0032 teaches “neurons 14 and 16 will “fire” (transmit a pulse) when the inputs they receive from axonal input connections (not shown) [(that is, receive an output signal output from each of one or more of the synapse circuits)] exceed a threshold [(that is, each of the neuron circuits is configured to receive an output signal output from each of one or more of the synapse circuits and output a firing signal in accordance with the received output signal)]”),
each of the random number circuits is configured to output a random signal representing a random number periodically changed (Brezzo ¶ 0028 teaches a “linear feedback shift register (LFSR) generates a new random number (e.g., pseudo random number) during every programming phase [(that is, each of the random number circuits is configured to output a random signal representing a random number periodically changed)]. A comparator provides a digital signal that determines whether or not a connected synapse is updated (i.e., programmed). This implements probabilistic updates of synapses according to the learning rule specified in the decay rate of the counter),
each of the synapse circuits includes:
a storage circuit configured to store a synaptic weight (Brezzo ¶ 0027 teaches “The circuit provides a reconfigurable compact and low-power digital CMOS spiking network implementing binary stochastic STDP on a static random access memory (SRAM) synapse array interconnecting digital neurons. A priority encoder sequentially grants array access to all simultaneously spiking neurons to implement communication of synaptic weights for programming of synapses [(that is, a “SRAM” is a storage circuit configured to store a synaptic weight)]”); and
a transmission circuit (Brezzo ¶ 0036 teaches “[d]river circuits 103 receive digital inputs from neurons 5 and programs the synapses 31 in the synapse array 12 using learning rules [(that is, “driver circuits” are a transmission circuit)]”) configured to
receive an input signal being the firing signal output from a pre-neuron circuit being one of the neuron circuits (Brezzo ¶ 0027 & Fig. 2B teaches “[p]erform neuron spiking by pulsing a row (or axon) of the synapse array 12 [(that is, the “axon neuron” is receive an input signal being the firing signal output from a pre-neuron circuit being one of the neuron circuits)]”), and
output an output signal to a post-neuron circuit being one of the neuron circuits (continuing, Brezzo ¶ 0036 teaches “[r]ead value of each synapse 31 in the row and pass the value to a connected neuron 5 [(that is, output an output signal to a post-neuron circuit being one of the neuron circuits)]”), the output signal being obtained by adding influence of the synaptic weight to the received input signal (Brezzo ¶ 0047 teaches “[t]he synapses 31 are binary memory devices, wherein each synapse can have a weight “0” indicating it is non-conducting, or a weight “1” indicating it is conducting [(that is, such “indicating” is the output signal being obtained by adding influence of the synaptic weight to the received input signal )]”),
the synapse circuits are divided into synapse groups (Brezzo ¶ 0004 teaches “, the point of contact between an axon of a neuron and a dendrite on another neuron is called a synapse, and with respect to the synapse, the two neurons are respectively called pre-synaptic and post-synaptic [(that is, the synapse circuits are divided into synapse groups)]”),
two or more synapse circuits are each configured to receive the random signal output from a first random number circuit out of the random number circuits, the two or more synapse circuits belonging to a first synapse group out of the synapse groups (Brezzo ¶ 0043 teaches “[d]ring every synapse programming phase, the LFSR 7C generates a new random number [(that is, the random signal output from a first random number circuit out of the random number circuits)]. A comparator circuit 7D compares the random number with a counter value (i.e., from counters 7A and 7B via a multiplexer 7E) to provide a digital signal that determines whether or not a synapse 31 is updated (i.e., programmed). As such, synapses 31 [(that is, “synapses 31” is two or more synapse circuits belonging to a first synapse group out of the synapse groups)] are updated probabilistically according to a learning rule specified in the decay rate of a counter (i.e., counters 7A and 7B) [(that is, two or more synapse circuits are each configured to receive the random signal output from a first random number circuit out of the random number circuits, the two or more synapse circuits belonging to a first synapse group out of the synapse groups)]”), and
two or more synapse circuits, each outputting the output signal to a first neuron circuit out of the neuron circuits, belong to a synapse group differing from a synapse group to which other synapse circuits, each outputting the output signal to the first neuron circuit, belong (Brezzo, Fig. 1, teaches dendrite and axon synapse groups [Examiner annotations in dashed-line text boxes]:
PNG
media_image5.png
687
861
media_image5.png
Greyscale
Brezzo ¶ 0032 teaches “[e]ach connection between dendrites 26, 28 [(that is, a synapse group differing from a synapse group differing from a synapse group)] and axons 34, 36 [(that is, a synapse group to which other synapse group . . . belong)] are made through a digital synapse device 31 (synapse). The junctions where the synapse devices are located may be referred to herein as “cross-point junctions”. In general, in accordance with an embodiment of the invention, neurons 14 and 16 will “fire” (transmit a pulse) when the inputs they receive from axonal input connections (not shown) exceed a threshold. Neurons 18 and 20 will “fire” (transmit a pulse) when the inputs they receive from dendritic input connections (not shown) exceed a threshold. [(that is, two or more synapse circuits, each outputting the output signal to a first neuron circuit out of the neuron circuits, belong to a synapse group differing from a synapse group to which other synapse circuits, each outputting the output signal to the first neuron circuit, belong)]”), and
each of the synapse circuits executes processing including:
receiving the random signal from one of the random number circuits (Brezzo ¶ 0043 & Fig. 3 teaches “[d]uring every synapse programming phase, the LFSR 7C generates a new random number. A comparator circuit 7D compares the random number [(that is, receiving the random signal from one of the random number circuits)] with a counter value (i.e., from counters 7A and 7B via a multiplexer 7E) to provide a digital signal that determines whether or not a synapse 31 is updated (i.e., programmed)”; as noted above, Brezzo ¶ 0028 teaches “linear feedback shift register (LFSR) generates a new random number (e.g., pseudo random number) during every programming phase”);
permitting update of the synaptic weight with a probability generated based on the received random signal (Brezzo, Fig. 8, teaches probabilistic updates [(that is, a probability)] of synapses according to the learning rule specified in the decay rate of the counter [Examiner annotations in dashed-line text boxes]:
PNG
media_image3.png
586
931
media_image3.png
Greyscale
Brezzo ¶ 0043 teaches “causal counter 7B is used for pre-synaptic updates, and the anti-causal counter 7A is used for post-synaptic update (pre-synaptic and post-synaptic updates may utilize different learning rules)”; Brezzo ¶ 0053 teaches “learning mode processes 141, 143, 145 for learning rules STDP, Anti-STDP (A-STDP) and Hebbian, respectively, in the circuit 100 without constant, according to an embodiment of the invention. The learning mode processes are performed in conjunction with neuron circuit 5 in FIG. 2A for probabilistic synapse updates [(that is, for example, “if (tau+ >= LFSR): update ‘1’” is permitting update of the synaptic weight with a probability generated based on the received random signal)]”);
prohibiting update of the synaptic weight unless the synaptic weight is permitted to be updated (Brezzo ¶ 0043 teaches the “learning mode processes are performed in conjunction with neuron circuit 5 in FIG. 2A for probabilistic synapse updates [(that is, for example, in causal counter 7B, “if (tau+ < LFSR): no update” is prohibiting update of the synaptic weight)]”) . . . . A synapse update may occur regardless of the value of τ [(that is, unless the synaptic weight is permitted to be updated)]”); and,
when the input signal is received from the pre-neuron circuit, updating the synaptic weight (Brezzo, Fig. 3, teaches a causal counter for pre-synaptic updates [Examiner annotations in dashed-line text boxes]:
PNG
media_image4.png
632
1047
media_image4.png
Greyscale
Brezzo ¶ 0036 teaches that “[e]ach synapse interconnects an axon of a pre-synaptic neuron via a row of the array 12, with a dendrite of a post-synaptic neuron via a column of the array 12; Brezzo ¶ 0043 teaches “causal counter 7B is used for pre-synaptic updates, and the anti-causal counter 7A is used for post-synaptic update (pre-synaptic and post-synaptic updates may utilize different learning rules) [(that is, when the input signal is received from the pre-neuron circuit, updating the synaptic weight)]”) . . . .
Though Brezzo teaches a firing signal representing where a synaptic weight is updated in relation to a STDP update rule, Brezzo, however, does not explicitly teach –
* * *
[updating the synaptic weight] in accordance with a feedback signal on condition that the synaptic weight is permitted to be updated, the feedback signal representing operation of the post-neuron circuit or a state of the post-neuron circuit,
* * *
But Marukame teaches -
* * *
[updating the synaptic weight] in accordance with a feedback signal on condition that the synaptic weight is permitted to be updated, the feedback signal representing operation of the post-neuron circuit or a state of the post-neuron circuit (Marukame ¶ 0027 teaches “[e]ach of the neuron circuits 30 updates coefficients assigned to the corresponding synapse circuits 40 [(that is, synaptic weight)] by internally providing feedback of a timing of the pulse signal [(that is, in accordance with a feedback signal on condition that the synaptic weight is permitted to be updated, the feedback signal representing operation of the post-neuron circuit or a state of the post-neuron circuit)]. Specifically, upon generating a pulse signal, the neuron circuit 30 updates a coefficient of a specified synapse circuit 40, which is one of the corresponding synapse circuits 40 and has given the input signal to this neuron circuit 30”),
* * *
Brezzo and Marukame are from the same or similar field of endeavor. Brezzo teaches reconfigurable and customizable general-purpose circuits for neural networks. Marukame teaches a neural network apparatus capable of feeding back a timing of the neuron firing without feedback paths apart from the neurons.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the claimed invention to modify Brezzo pertaining to a reconfigurable and customizable neural network circuits with the feedback without feedback paths apart from the neurons of Marukame.
The motivation to do so is for a “neural network apparatus 10 according to the embodiment is capable of holding energy sources in a form similar to neurons of a human body. Furthermore, the neural network apparatus 10 according to the embodiment is capable of feeding back a timing of the neuron firing without feedback paths apart from the neurons.” (Marukame ¶ 0014).
10. Claim 7 is rejected under 35 U.S.C. § 103 as being unpatentable over US Published Application 20120259804 to Brezzo et al. [hereinafter Brezzo] in view of US Published Application 20200302274 to Marukame et al. [hereinafter Marukame] and Nishi et al., "Stochastic binary synapses having sigmoidal cumulative distribution functions for unsupervised learning with spike timing‑dependent plasticity," Nature (2021) [hereinafter Nishi].
Regarding claim 7, the combination of Brezzo and Marukame teaches all of the limitations of claim 4, as described above in detail.
Though Brezzo and Marukame teaches each neuron including a learning modules for probabilistic synapse updates, the combination of Brezzo and Marukame, however, do not explicitly teach –
wherein the first probability is larger than the second probability.
But Nishi teaches -
wherein the first probability is larger than the second probability (Nishi, Fig. 1a, teaches transition probabilities [Examiner annotations in dashed-line text boxes]:
PNG
media_image9.png
371
461
media_image9.png
Greyscale
Nishi, Fig. 1a & caption teaches “While the synaptic weight update has exponential-like dependence on tpost − tpre in standard STDP (broken curves), S-STDP is characterised by a rectangular dependence (green line). Since an update takes place at the occurrence of a post-neuron’s fire, we only consider the case of tpost − tpre > 0 for S-STDP. In the scheme of stochastic S-STDP with binary weights, the weight change η+ and η− are read as the transition probabilities p from w = 0 to 1 for potentiation and q from 1 to 0 for depression, respectively [(that is, wherein the first probability is larger than the second probability)]”; see also Nishi at p. 2, “Expected Weights in Stochastic S-STDP,” last partial paragraph, which teaches “[s]electing [probabilities] p and q appropriately, we can observe relatively high accuracy for conventional stochastic S-STDP. Our best accuracy 85.5% is achieved with [probabilities] p = 0.04 and q = 0.008”).
Brezzo and Marukame are from the same or similar field of endeavor. Brezzo teaches reconfigurable and customizable general-purpose circuits for neural networks. Marukame teaches a neural network apparatus capable of feeding back a timing of the neuron firing without feedback paths apart from the neurons. Nishi teaches spike timing-dependent plasticity (STDP) based on a stochastic binary synaptic model where the cumulative probability of the weight change evolves in a sigmoidal fashion with potentiation or depression trials.
Thus, it would have been obvious to a person having ordinary skill in the art as of the effective filing date of the claimed invention to modify the combination of Brezzo and Marukame pertaining to a reconfigurable and customizable neural network circuits with the feedback without feedback paths apart from the neurons with the first probability p and second probability q of Nishi.
The motivation to do so is because the “simplified STDP in combination with unsupervised learning can outperform conventional rules with continuous weights not only in memory maintenance but also in recognition accuracy. Our method achieves 97.3% in recognition accuracy, which is higher than that reported with standard STDP in the same framework. We also show that the high performance of our learning rule is robust against device-to-device variability of the memristor’s probabilistic behaviour.” (Nishi, Abstract).
Conclusion
11. The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
(US Published Application 20210279559 to Nishi et al.) teaches A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a determinator, a synaptic depressor, and a synaptic potentiator. The synaptic element has a variable weight and outputs, in response to input of a first spike signal, a synaptic signal having intensity adjusted in accordance with the weight. The neuron circuit outputs a second spike signal in a case where the synaptic signal is inputted and a predetermined firing condition for the synaptic signal is satisfied. The determinator determines whether or not the weight is to be updated on a basis of an output frequency of the second spike signal by the neuron circuit. The synaptic depressor performs depression operation for depressing the weight in a case where it is determined that the weight is to be updated. The synaptic potentiator performs potentiating operation for potentiating the weight.
(Detorakis et al., “Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning,” arXiv (2018)) teaches neural and synaptic array transceiver (NSAT), a neuromorphic computational framework facilitating flexible and efficient embedded learning by matching algorithmic requirements and neural and synaptic dynamics.
12. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to KEVIN L. SMITH whose telephone number is (571) 272-5964. Normally, the Examiner is available on Monday-Thursday 0730-1730.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, KAKALI CHAKI can be reached on 571-272-3719. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.L.S./
Examiner, Art Unit 2122
/KAKALI CHAKI/Supervisory Patent Examiner, Art Unit 2122
Prosecution Insights