DETAILED ACTION
Claims 1-20 are presented for examination.
Claims 1-20 are amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding the rejection of independent claims 7, 12 and 17, claims 7, 12 and 17 recite the same limitations as set forth in claim 1, the response to claim 1 is also applicable to claims 7, 12 and 17, and thus please refer to the response to claim 1 above.
Regarding the dependent claims 2-6, 8-11, 13-16 and 18-20, Applicant has not made specific arguments pertaining to why the cited references do not teach the recited claims. Without such arguments, the Examiner cannot respond and is not persuaded by such argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 3, 4, 5, 6, 12, 13, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jerolm (US 20200092132 A1) in view of Schultz (US 20120221755 A1).
Regarding claim 1, Jerolm teaches an address assignment apparatus comprising:
a bus line coupled to the gateway to receive the address signal ([0044] The local bus master 3 (gateway) in the exemplary embodiment shown here has a further second interface in order to connect the local bus master 3 to the local bus (contains address assignment line), wherein the local bus in the embodiment shown here is designed as a ring bus 6. In this case, the second interface is divided into a first part 5a and a second part 5b. The first part 5a of the second interface establishes the downlink in the ring bus 6 and the second part 5b of the second interface establishes the uplink in the ring bus 6. [0008] The local bus master can therefore also be designed as a gateway.), wherein the address assignment line is provided with a plurality of switches (Fig. 1 shows the data bus (address assignment line) with a plurality of module units (connection units) along the data bus. [0045] The ring bus 6, whose data transmission direction is shown with arrows in the exemplary embodiment shown in FIG. 1, has a plurality of module units 8a, 8b, . . . , 8n. [0038] FIG. 2 is a schematic circuit diagram of an embodiment of the module unit according to the invention without a data bus subscriber arranged thereon with the switch in the first switching state. Each module unit contains a switch; therefore the address assignment line is provided with a plurality of switches.)
a plurality of connection units disposed in series along the bus line and each adapted to be connected to a bus device among a plurality of bus devices that are structurally separate devices than the plurality of connection units (Fig. 1 shows module units (8a, 8b, 8n) (connection units) and structurally separate data bus subscribers (20a, 20b, ..., 20n) (bus devices). [0045] The ring bus 6, whose data transmission direction is shown with arrows in the exemplary embodiment shown in FIG. 1, has a plurality of module units 8a, 8b, . . . , 8n for connection to data bus subscribers 20a, 20b, . . . , 20n in the exemplary embodiment shown here. [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n. [0010] In a ring bus, the data bus subscribers…are each connected to the data bus subscriber directly adjacent to them and data is forwarded in order from one to the other data bus subscriber (connected in series). Thus, the data is not sent to all data bus subscribers at the same time, but in turn, wherein a data bus subscriber receives data from its upstream data bus subscriber and forwards data to its downstream data bus subscriber. Between receiving the data and forwarding, the data bus subscriber can process the received data.)
wherein each of the plurality of switches is located within one of the plurality of connection units ([0013] the module unit (connection unit) according to the invention has a first switch device, which is adapted to assume a first or a second switching state in response to a control input from the data bus subscriber. [0055] the module unit 8a has a first switch 23 for the downlink direction and a second optional switch 24 for the uplink direction. [0058] The switches 23, 24 may be integrated in the module unit 8a.)
wherein each of the plurality of switches is a normally closed switch configured to passively propagate the address signal through a respective connection unit in which that normally closed switch is located ([0027] For example, both switches may initially be in the first switching state, i.e., provide a forwarding of signals in the downlink and uplink direction (normally closed). [0030] The first switch and/or the second switch can be adapted to assume the first switching state (normally closed) when there is no control input, in particular if no data bus subscriber is connected to the module unit. In this case, the first switching state is preferred, which allows a passage of the signals on the local bus in the downlink and uplink direction (passively propagate the address signal through a respective connection unit). [0055] FIG. 2 shows an exemplary embodiment of a module unit (connection unit) without a data bus subscriber (bus device) arranged thereon with the switch 23, 24 in the first switching state (normally closed).)
and wherein each of the plurality of connection units that is connected to one of the bus devices ([0013] The module unit (connection unit) according to the invention also has a first data connection interface, which can be connected to the data bus subscriber (bus device)) is further adapted to:
couple the bus line to a first address port of a bus device to which the connection unit is connected through a second address port of the connection unit (Fig. 1; [0050] The data bus subscribers 20a, 20b, 20n (bus devices) that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n (connection units) interconnect via data connection interfaces 13a, 14a, 15a, 16a (comprises first address port) with corresponding data connection interfaces 13b, 14b, 15b, 16b (comprises second address port) on the module units 8a, 8b, . . . , 8n. [0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12 (connections to address assignment line).), and
control, according to a switch control signal transmitted from a first control port of the connected bus device to a second control port of the connection unit an on-off state of a switch of the plurality of switches that is located within the connection unit to control a delivery of the address signal to a downstream connection unit of the plurality of connection units ([0057] As shown in FIG. 2, the module unit 8a has a control input interface 19b for receiving the control input, for example a control signal, from a data bus subscriber 20a and/or for forwarding the control input to the switch 23, 24. In the example shown in FIG. 2, the control input controls all shown switches 23, 24 simultaneously. This means that all switches in the switches 23, 24 switch simultaneously in response to the control input, so that depending on the control input, the switches 23, 24 respectively assume either the defined first switching state (closed) or the defined second switching state (open). [0027] The control signal can, for example, be generated by the data bus subscriber itself and only generated when a specific condition has occurred. For example, both switches may initially be in the first switching state, i.e., provide a forwarding of signals in the downlink and uplink direction. When the data bus subscriber is connected with the module unit, for example, this can immediately provide a control signal, which causes the switch to change to the second switching state so that the signals are no longer routed past the data bus subscriber but instead can be processed by this.), the downstream connection unit being located downstream of the connection unit relative to the gateway (Fig. 1; [0047] Furthermore, in the exemplary embodiment shown here, the module units 8a, 8b, . . . , 8n each have a first output interface 10 in order to transmit data to a downstream or subsequent module unit and/or a data bus subscriber. In the case of module unit 8a, this transmits data via the first output interface 10 to the downstream module unit 8b with the data bus subscriber 20b attached thereto.),
wherein at least a first downstream connection of the plurality of connection units is not connected to any of the plurality of bus devices ([0055] FIG. 2 shows an exemplary embodiment of a module unit without a data bus subscriber arranged thereon with the switch 23, 24 in the first switching state (normally closed). The module unit 8a shown in FIG. 2 is the module unit 8a shown in FIG. 1.), and wherein a first normally closed switch of the plurality of switches is located within the first downstream connection and is configured to remain closed such that the address signal directly passes through the first downstream connection unit to a second downstream connection unit that is connected one of the bus devices ([0055] As has already been described with regard to FIG. 1, in order for the ring bus 6 not to be interrupted, the data must be able to be routed from one subscriber to another. In order to ensure the operability of the ring bus 6, the data in the uplink direction and in the downlink direction needs to be looped through the module units 8a, 8b, . . . , 8n, or forwarded without interruption, even if, for example, no data bus subscriber 20a is mounted on the module unit 8a. For this purpose, the module unit 8a has a first switch 23 for the downlink direction and a second optional switch 24 for the uplink direction. As shown in FIG. 2, the first switch 23 switches the downlink direction and the second switch 24 switches the uplink direction. In this case, the first switch 23 switches the downlink direction such that in the first switching state shown in FIG. 2, the first input interface 9 of the module unit 8a is electrically or optically conductively connected to the first output interface 10. The data starting from the local bus master 3 is accordingly conducted directly in the downlink direction through the module unit 8a to the module unit 8b.).
Jerolm does not teach a gateway configured to generate an address signal that enables address assignment, and the bus line contains an address assignment line.
Schultz in the same field of endeavor of teaches
a gateway configured to generate an address signal that enables address assignment ([0032] The bus system comprises a master unit 1 (gateway), which is connected with the beginning of a bus line 3. In the embodiment shown in the figure, a control line (used as an address line) is also integrated in the bus line 3. [0021] the master unit provides an appropriate switching signal directed at these slave units at the interface, so that the control line is interrupted only in each slave unit to be addressed. [0055] At the beginning of the addressing operation, the master unit sends in step 100 a broadcast message to all slave units connected to the bus, which causes the slave units to switch their relays to the OFF state. This state corresponds to the state shown in FIG. 2, in which the switch 13a is open. [0056] In the next step, step 110, the master unit in this embodiment applies direct voltage between the control line VI and a reference potential GND (generate an address signal that enables address assignment), which is supplied due to the opened switch of the slave unit only to the first slave unit. [0057] After the master unit has set the control signal to the control line (generate an address signal that enables address assignment), the master unit in the embodiment shown here initializes the addressing operation in step 120); and
the bus line contains an address assignment line ([0032] In the embodiment shown in the figure, a control line (address assignment line) is also integrated in the bus line 3.).
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the gateway of Schultz configured to generate an address signal that enables address assignment. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Regarding claim 2, Jerolm teaches the address assignment apparatus of claim 1, wherein each of the plurality of connection units is further adapted to:
in response to the switch control signal being a first control signal, cause a normally closed switch within the connection unit to be in an open state to prevent the address signal from being delivered to the downstream connection unit ([0027] When the data bus subscriber is connected with the module unit, for example, this can immediately provide a control signal, which causes the switch to change to the second switching state (open) so that the signals are no longer routed past the data bus subscriber but instead can be processed by this.); and
in response to the switch control signal being a second control signal different from the first control signal, cause the normally closed switch within the connection unit to be in a closed state, so that the address signal is delivered to the downstream connection unit through the address assignment line ([0030] The first switch and/or the second switch can be adapted to assume the first switching state (closed) when there is no control input, in particular if no data bus subscriber is connected to the module unit. That is, if no data bus subscriber is connected to the module unit, there is no control signal, or there is no geometry that causes a switching state. In this case, the first switching state is preferred, which allows a passage of the signals on the local bus in the downlink and uplink direction.).
Regarding claim 3, Jerolm teaches the address assignment apparatus of claim 2, wherein the second control signal maintains the closed state of the normally closed switch ([0030] The first switch and/or the second switch can be adapted to assume the first switching state (closed) when there is no control input, in particular if no data bus subscriber is connected to the module unit. That is, if no data bus subscriber is connected to the module unit, there is no control signal, or there is no geometry that causes a switching state. In this case, the first switching state is preferred, which allows a passage of the signals on the local bus in the downlink and uplink direction.), and
wherein the first control signal causes the normally closed switch to open to prevent the address signal from being delivered to the downstream connection unit ([0027] When the data bus subscriber is connected with the module unit, for example, this can immediately provide a control signal, which causes the switch to change to the second switching state (open) so that the signals are no longer routed past the data bus subscriber but instead can be processed by this.).
Regarding claim 4, Jerolm teaches the address assignment apparatus of claim 1, further comprising:
a communication data line connected to the gateway ([0044] The local bus master 3 (gateway) in the exemplary embodiment shown here has a further second interface in order to connect the local bus master 3 to the local bus (contains the communication data lines), wherein the local bus in the embodiment shown here is designed as a ring bus 6.)
wherein each of the plurality of connection units is further adapted to couple the communication data line to a bus device to which the connection unit is connected (Fig. 1; [0050] The data bus subscribers 20a, 20b, 20n (bus devices) that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n (connection units) interconnect via data connection interfaces 13a, 14a, 15a, 16a with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n. [0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12 (which are the connections to the communication data lines)),
wherein upon a failure of the bus device to which the connection unit is connected, the normally closed switch remains closed such that an address assigned by the gateway proceeds through the connection unit connected to the failed bus device and is delivered to a subsequent bus device via a downstream connection unit connected to the subsequent bus device, and wherein the address assigned by the gateway is communicated over the communication data line ([0057] As already described above, the ring bus 6 is thereby not interrupted in the absence of a data bus subscriber 20a, or in the absence of a control input of the data bus subscriber 20a. That is, in the event of an error of the data bus subscriber 20a, for example, the first switching state (normally closed) can be assumed because a corresponding control input is missing.).
Jerolm does not teach a communication data line in parallel with the address assignment line.
Schultz in the same field of endeavor of data bus systems teaches
a communication data line connected to the gateway and in parallel with the address assignment line ([0018] In some embodiments, the control line (address assignment line) is designed as an additional conductor, in this case for at least two bus lines connected to the interfaces, so that the control ports form a part of the bus interfaces. [0032] The bus system comprises a master unit 1 (gateway), which is connected with the beginning of a bus line 3 (communication data line). In the embodiment shown in the figure, a control line is also integrated in the bus line 3 (communication data line in parallel with the address assignment line)).
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include an address assignment line in parallel with the communication data line of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Regarding claim 5, Jerolm teaches the address assignment apparatus of claim 4, wherein the gateway is further configured to:
wherein the first address port of the first bus device is configured to receive the address signal via the second address port of the connection unit to which the first bus device is connected (Fig. 1; [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n.[0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12.).
wherein the first bus device includes a first communication port configured to receive the first address via a second communication port of the connection unit to which the first bus device is connected (Fig. 1; [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n.[0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12.).
wherein the second bus device includes a third communication port configured to receive the second address via a fourth communication port of the connection unit to which the second bus device is connected (Fig. 1; [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n.[0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12.)., wherein the gateway includes a fifth communication port configured to transmit the first and second addresses to the first and second bus devices through the communication data line (Fig. 1; [0044] The first part 5a (first transmission port of the gateway) of the second interface establishes the downlink in the ring bus 6.
Jerolm does not teach transmit, through the address assignment line, the address signal from a third address port of the gateway to at least a first bus device among the plurality of bus devices; in a case that the address signal is valid, transmit a first address to be assigned to the first bus device through the communication data line; and in response to determining that the first address has been assigned, transmit a second address to be assigned through the communication data line to a second bus device among the plurality of bus devices.
Schultz teaches
transmit, through the address assignment line, the address signal from a third address port of the gateway to at least a first bus device among the plurality of bus devices ([0056] In the next step, step 110, the master unit (gateway) in this embodiment applies direct voltage between the control line VI and a reference potential GND, which is supplied due to the opened switch of the slave unit only to the first slave unit. [0057] After the master unit (gateway) has set the control signal to the control line, the master unit in the embodiment shown here initializes the addressing operation in step 120, in which the variable n, which indicates the current slave unit to be addressed, and variable i, which is used in this embodiment to determine whether the last slave unit was addressed, is in each case set to one. After that, the master unit sends in step 130 a broadcast signal through the bus line which assigns the address 1 in an undetermined manner to all slaves. However, since only the first slave unit has been released for addressing, only this slave unit will accept the address 1, see FIG. 5.).
in a case that the address signal is valid, transmit a first address to be assigned to the first bus device through the communication data line (Fig. 4, [0056] In the next step, step 110, the master unit in this embodiment applies direct voltage between the control line VI and a reference potential GND, which is supplied due to the opened switch of the slave unit only to the first slave unit. Due to the enable switch 10, this first slave unit is with this applied control signal set to the OFF position of the relay in a state in which it is released for addressing. [0057] After that, the master unit sends in step 130 a broadcast signal through the bus line which assigns the address 1 in an undetermined manner to all slaves. However, since only the first slave unit has been released for addressing, only this slave unit will accept the address 1); and
in response to determining that the first address has been assigned, transmit a second address to be assigned through the communication data line to a second bus device among the plurality of bus devices (Fig. 4, [0059] If the master unit received from the addressed slave unit the response through the bus line (see step 160) that the addressing was successful, it will send through the bus line to the just addressed unit having the address 1 the instruction to set its relay to the ON status, in which the switch 13a is closed and the control signal thus can be passed on to the next slave unit. [0060] After that, the master unit repeats the operation for each of the next slave units, incrementing the address by 1, as shown in Fig. 4 step 180.).
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Regarding claim 6, Jerolm teaches the address assignment apparatus of claim 4, wherein the communication data line comprises:
a transmission data line adapted to transmit first data from a first transmission port of the gateway to at least a second transmission port of a first bus device among the plurality of bus devices, the second transmission port being configured to receive the first data via a third transmission port of the connection unit to which the first bus device is connected, wherein the third transmission port is disposed between the first and second transmission ports and is configured to directly connect to the transmission data line (Fig. 1; [0044] The first part 5a (first transmission port of the gateway) of the second interface establishes the downlink in the ring bus 6 and the second part 5b of the second interface establishes the uplink in the ring bus 6. [0047] In the exemplary embodiment shown here, the module units 8a, 8b, . . . , 8n each have a first input interface 9 (third transmission port of the connection unit) for receiving data from a subscriber upstream of or preceding the ring bus 6, for example from an upstream module unit, a data bus subscriber or a local bus master 3. The receiving may be active or passive, i.e., signal processing can take place or not. In the case of the module unit 8a shown, this receives data from the upstream local bus master 3 via the first input interface 9. Furthermore, in the exemplary embodiment shown here, the module units 8a, 8b, . . . , 8n each have a first output interface 10 in order to transmit data to a downstream or subsequent module unit and/or a data bus subscriber. In the case of module unit 8a, this transmits data via the first output interface 10 to the downstream module unit 8b with the data bus subscriber 20b attached thereto. The transmission can be active or passive, i.e., signal processing may or may not take place. The first input interface 9 and the first output interface 10 serve to propagate data in the downlink direction of the ring bus 6, i.e., away from the local bus master 3. [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a (comprises second transmission port of a bus device) with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n. [0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12.); and
a reception data line adapted to transmit second data from at least a first reception port of the first bus device to a second reception port of the gateway via a third reception port of the connection unit to which the first bus device is connected, wherein the third reception port is disposed between the first and second reception ports and is configured to directly connect to the reception data line ((Fig. 1; [0044] The first part 5a of the second interface establishes the downlink in the ring bus 6 and the second part 5b (second reception port of the gateway) of the second interface establishes the uplink in the ring bus 6. [0047] Furthermore, the module units 8a, 8b, . . . , 8n also have a second input interface 11 and a second output interface 12 (third reception port of the connection unit) which serve to propagate data in the uplink direction of the ring bus 6, i.e., towards the local bus master 3. In the case of the module unit 8a, the second input interface 11 is designed to receive data from the downstream or subsequent module unit 8b with or without data bus subscriber 20b arranged thereon and the second output interface 12 is designed to forward data to the upstream or the preceding module unit and/or data bus subscriber, here the local bus master 3. [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a (comprises first reception port of the bus device) with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n. [0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12.);.
Regarding claim 12, Jerolm teaches an address assignment method comprising:
wherein each of the plurality of bus devices is configured to connect to a connection unit among a plurality of connection units that are structurally separate devices than the plurality of bus devices (Fig. 1 shows module units (8a, 8b, 8n) (connection units) and structurally separate data bus subscribers (20a, 20b, ..., 20n) (bus devices). [0045] The ring bus 6, whose data transmission direction is shown with arrows in the exemplary embodiment shown in FIG. 1, has a plurality of module units 8a, 8b, . . . , 8n for connection to data bus subscribers 20a, 20b, . . . , 20n in the exemplary embodiment shown here. [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n.)
the switch control signal is provided from a first control port of the bus device to a second control port of the connection unit ([0057] As shown in FIG. 2, the module unit 8a (connection unit) has a control input interface 19b for receiving the control input, for example a control signal, from a data bus subscriber 20a (bus device) and/or for forwarding the control input to the switch 23, 24. [0061] For this purpose, the data bus subscriber 20b may have interfaces which correspond to the interfaces 13b to 19b of the module unit 8b and which can be connected to the interfaces 13b to 19b.)
the address assignment line is coupled to a first address port of the gateway, wherein the bus device includes a second address port configured to receive the address signal from the gateway through a third address port of the connection unit to which the bus device is connected (Fig. 1; [0044] The first part 5a (first address port of the gateway) of the second interface establishes the downlink in the ring bus 6 and the second part 5b of the second interface establishes the uplink in the ring bus 6. [0047] In the exemplary embodiment shown here, the module units 8a, 8b, . . . , 8n each have a first input interface 9 (third address port of the connection unit) for receiving data from a subscriber upstream of or preceding the ring bus 6, for example from an upstream module unit, a data bus subscriber or a local bus master 3. The receiving may be active or passive, i.e., signal processing can take place or not. In the case of the module unit 8a shown, this receives data from the upstream local bus master 3 via the first input interface 9. Furthermore, in the exemplary embodiment shown here, the module units 8a, 8b, . . . , 8n each have a first output interface 10 in order to transmit data to a downstream or subsequent module unit and/or a data bus subscriber. In the case of module unit 8a, this transmits data via the first output interface 10 to the downstream module unit 8b with the data bus subscriber 20b attached thereto. The transmission can be active or passive, i.e., signal processing may or may not take place. The first input interface 9 and the first output interface 10 serve to propagate data in the downlink direction of the ring bus 6, i.e., away from the local bus master 3. [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a (comprises second address port of a bus device) with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n. [0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12.);
wherein the downstream connection unit is disposed in series with the connected connection unit along the address assignment line, and is located downstream of the connected connection unit relative to the gateway (Fig. 1; [0016] Subsequently, the data bus subscriber can output the processed data on the first data connection interface, which is connected to the first output interface, so that the processed data can be forwarded to the next module unit (connection unit) or the next data bus subscriber. [0024] The module unit can have at least one connecting element in order to be connected with another module unit, wherein the first output interface of the module unit is electrically connected to a first input interface of the further module unit, or the first input interface of the module unit is electrically connected to a first output interface of the other module unit.)
wherein at least a first downstream connection of the plurality of connection units is not connected to any of the plurality of bus devices ([0055] FIG. 2 shows an exemplary embodiment of a module unit without a data bus subscriber arranged thereon with the switch 23, 24 in the first switching state (normally closed). The module unit 8a shown in FIG. 2 is the module unit 8a shown in FIG. 1.),
wherein each of the plurality of switches is a normally closed switch configured to passively propagate the address signal through the connection unit in which that normally closed switch is located ([0027] For example, both switches may initially be in the first switching state, i.e., provide a forwarding of signals in the downlink and uplink direction. [0030] The first switch and/or the second switch can be adapted to assume the first switching state (closed) when there is no control input, in particular if no data bus subscriber is connected to the module unit. In this case, the first switching state is preferred, which allows a passage of the signals on the local bus in the downlink and uplink direction (passively propagate the address signal through a respective connection unit). [0055] FIG. 2 shows an exemplary embodiment of a module unit (connection unit) without a data bus subscriber (bus device) arranged thereon with the switch 23, 24 in the first switching state (normally closed).), and
wherein a first normally closed switch of the plurality of switches is located within the first downstream connection and is configured to remain closed such that the address signal directly passes through the first downstream connection unit to a second downstream connection unit that is connected one of the bus devices ([0055] As has already been described with regard to FIG. 1, in order for the ring bus 6 not to be interrupted, the data must be able to be routed from one subscriber to another. In order to ensure the operability of the ring bus 6, the data in the uplink direction and in the downlink direction needs to be looped through the module units 8a, 8b, . . . , 8n, or forwarded without interruption, even if, for example, no data bus subscriber 20a is mounted on the module unit 8a. For this purpose, the module unit 8a has a first switch 23 for the downlink direction and a second optional switch 24 for the uplink direction. As shown in FIG. 2, the first switch 23 switches the downlink direction and the second switch 24 switches the uplink direction. In this case, the first switch 23 switches the downlink direction such that in the first switching state shown in FIG. 2, the first input interface 9 of the module unit 8a is electrically or optically conductively connected to the first output interface 10. The data starting from the local bus master 3 is accordingly conducted directly in the downlink direction through the module unit 8a to the module unit 8b.).
Jerolm does not teach
acquiring an address assignment state indicating whether a bus device among a plurality of bus devices, has been assigned an address by a gateway ([0058] The master unit (gateway) starts a status query in step 150 through the bus line to the just addressed slave which has the address 1. The master unit ensures with this status query that the addressing was successful (an address state of already addressed). In addition, it uses the status query here to determine whether other slave units are still to be addressed (an address state of needing an address).); and
setting a switch control signal provided to a connection unit to which the bus device is connected based on the address assignment state ([0059] If the master unit received from the addressed slave unit the response through the bus line (see step 160) that the addressing was successful, it will send through the bus line to the just addressed unit having the address 1 the instruction to set its relay to the ON status, in which the switch 13a is closed and the control signal thus can be passed on to the next slave unit. Fig. 2, [0042] The microcomputer (in the slave unit) is equipped in the embodiment shown here also with an output 15 which is used to control the relay 13 that is set depending on the signal (switch control signal) applied through the interface (connection unit)), the switch control signal being used for controlling an on-off state of a switch (switch 13 of Fig. 2) among a plurality of switches located within the plurality of connection units, wherein the switch is within the connected connection unit ([0037] The enable circuit 10 comprises in the embodiment shown here a relay 13, which is connected through a switch 13a with the control ports 12) and is set to control a delivery of an address signal generated by the gateway to a downstream connection unit of the plurality of connection units along an address assignment line ([0059] If the master unit (gateway) received from the addressed slave unit the response through the bus line (see step 160) that the addressing was successful, it will send through the bus line to the just addressed unit having the address 1 the instruction to set its relay to the ON status, in which the switch 13a is closed and the control signal (address signal) thus can be passed on to the next slave unit (a downstream connection unit integrated with the downstream slave unit)), wherein the downstream connection unit is disposed in series with the connected connection unit along the address assignment line, and is located downstream of the connected connection unit relative to the gateway (Fig. 1 shows the second or third slave units 2 disposed in series along the bus (address assignment line) located downstream relative to the master unit 1 (gateway). The connection units are integrated with the slave units as shown in Fig. 2, thus the connection units are also disposed in series and located downstream of each other).
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Regarding claim 13, Jerolm in view of Schultz teaches the method of claim 12, and Shultz teaches wherein setting the switch control signal comprises:
in response to the bus device not being assigned an address by the gateway, set the switch control signal to be a first control signal, so that a switch within the connected connection unit is in an open state ([0021] Prior to applying the signal, the master unit preferably forces al the slave units to be addressed to open their switch, for example with a corresponding broadcast signal. As an alternative--for example during a procedure to redirect addressing of certain slave units--the master unit provides an appropriate switching signal directed at these slave units at the interface, so that the control line is interrupted only in each slave unit to be addressed. [0055] At the beginning of the addressing operation, the master unit sends in step 100 a broadcast message to all slave units connected to the bus, which causes the slave units (bus devices) to switch their relays to the OFF state. Fig. 2, [0042] The microcomputer (in the bus device) is equipped in the embodiment shown here also with an output 15 (switch control signal) which is used to control the relay 13 that is set depending on the signal applied through the interface. For example, in the embodiment shown here, the output 15 determines the position of the switches 13a and 13b.); and
in response to the bus device being assigned an address by the gateway, set the switch control signal to be a second control signal different from the first control signal, so that the switch within the connected connection unit is in a closed state ([0059] If the master unit received from the addressed slave unit the response through the bus line (see step 160) that the addressing was successful, it will send through the bus line to the just addressed unit having the address 1 the instruction to set its relay to the ON status. [0068] Upon the receipt at the bus interface of a corresponding signal which is directed to the slave unit, the slave unit reverses the switch, which results in the enabled status and leads to a transition into the locked state indicated in FIG. 5 as addressing OFF (address assignment state) (steps 320 and 330). The slave unit (bus device) is not addressable in this state. [Fig. 2, [0042] The microcomputer (of the slave unit) is equipped in the embodiment shown here also with an output 15 (switch control signal) which is used to control the relay 13 that is set depending on the signal applied through the interface.).
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Regarding claim 15, Jerolm in view of Schultz teaches the method of claim 12, and Schultz teaches further comprising performing,
in response to the second address port receiving the address signal over the address assignment line via the third address port of a connection unit to which the bus device is connected, address assignment for the bus device according to a communication with the gateway ([0056] In the next step, step 110, the master unit in this embodiment applies direct voltage between the control line VI and a reference potential GND, which is supplied due to the opened switch of the slave unit only to the first slave unit. Fig. 2 shows the control signal is applied to the control ports 12, which are part of the bus interfaces 11 (connection unit). [0057] After that, the master unit sends in step 130 a broadcast signal through the bus line which assigns the address 1 in an undetermined manner to all slaves. However, since only the first slave unit has been released for addressing, only this slave unit will accept the address 1, see FIG. 5. [0041] The presence of the control signal results in the enable state of the enable input or of the microcomputer. As a result of this, the microcontroller allows the assignment of one address to the slave unit 2 if a corresponding signal is provided at the addressing line of the bus interface.)
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Regarding claim 16, Jerolm teaches wherein performing address assignment for the bus device according to a communication with the gateway comprises:
wherein the address is received at the first transmission port via a third transmission port of the connected connection unit (Fig. 1; [0044] The first part 5a (first transmission port of the gateway) of the second interface establishes the downlink in the ring bus 6 and the second part 5b of the second interface establishes the uplink in the ring bus 6. [0047] In the exemplary embodiment shown here, the module units 8a, 8b, . . . , 8n each have a first input interface 9 (third transmission port of the connection unit) for receiving data from a subscriber upstream of or preceding the ring bus 6, for example from an upstream module unit, a data bus subscriber or a local bus master 3. The receiving may be active or passive, i.e., signal processing can take place or not. In the case of the module unit 8a shown, this receives data from the upstream local bus master 3 via the first input interface 9. Furthermore, in the exemplary embodiment shown here, the module units 8a, 8b, . . . , 8n each have a first output interface 10 in order to transmit data to a downstream or subsequent module unit and/or a data bus subscriber. In the case of module unit 8a, this transmits data via the first output interface 10 to the downstream module unit 8b with the data bus subscriber 20b attached thereto. The transmission can be active or passive, i.e., signal processing may or may not take place. The first input interface 9 and the first output interface 10 serve to propagate data in the downlink direction of the ring bus 6, i.e., away from the local bus master 3. [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a (comprises second transmission port of a bus device) with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n. [0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12.);
wherein the positive response is transmitted to a second reception port of the gateway via a third reception port of the connected connection unit ((Fig. 1; [0044] The first part 5a of the second interface establishes the downlink in the ring bus 6 and the second part 5b (second reception port of the gateway) of the second interface establishes the uplink in the ring bus 6. [0047] Furthermore, the module units 8a, 8b, . . . , 8n also have a second input interface 11 and a second output interface 12 (third reception port of the connection unit) which serve to propagate data in the uplink direction of the ring bus 6, i.e., towards the local bus master 3. In the case of the module unit 8a, the second input interface 11 is designed to receive data from the downstream or subsequent module unit 8b with or without data bus subscriber 20b arranged thereon and the second output interface 12 is designed to forward data to the upstream or the preceding module unit and/or data bus subscriber, here the local bus master 3. [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a (comprises first reception port of the bus device) with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n. [0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12.).
Jerolm does not teach receiving, at a first transmission port of the bus device, an address to be assigned from a second transmission port of the gateway; in response to receiving the address signal, set the bus device to have the address; and transmitting, through a first reception port of the bus device, a positive response that the address has been assigned.
Schultz teaches
receiving, at a first transmission port of the bus device, an address to be assigned from a second transmission port of the gateway ([0057] After that, the master unit (gateway) sends in step 130 a broadcast signal through the bus line which assigns the address 1 in an undetermined manner to all slaves. However, since only the first slave unit (bus device) has been released for addressing, only this slave unit (bus device) will accept the address 1, see FIG. 5. Fig. 2, [0035] The bus interfaces 11 comprises in the embodiment shown here among other items address lines D- and D+ which can be used to supply addressing signal.);
in response to receiving the address signal, set the bus device to have the address ([0041] As explained above, the control signal is then applied in the embodiment shown here to the enable input 14 when the release conditions "control line interrupted by open switch 13a" and "control signal applied at one of the control ports" are present. The presence of the control signal results in the enable state of the enable input or of the microcomputer. As a result of this, the microcontroller allows the assignment of one address to the slave unit 2 if a corresponding signal is provided at the addressing line of the bus interface.); and
transmitting, through a first reception port of the bus device, a positive response that the address has been assigned ([0059] If the master unit (gateway) received from the addressed slave unit (bus device) the response through the bus line (through the bus interface or the connection unit) (see step 160) that the addressing was successful, it will send through the bus line to the just addressed unit having the address 1 the instruction to set its relay to the ON status, in which the switch 13a is closed and the control signal thus can be passed on to the next slave unit. [0067] If for example a status query whether the addressing was successful is directed to the slave unit, it answers accordingly (steps 340 and 350).).
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Claim Rejections - 35 USC § 103
Claim(s) 7, 8, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Jerolm (US 20200092132 A1) and Schultz (US 20120221755 A1) further in view of Hansing (US 20200320027 A1).
Regarding claim 7, Jerolm in view of Schultz teaches the address assignment apparatus according to claim 1; and Schultz teaches one or more bus device, each of the one or more bus device being connected to one of the plurality of connection units and configured to set the switch control signal provided to a connection unit to which the bus device is connected based on an address assignment state of the bus device ([0068] Upon the receipt at the bus interface of a corresponding signal which is directed to the slave unit, the slave unit reverses the switch, which results in the enabled status and leads to a transition into the locked state indicated in FIG. 5 as addressing OFF (address assignment state) (steps 320 and 330). The slave unit (bus device) is not addressable in this state. [Fig. 2, [0042] The microcomputer (of the slave unit) is equipped in the embodiment shown here also with an output 15 (switch control signal) which is used to control the relay 13 that is set depending on the signal applied through the interface.)
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Schultz does not teach a power distribution cabinet that comprises the address assignment apparatus according to claim1.
Hansing in the same field of endeavor of bus arrangements teaches a power distribution cabinet that comprises the address assignment apparatus according to claim1 ([0064] In one embodiment, the first subscriber arrangement is embodied as a drawer or sliding box. The bus arrangement is constructed in a cabinet, such as a control cabinet (power distribution cabinet). The first subscriber arrangement can be pulled out and reinserted into the cabinet like a drawer or sliding box.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the cabinet of Hansing with the addressing method of bus systems of Jerolm and Schultz. The motivation to do so would have been to advantageously improve the automatic addressing of subscribers in a bus system by the bus arrangement and method (Hansing; [0069]).
Regarding claim 8, Jerolm in view of Schultz and Hansing teach the power distribution cabinet of claim 7, Schultz further teaches wherein each of the one or more bus device is further configured to:
in response to the bus device not being assigned an address by the gateway, set the switch control signal to be a first control signal, so that a switch within the connected connection unit is in an open state ([0021] Prior to applying the signal, the master unit preferably forces al the slave units to be addressed to open their switch, for example with a corresponding broadcast signal. As an alternative--for example during a procedure to redirect addressing of certain slave units--the master unit provides an appropriate switching signal directed at these slave units at the interface, so that the control line is interrupted only in each slave unit to be addressed. [0055] At the beginning of the addressing operation, the master unit sends in step 100 a broadcast message to all slave units connected to the bus, which causes the slave units (bus devices) to switch their relays to the OFF state. Fig. 2, [0042] The microcomputer (in the bus device) is equipped in the embodiment shown here also with an output 15 (switch control signal) which is used to control the relay 13 that is set depending on the signal applied through the interface. For example, in the embodiment shown here, the output 15 determines the position of the switches 13a and 13b.); and
in response to the bus device being assigned an address by the gateway, set the switch control signal to be a second control signal different from the first control signal, so that the switch within the connected connection unit is in a closed state ([0059] If the master unit received from the addressed slave unit the response through the bus line (see step 160) that the addressing was successful, it will send through the bus line to the just addressed unit having the address 1 the instruction to set its relay to the ON status. [0068] Upon the receipt at the bus interface of a corresponding signal which is directed to the slave unit, the slave unit reverses the switch, which results in the enabled status and leads to a transition into the locked state indicated in FIG. 5 as addressing OFF (address assignment state) (steps 320 and 330). The slave unit (bus device) is not addressable in this state. [Fig. 2, [0042] The microcomputer (of the slave unit) is equipped in the embodiment shown here also with an output 15 (switch control signal) which is used to control the relay 13 that is set depending on the signal applied through the interface.).
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Regarding claim 10, Jerolm in view of Schultz and Hansing teach the power distribution cabinet of claim 7, and Schultz teaches wherein each of the one or more bus device is further configured to perform, in response to receiving the address signal via a connection unit to which the bus device is connected, address assignment for the bus device according to a communication with the gateway ([0056] In the next step, step 110, the master unit in this embodiment applies direct voltage between the control line VI and a reference potential GND, which is supplied due to the opened switch of the slave unit only to the first slave unit. Fig. 2 shows the control signal is applied to the control ports 12, which are part of the bus interfaces 11 (connection unit). [0057] After that, the master unit sends in step 130 a broadcast signal through the bus line which assigns the address 1 in an undetermined manner to all slaves. However, since only the first slave unit has been released for addressing, only this slave unit will accept the address 1, see FIG. 5. [0041] The presence of the control signal results in the enable state of the enable input or of the microcomputer. As a result of this, the microcontroller allows the assignment of one address to the slave unit 2 if a corresponding signal is provided at the addressing line of the bus interface.)
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Regarding claim 11, Jerolm teaches wherein each of the one or more bus device is further configured to:
wherein the gateway includes a third transmission port configured to transmit the address over a transmission data line coupled to the first transmission port via the second transmission port (Fig. 1; [0044] The first part 5a (first transmission port of the gateway) of the second interface establishes the downlink in the ring bus 6 and the second part 5b of the second interface establishes the uplink in the ring bus 6. [0047] In the exemplary embodiment shown here, the module units 8a, 8b, . . . , 8n each have a first input interface 9 (third transmission port of the connection unit) for receiving data from a subscriber upstream of or preceding the ring bus 6, for example from an upstream module unit, a data bus subscriber or a local bus master 3. The receiving may be active or passive, i.e., signal processing can take place or not. In the case of the module unit 8a shown, this receives data from the upstream local bus master 3 via the first input interface 9. Furthermore, in the exemplary embodiment shown here, the module units 8a, 8b, . . . , 8n each have a first output interface 10 in order to transmit data to a downstream or subsequent module unit and/or a data bus subscriber. In the case of module unit 8a, this transmits data via the first output interface 10 to the downstream module unit 8b with the data bus subscriber 20b attached thereto. The transmission can be active or passive, i.e., signal processing may or may not take place. The first input interface 9 and the first output interface 10 serve to propagate data in the downlink direction of the ring bus 6, i.e., away from the local bus master 3. [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a (comprises second transmission port of a bus device) with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n. [0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12.);
wherein the gateway includes a third reception port configured to receive the positive response over a reception data line coupled to the first reception port via the second reception port ((Fig. 1; [0044] The first part 5a of the second interface establishes the downlink in the ring bus 6 and the second part 5b (second reception port of the gateway) of the second interface establishes the uplink in the ring bus 6. [0047] Furthermore, the module units 8a, 8b, . . . , 8n also have a second input interface 11 and a second output interface 12 (third reception port of the connection unit) which serve to propagate data in the uplink direction of the ring bus 6, i.e., towards the local bus master 3. In the case of the module unit 8a, the second input interface 11 is designed to receive data from the downstream or subsequent module unit 8b with or without data bus subscriber 20b arranged thereon and the second output interface 12 is designed to forward data to the upstream or the preceding module unit and/or data bus subscriber, here the local bus master 3. [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a (comprises first reception port of the bus device) with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n. [0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12.).
Jerolm does not teach receive, at a first transmission port of the bus device, an address to be assigned from the gateway via a second transmission port of the connected connection unit, in response to the first address port receiving the address signal over the address assignment line via the second address port, set the bus device to have the address; and transmit, from a first reception port of the bus device, a positive response that the address has been assigned to the gateway via a second reception port of the connected connection unit.
Schultz teaches
receive, at a first transmission port of the bus device, an address to be assigned from the gateway via a second transmission port of the connected connection unit ([0057] After that, the master unit (gateway) sends in step 130 a broadcast signal through the bus line which assigns the address 1 in an undetermined manner to all slaves. However, since only the first slave unit (bus device) has been released for addressing, only this slave unit (bus device) will accept the address 1, see FIG. 5. Fig. 2, [0035] The bus interfaces 11 (connection unit) comprises in the embodiment shown here among other items address lines D- and D+ which can be used to supply addressing signal.);
in response to the first address port receiving the address signal, over the address assignment line via the second address port, set the bus device to have the address ([0041] As explained above, the control signal is then applied in the embodiment shown here to the enable input 14 when the release conditions "control line interrupted by open switch 13a" and "control signal applied at one of the control ports" are present. The presence of the control signal results in the enable state of the enable input or of the microcomputer. As a result of this, the microcontroller allows the assignment of one address to the slave unit 2 if a corresponding signal is provided at the addressing line of the bus interface.); and
transmit, from a first reception port of the bus device, a positive response that the address has been assigned to the gateway via a second reception port of the connected connection unit ([0059] If the master unit (gateway) received from the addressed slave unit (bus device) the response through the bus line (through the bus interface or the connection unit) (see step 160) that the addressing was successful, it will send through the bus line to the just addressed unit having the address 1 the instruction to set its relay to the ON status, in which the switch 13a is closed and the control signal thus can be passed on to the next slave unit. [0067] If for example a status query whether the addressing was successful is directed to the slave unit, it answers accordingly (steps 340 and 350).).
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Claim Rejections - 35 USC § 103
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jerolm (US 20200092132 A1) and Schultz (US 20120221755 A1) further in view of Hansing (US 20200320027 A1); further in view of Buenaventura (US 20210049121 A1).
Regarding claim 9, Schultz teaches the power distribution cabinet of claim 8, wherein each of the one or more bus device is further configured to:
set the switch control signal to be the first control signal (open switch) when a slave unit needs to be assigned an address ([0021] Prior to applying the signal, the master unit preferably forces all the slave units to be addressed to open their switch, for example with a corresponding broadcast signal. [0055] At the beginning of the addressing operation, the master unit sends in step 100 a broadcast message to all slave units connected to the bus, which causes the slave units (bus devices) to switch their relays to the OFF state (switch is open). The switch is opened by the slave unit providing a switch control signal to be the first control signal. Fig. 2, [0042] The microcomputer (in the bus device) is equipped … with an output 15 (switch control signal) which is used to control the relay 13.)
Schultz does not teach in response to the bus device having a preset address, assign an address.
Buenaventura in the same field of endeavor of addressing slave devices teaches wherein each of the at least one bus device is further configured to: in response to the bus device having a preset address, assign an address. ([0059] By default, and initially, all the slave devices have a common default address, such as 0*FE for example (preset address). [0077] at startup-up, all the slave devices are deactivated by the master device and that the activations are performed iteratively. Fig. 3 shows the iterative process of addressing each slave device. The method comprising, [0016] sending, to the common default address on the communication line, a command to change the common default address of the slave device of index k to a unique address of index k.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the slave units with default addresses of Buenaventura with the addressing method of master-slave bus systems of Jerolm in view of Schultz and Hansing. The motivation to do so would have been to improve the efficiency of the addressing method by measuring a value of a current consumption on the power line before sending the command to change the common default address of the slave device of index k. This ensures to perform the addressing step only if a new slave device is detected. (Buenaventura; [0020] – [0021]).
Claim Rejections - 35 USC § 103
Claim(s) 14, 17, 18, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jerolm (US 20200092132 A1) and Schultz (US 20120221755 A1) further in view of Buenaventura (US 20210049121 A1).
Regarding claim 14, Jerolm in view of Schultz teaches the method of claim 13, and Schultz teaches wherein setting the switch control signal provided to a connection unit to which the bus device is connected comprises setting, the switch control signal to be the first control signal (open switch) when a slave unit needs to be assigned an address ([0021] Prior to applying the signal, the master unit preferably forces all the slave units to be addressed to open their switch, for example with a corresponding broadcast signal. [0055] At the beginning of the addressing operation, the master unit sends in step 100 a broadcast message to all slave units connected to the bus, which causes the slave units (bus devices) to switch their relays to the OFF state (switch is open). The switch is opened by the slave unit providing a switch control signal to be the first control signal. Fig. 2, [0042] The microcomputer (in the bus device) is equipped … with an output 15 (switch control signal) which is used to control the relay 13.)
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Schultz does not teach in response to the bus device having a preset address, assign an address.
Buenaventura in the same field of endeavor of addressing slave devices teaches wherein each of the at least one bus device is further configured to: in response to the bus device having a preset address, assign an address. ([0059] By default, and initially, all the slave devices have a common default address, such as 0*FE for example (preset address). [0077] at startup-up, all the slave devices are deactivated by the master device and that the activations are performed iteratively. Fig. 3 shows the iterative process of addressing each slave device. The method comprising, [0016] sending, to the common default address on the communication line, a command to change the common default address of the slave device of index k to a unique address of index k.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the slave units with default addresses of Buenaventura with the addressing method of master-slave bus systems of Jerolm in view of Schultz. The motivation to do so would have been to improve the efficiency of the addressing method by measuring a value of a current consumption on the power line before sending the command to change the common default address of the slave device of index k. This ensures to perform the addressing step only if a new slave device is detected. (Buenaventura; [0020] – [0021]).
Regarding claim 17, Jerolm teaches
wherein each of the plurality of bus devices is configured to connect to a connection unit among a plurality of connection units that are structurally separate devices than the plurality of bus devices (Fig. 1 shows module units (8a, 8b, 8n) (connection units) and structurally separate data bus subscribers (20a, 20b, ..., 20n) (bus devices). [0045] The ring bus 6, whose data transmission direction is shown with arrows in the exemplary embodiment shown in FIG. 1, has a plurality of module units 8a, 8b, . . . , 8n for connection to data bus subscribers 20a, 20b, . . . , 20n in the exemplary embodiment shown here. [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n.)
the switch control signal is provided from a first control port of the bus device to a second control port of the connection unit ([0057] As shown in FIG. 2, the module unit 8a has a control input interface 19b for receiving the control input, for example a control signal, from a data bus subscriber 20a and/or for forwarding the control input to the switch 23, 24. In the example shown in FIG. 2, the control input controls all shown switches 23, 24 simultaneously. This means that all switches in the switches 23, 24 switch simultaneously in response to the control input, so that depending on the control input, the switches 23, 24 respectively assume either the defined first switching state or the defined second switching state.)
wherein the bus device includes a second address port configured to receive the address signal from the gateway through a third address port of the connection unit to which the bus device is connected (Fig. 1; [0044] The first part 5a (first transmission port of the gateway) of the second interface establishes the downlink in the ring bus 6 and the second part 5b of the second interface establishes the uplink in the ring bus 6. [0047] In the exemplary embodiment shown here, the module units 8a, 8b, . . . , 8n each have a first input interface 9 (third transmission port of the connection unit) for receiving data from a subscriber upstream of or preceding the ring bus 6, for example from an upstream module unit, a data bus subscriber or a local bus master 3. The receiving may be active or passive, i.e., signal processing can take place or not. In the case of the module unit 8a shown, this receives data from the upstream local bus master 3 via the first input interface 9. Furthermore, in the exemplary embodiment shown here, the module units 8a, 8b, . . . , 8n each have a first output interface 10 in order to transmit data to a downstream or subsequent module unit and/or a data bus subscriber. In the case of module unit 8a, this transmits data via the first output interface 10 to the downstream module unit 8b with the data bus subscriber 20b attached thereto. The transmission can be active or passive, i.e., signal processing may or may not take place. The first input interface 9 and the first output interface 10 serve to propagate data in the downlink direction of the ring bus 6, i.e., away from the local bus master 3. [0050] The data bus subscribers 20a, 20b, 20n that can be attached to or plugged onto the module units 8a, 8b, . . . , 8n interconnect via data connection interfaces 13a, 14a, 15a, 16a (comprises second transmission port of a bus device) with corresponding data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n. [0051] The data connection interfaces 13b, 14b, 15b, 16b on the module units 8a, 8b, . . . , 8n are in turn connected to the first and second input and output interfaces 9, 10, 11, 12.)
wherein the downstream connection unit is disposed in series with the connected connection unit along the address assignment line, and is located downstream of the connected connection unit relative to the gateway (Fig. 1 shows the module units (connection units) connected along the bus, each downstream from the other. [0010] In a ring bus, the data bus subscribers…are each connected to the data bus subscriber directly adjacent to them and data is forwarded in order from one to the other data bus subscriber (connected in series). Thus, the data is not sent to all data bus subscribers at the same time, but in turn, wherein a data bus subscriber receives data from its upstream data bus subscriber and forwards data to its downstream data bus subscriber. Between receiving the data and forwarding, the data bus subscriber can process the received data. Each data bus subscriber is connected to a module unit (connection unit), thus the connection units are disposed in series along the address assignment line.)
wherein at least a first downstream connection of the plurality of connection units is not connected to any of the plurality of bus devices ([0055] FIG. 2 shows an exemplary embodiment of a module unit without a data bus subscriber arranged thereon with the switch 23, 24 in the first switching state (normally closed). The module unit 8a shown in FIG. 2 is the module unit 8a shown in FIG. 1.),
wherein each of the plurality of switches is a normally closed switch configured to passively propagate the address signal through the connection unit in which that normally closed switch is located ([0027] For example, both switches may initially be in the first switching state, i.e., provide a forwarding of signals in the downlink and uplink direction. [0030] The first switch and/or the second switch can be adapted to assume the first switching state (closed) when there is no control input, in particular if no data bus subscriber is connected to the module unit. In this case, the first switching state is preferred, which allows a passage of the signals on the local bus in the downlink and uplink direction (passively propagate the address signal through a respective connection unit). [0055] FIG. 2 shows an exemplary embodiment of a module unit (connection unit) without a data bus subscriber (bus device) arranged thereon with the switch 23, 24 in the first switching state (normally closed).), and
wherein a first normally closed switch of the plurality of switches is located within the first downstream connection and is configured to remain closed such that the address signal directly passes through the first downstream connection unit to a second downstream connection unit that is connected one of the bus devices ([0055] As has already been described with regard to FIG. 1, in order for the ring bus 6 not to be interrupted, the data must be able to be routed from one subscriber to another. In order to ensure the operability of the ring bus 6, the data in the uplink direction and in the downlink direction needs to be looped through the module units 8a, 8b, . . . , 8n, or forwarded without interruption, even if, for example, no data bus subscriber 20a is mounted on the module unit 8a. For this purpose, the module unit 8a has a first switch 23 for the downlink direction and a second optional switch 24 for the uplink direction. As shown in FIG. 2, the first switch 23 switches the downlink direction and the second switch 24 switches the uplink direction. In this case, the first switch 23 switches the downlink direction such that in the first switching state shown in FIG. 2, the first input interface 9 of the module unit 8a is electrically or optically conductively connected to the first output interface 10. The data starting from the local bus master 3 is accordingly conducted directly in the downlink direction through the module unit 8a to the module unit 8b.).
Jerolm does not teach acquire an address assignment state indicating whether a bus device, among a plurality of bus devices, has been assigned an address by a gateway; set a switch control signal provided to a connection unit to which the bus device is connected based on the address assignment state, the switch control signal being used for controlling an on- off state of a switch among a plurality of switches located within the plurality of connection units, wherein the switch is within the connected connection unit and is set to control a delivery of an address signal generated by the gateway to a downstream connection unit of the plurality of connection units along an address assignment line coupled to a first address port of the gateway
Schultz in the same field of endeavor of bus systems teaches
acquire an address assignment state indicating whether a bus device, among a plurality of bus devices, has been assigned an address by a gateway ([0058] The master unit (gateway) starts a status query in step 150 through the bus line to the just addressed slave which has the address 1. The master unit ensures with this status query that the addressing was successful (an address state of already addressed). In addition, it uses the status query here to determine whether other slave units are still to be addressed (an address state of needing an address).); and
set a switch control signal provided from a first control port of the bus device to a second control port of the connection unit to which the bus device is connected, based on the address assignment state ([0059] If the master unit received from the addressed slave unit the response through the bus line (see step 160) that the addressing was successful, it will send through the bus line to the just addressed unit having the address 1 the instruction to set its relay to the ON status, in which the switch 13a is closed and the control signal thus can be passed on to the next slave unit. Fig. 2, [0042] The microcomputer (in the slave unit) is equipped in the embodiment shown here also with an output 15 which is used to control the relay 13 that is set depending on the signal (switch control signal) applied through the interface (connection unit)), the switch control signal being used for controlling an on-off state of a switch (switch 13 of Fig. 2) among a plurality of switches located within the plurality of connection units, wherein the switch is within the connected connection unit ([0037] The enable circuit 10 comprises in the embodiment shown here a relay 13, which is connected through a switch 13a with the control ports 12) and is set to control a delivery of an address signal generated by the gateway to a downstream connection unit of the plurality of connection units along an address assignment line coupled to a first address port of the gateway ([0059] If the master unit (gateway) received from the addressed slave unit the response through the bus line (see step 160) that the addressing was successful, it will send through the bus line to the just addressed unit having the address 1 the instruction to set its relay to the ON status, in which the switch 13a is closed and the control signal (address signal) thus can be passed on to the next slave unit (a downstream connection unit integrated with the downstream slave unit)).
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Schultz does not teach a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program is executable by a processor to perform the steps above.
Buenaventura in the same field of endeavor of addressing of slave devices teaches a non-transitory computer-readable storage medium having a computer program stored thereon, which is executable by a processor to perform at least ([0034] A second aspect of the invention concerns a non-transitory computer readable storage medium, with a computer program stored thereon, the computer program comprising instructions for, when executed by a processor, carrying out the steps of a method according to the first aspect of the invention.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the non-transitory computer-readable storage medium of Buenaventura with the addressing method of master-slave bus systems of Jerolm in view of Schultz. The motivation to do so would have been to improve the efficiency of the addressing method by measuring a value of a current consumption on the power line before sending the command to change the common default address of the slave device of index k. This ensures to perform the addressing step only if a new slave device is detected. (Buenaventura; [0020] – [0021]).
Regarding claim 18, Jerolm, Schultz and Buenaventura teach the non-transitory computer-readable storage medium of claim 17, and Schultz teaches wherein the processor is configured to set the switch control signal by:
setting, in response to the bus device not being assigned an address by the gateway, the switch control signal to be a first control signal, so that a switch within the connected connection unit is in an open state ([0021] Prior to applying the signal, the master unit preferably forces al the slave units to be addressed to open their switch, for example with a corresponding broadcast signal. As an alternative--for example during a procedure to redirect addressing of certain slave units--the master unit provides an appropriate switching signal directed at these slave units at the interface, so that the control line is interrupted only in each slave unit to be addressed. [0055] At the beginning of the addressing operation, the master unit sends in step 100 a broadcast message to all slave units connected to the bus, which causes the slave units (bus devices) to switch their relays to the OFF state. Fig. 2, [0042] The microcomputer (in the bus device) is equipped in the embodiment shown here also with an output 15 (switch control signal) which is used to control the relay 13 that is set depending on the signal applied through the interface. For example, in the embodiment shown here, the output 15 determines the position of the switches 13a and 13b.); and
setting, in response to the bus device being assigned an address by the gateway, the switch control signal to be a second control signal different from the first control signal, so that the switch within the connected connection unit is in a closed state ([0059] If the master unit received from the addressed slave unit the response through the bus line (see step 160) that the addressing was successful, it will send through the bus line to the just addressed unit having the address 1 the instruction to set its relay to the ON status. [0068] Upon the receipt at the bus interface of a corresponding signal which is directed to the slave unit, the slave unit reverses the switch, which results in the enabled status and leads to a transition into the locked state indicated in FIG. 5 as addressing OFF (address assignment state) (steps 320 and 330). The slave unit (bus device) is not addressable in this state. [Fig. 2, [0042] The microcomputer (of the slave unit) is equipped in the embodiment shown here also with an output 15 (switch control signal) which is used to control the relay 13 that is set depending on the signal applied through the interface.).
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Regarding claim 19, Schultz teaches the non-transitory computer-readable storage medium of claim 18, wherein the processor is further configured to set the switch control signal to be the first control signal (open switch) when a slave unit needs to be assigned an address ([0021] Prior to applying the signal, the master unit preferably forces all the slave units to be addressed to open their switch, for example with a corresponding broadcast signal. [0055] At the beginning of the addressing operation, the master unit sends in step 100 a broadcast message to all slave units connected to the bus, which causes the slave units (bus devices) to switch their relays to the OFF state (switch is open). The switch is opened by the slave unit providing a switch control signal to be the first control signal. Fig. 2, [0042] The microcomputer (in the bus device) is equipped … with an output 15 (switch control signal) which is used to control the relay 13.)
Schultz does not teach in response to the bus device having a preset address, set an address.
Buenaventura in the same field of endeavor of addressing slave devices teaches wherein each of the at least one bus device is further configured to: in response to the bus device having a preset address, assign an address. ([0059] By default, and initially, all the slave devices have a common default address, such as 0*FE for example (preset address). [0077] at startup-up, all the slave devices are deactivated by the master device and that the activations are performed iteratively. Fig. 3 shows the iterative process of addressing each slave device. The method comprising, [0016] sending, to the common default address on the communication line, a command to change the common default address of the slave device of index k to a unique address of index k.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the slave units with default addresses of Buenaventura with the addressing method of master-slave bus systems of Schultz. The motivation to do so would have been to improve the efficiency of the addressing method by measuring a value of a current consumption on the power line before sending the command to change the common default address of the slave device of index k. This ensures to perform the addressing step only if a new slave device is detected. (Buenaventura; [0020] – [0021]).
Regarding claim 20, Jerolm, Schultz and Buenaventura teach the non-transitory computer-readable storage medium of claim 17, and Schultz teaches wherein the processor is configured to perform, in response to receiving the address signal via a connection unit to which the bus device is connected, address assignment for the bus device according to a communication with the gateway ([0056] In the next step, step 110, the master unit in this embodiment applies direct voltage between the control line VI and a reference potential GND, which is supplied due to the opened switch of the slave unit only to the first slave unit. Fig. 2 shows the control signal is applied to the control ports 12, which are part of the bus interfaces 11 (connection unit). [0057] After that, the master unit sends in step 130 a broadcast signal through the bus line which assigns the address 1 in an undetermined manner to all slaves. However, since only the first slave unit has been released for addressing, only this slave unit will accept the address 1, see FIG. 5. [0041] The presence of the control signal results in the enable state of the enable input or of the microcomputer. As a result of this, the microcontroller allows the assignment of one address to the slave unit 2 if a corresponding signal is provided at the addressing line of the bus interface.)
It would have been obvious for one of ordinary skill before the effective filing date of the claimed invention to modify the teachings of Jerolm to include the address assignment method of Schultz. The motivation to do so would have been to provide a flexible, simple and quick method for addressing slave units which can be used with a plurality of bus systems. (Schultz; [0013]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NANCY SIXTO whose telephone number is (571)272-3295. The examiner can normally be reached Mon - Friday 9AM-5PM EST.
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/NANCY SIXTO/Examiner, Art Unit 2465
/GARY MUI/Supervisory Patent Examiner, Art Unit 2465
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