DETAILED ACTION
Response to Arguments
Applicant’s arguments, filed 4/15/2026 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 2024/0004140 to Bian.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0004140 to Bian.
Bian discloses in figures 4-13 and paragraph 31, a chip comprising:
a silicon substrate (16);
a first waveguide (12) comprising silicon and nitrogen (Silicon Nitride; paragraph 33);
a second waveguide (26) comprising silicon (paragraph 28), wherein a portion of the first waveguide overlaps a portion of the second waveguide (figure 4); and
an oxide layer (14) coupled with a face of the silicon substrate, wherein a first portion of the oxide layer between the silicon substrate and the first waveguide has a thickness that is greater than a thickness of a second portion of the oxide layer that is between the second waveguide and the oxide layer (unlabeled area between 26 and 14 in figure 4. The claim language describing the thicknesses defines the waveguides overlapping one another which is shown in figure 4).
Bian discloses the thickness “S” between the two waveguides as being 500nm to 1.5 microns (paragraph 31).
Claim 10 recites similar structure to the above but removes the language of the waveguides being present. The above disclosed waveguide portions contain their respective silicon and silicon nitride layers.
Although Bian discloses a thickness between waveguides, Bian fails to explicitly disclose the distance between the first waveguide (26 in Bian) and the oxide layer interface touching the substrate (bottom of 14) being between 1.5-3 microns and the thickness between the bottom of the oxide layer and the second waveguide of 1 micron.
It would have been obvious to one having ordinary skill in the art to visually estimate that the thicknesses in Bian figure 4 would match the claimed ranges. Even assuming they do not, one would be able to adjust and set the layer thickness as claimed to optimize chip performance and size.
Claim(s) 2, 5, 8, 11,14, 17, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bian as applied to claims above, and further in view of US 10,473,858,to Mahgerefteh et al.
Bian discloses the invention as claimed except for the below that are satisfied with Mahgerefteh.
As to claim 2, there is an oxide layer between a first and second waveguide portion (206; figure 2).
As to claim 5, figure 5 shows a taper area in a direction perpendicular to the face of the silicon substrate.
Claims 8 and 17 makes mention of the waveguides being adjacent without any specific locations. This limitation only requires the two waveguides to be in the same proximity as one another. The prior art waveguides certainly are adjacent to one another in figure 5.
Claims 11 and 14 relate to the similar claims 5 and 8 above.
Claim 19 is similar to the above but describes a portion of a silicon waveguide and silicon nitride waveguide within an oxide layer. This feature is shown both in figures 2 and 5 for the waveguide portions surrounded by oxide.
As to claim 20, the portion of the silicon waveguide is tapered (508).
It would have been obvious to one having ordinary skill in the art to add a third layer as taught by Mahgerefteh in Bian to further reduce coupling losses.
Claim(s) 3-4, 7, 12-13, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bian in view of Mahgerefteh.
Bian in view of Mahgerefteh discloses the invention as claimed except for variations in thickness.
It would have been obvious to one having ordinary skill in the art to use the claimed thicknesses since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim(s) 6, 9, 15 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bian in view of Mahgerefteh as applied to claims above, and further in view of US 2022/0013985 to Koch et al.
Bian in view of Mahgerefteh discloses the invention as claimed except for the angled facet in a direction parallel to the propagation. Such angles are commonly used to couple light between two planes.
Koch discloses such a tapered portion (904) in figures 8-11 to properly redirect light.
It would have been obvious to one having ordinary skill in the art to angle or taper a facet end of a waveguide as taught by Koch in Bian in view of Mahgerefteh to optimize the redirection of a light signal.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eric K Wong whose telephone number is (571)272-2363. The examiner can normally be reached M-Tu, Th-F 8A-6P.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg can be reached at 571-270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
ERIC K. WONG
Primary Examiner
Art Unit 2874
/Eric Wong/Primary Examiner, Art Unit 2874