DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Status of Claims
This office action is in response to "Claims filed on 6/2/2026". Applicant's amendments of claims 1-3 with the same reply have been entered by the Examiner. Upon entry of the amendments, claims 1-21 are pending wherein claims 1 and 13 are independent.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Note applicable to all claims being rejected in this Office action: Examiner notes that the limitations "overlap", "layer", "portion" “disposed” “on” “part” are being interpreted broadly in accordance with MPEP. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. The claim presently discloses a structural limitation (i.e. overlap, layer, portion, contact) that is taught by prior art of record, therefore, the limitation is considered met by the prior art of record. Additionally, Merriam Webster dictionary defines the above limitations as “to occupy the same area in part”, “one thickness lying over or under another”, “an often limited part of a whole” “arranged” “a function word to indicate position in close proximity with” “one of several or many equal units of which something is composed” respectively. Further note the limitation “contact” is being interpreted to include "direct contact" (no intermediate materials, elements or space disposed there between) and "indirect contact" (intermediate materials, elements or space disposed there between).
Claim(s) 1-3, 6-8, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 2018/0012947 A1 hereinafter Lee) as evidenced by Kim et al (US 2017/0365649 A1 hereinafter Kim).
Regarding Claim 1, Lee discloses in Fig 2C: A thin film transistor substrate comprising:
a substrate (110);
a first thin film transistor (140) disposed on the substrate, the first thin film transistor including a first gate electrode (144), a first active layer (141), a first source electrode (142), and a first drain electrode (143);
a second thin film transistor (130) disposed on the substrate, the second thin film transistor including a second gate electrode (134), a second active layer (131) disposed on a different layer as the first active layer, a second source electrode (132), a second drain electrode (133), a first conductive layer (portion of 132 in the via opening) disposed between the second active layer (131) and the second source electrode, and a second conductive layer (portion of 133 in the via opening) disposed between the second active layer and the second drain electrode; and
a capacitor electrode (121) is on a same layer as the second active layer (131), and the first conductive layer [0090-0092].
Lee does not disclose: a capacitor electrode including a first layer and a second layer disposed on the first layer, wherein the first layer of the capacitor electrode is on a same layer as the second active layer, and the second layer of the capacitor electrode is on a same layer as the first conductive layer and; wherein the first layer of the capacitor electrode is in contact with the second layer of the capacitor electrode
However, Kim in a similar display device teaches in Fig 11 a capacitor electrode (CE1) including a first layer (TP1) and a second layer (TP2) disposed on the first layer, wherein the first layer of the capacitor electrode is on a same layer as the second active layer (A1), and the second layer of the capacitor electrode is on a same layer as the first conductive layer (portion of MEP1 inside the via) and; wherein the first layer (TP1) of the capacitor electrode is in contact with the second layer (TP2) of the capacitor electrode.
References Lee and Kim are analogous art because they both are directed to display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify device of Lee with the specified features of Kim because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to combine teachings of Lee and Kim so that a capacitor electrode including a first layer and a second layer disposed on the first layer, wherein the first layer of the capacitor electrode is on a same layer as the second active layer, and the second layer of the capacitor electrode is on a same layer as the first conductive layer and; wherein the first layer of the capacitor electrode is in contact with the second layer of the capacitor electrode as taught by Kim in Lee’s device since, this provides an increased light emission region of the organic light-emitting element OLED.
Regarding Claim 2, Lee and Kim disclose: The thin film transistor substrate according to claim 1, Lee further discloses in Fig 2C: wherein a distance from the second active layer (131) to the second gate electrode (134) is different from a distance from the first active layer (141) to the first gate electrode (144). Note that the claim does not specify how these distances are measured and hence one of ordinary skilled in the art could arbitrarily choose a point on each structure to measure the distances to read on the claimed limitations.
Regarding Claim 3, Lee and Kim disclose: The thin film transistor substrate according to claim 2, Lee further discloses in Fig 2C: wherein a distance from the second active layer (141) to the second gate electrode (144) is greater than a distance from the first active layer (131) to the first gate electrode (134). Note that the claim does not specify how these distances are measured and hence one of ordinary skilled in the art could arbitrarily choose a point on each structure to measure the distances to read on the claimed limitations.
Regarding Claim 6, Lee and Kim disclose: The thin film transistor substrate according to claim 1, Lee further discloses in Fig 2C: wherein the first active layer includes:
a first channel part (CA) overlapping the first gate electrode;
a first connection part (SA) disposed on a first side of the first channel part, the first connection part is in contact with the first source electrode;
a second connection part (DA) disposed on a second side of the first channel part, and
the second connection part is in contact with the first drain electrode (133);
the second active layer includes a second channel part (141) overlapping the second gate electrode (144);
a third connection part (portion of 141 in contact with 142) disposed on a first side of the second channel part, and the third connection part is in contact with the first conductive layer; and a fourth connection part (portion of 141 in contact with 143) disposed on a second side of the second channel part, and the fourth connection part is in contact with the second conductive layer (See Fig 2C).
Regarding Claim 7, Lee and Kim disclose: The thin film transistor substrate according to claim 6, Lee further discloses in Fig 2C: wherein the second active layer includes:
a first intermediate part disposed between the second channel part and the third connection part;
a second intermediate part disposed between the second channel part and the fourth connection part (See mark-up below and interpretation of “part” in note above);
the first intermediate part overlaps a region between the second gate electrode and the first conductive layer; and
the second intermediate part overlaps a region between the second gate electrode and the second conductive layer. Examiner notes that the claim does not specify an overlap direction and hence the intermediate parts are being chosen so as to overlap the structures claimed in any direction/view.
Regarding Claim 8, Choi discloses in Fig 4, 5: The thin film transistor substrate according to claim 1, wherein the capacitor electrode (121) is electrically connected to the first source electrode (132) and the capacitor electrode overlaps at least a portion of the first active layer. Examiner notes that the claim does not specify an overlap direction and hence the capacitor electrode and the first active layer overlap; additionally, since the capacitor and the first transistor belong to the same display device, they are electrically connected to one another.
Regarding Claim 21, Lee and Kim discloses in Fig 2C: A display apparatus comprising:
a thin film transistor substrate (110) according to claim 1;
a first electrode (181) disposed on the thin film transistor substrate;
a light emitting layer (182) disposed on the first electrode; and
a second electrode (183) disposed on the light emitting layer [0089].
Allowable Subject Matter
Claims 4-5, 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 4, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein the first gate electrode and the second gate electrode are disposed on a same layer, or the first gate electrode and the second gate electrode include a same material, and the second active layer is disposed below the first active layer” as recited in claim 4 in combination with the remaining features.
Dependent claim 5 is allowed based on virtue of its dependencies
The most relevant prior art references, (US 20170278916 A1) to Maruyama, Satoshi in Fig 4 substantially teaches the limitations of the claim 4, with the exception of the limitations described in the preceding paragraph.
With respect to claim 9, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “a first channel part overlapping the first gate electrode, a first connection part disposed on a first side of the first channel part, and the first connection part is in contact with the first source electrode; a second connection part disposed on a second side of the first channel part, and the second connection part is in contact with the first drain electrode; and the capacitor electrode overlapping the first connection part, and the capacitor electrode not overlapping the second connection part.” as recited in claim 9 in combination with the remaining features.
The most relevant prior art references, (US 20170278916 A1) to Maruyama, Satoshi in Fig 4 substantially teaches the limitations of the claim 9, with the exception of the limitations described in the preceding paragraph.
With respect to claim 10, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “a light blocking layer overlapping at least a portion of the first active layer and the capacitor electrode below the capacitor electrode, wherein a capacitor comprises the light blocking layer and the capacitor electrode.” as recited in claim 10 in combination with the remaining features.
Dependent claim 11 is allowed based on virtue of its dependencies
The most relevant prior art references, (US 20170278916 A1) to Maruyama, Satoshi in Fig 4 substantially teaches the limitations of the claim 10, with the exception of the limitations described in the preceding paragraph.
With respect to claim 12, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “a light blocking layer overlapping at least a portion of the second active layer, the light blocking layer electrically connected to the second source electrode, wherein a capacitor comprises the light blocking layer and the capacitor electrode.” as recited in claim 12 in combination with the remaining features.
The most relevant prior art references, (US 20170278916 A1) to Maruyama, Satoshi in Fig 4 substantially teaches the limitations of the claim 12, with the exception of the limitations described in the preceding paragraph.
Claims 13-20 are allowed.
The following is an examiner’s statement of reasons for allowance: With respect to claim 13, the primary reason for allowance is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “the first layer of the first gate electrode is disposed on a same layer as the second active layer or the first layer of the first gate electrode contains a same material as the second active layer, and the second layer of the first gate electrode is disposed on a same layer as the first conductive layer or the second layer of the first gate electrode contains a same material as the first conductive layer.” as recited in claim 13 in combination with the remaining features.
Dependent claims 14-20 are allowed based on virtue of their dependencies
The most relevant prior art references, (US 20170278916 A1) to Maruyama, Satoshi in Fig 4 substantially teaches the limitations of the claim 13, with the exception of the limitations described in the preceding paragraph.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NISHATH YASMEEN whose telephone number is (571)270-7564. The examiner can normally be reached Mon-Fri 9AM-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NISHATH YASMEEN/Primary Examiner, Art Unit 2811
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