DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-21 are rejected under 35 U.S.C. 103 as being unpatentable over Croxford (US 10,509,743), in view of Holm (US 6,622,183).
Referring to claims 1-2, 9, 12 and 15, Croxford discloses an apparatus (fig. 1, data processing apparatus 2) comprising:
a display controller (fig. 1, display processor 10);
communication circuitry (fig. 1, interconnect IC 22) coupled to the display controller;
memory controller circuitry [memory interface circuitry of claim 9] (fig. 1, DMC 24) coupled to a first memory (fig. 1, memory 26, buffer 40/45) and a second memory (fig. 1, memory 26, buffer 40/45), the first memory to store a plurality of animation frames (2:42-55, frames of image data); and
a direct memory access DMA controller [event receiver/animation control/communication circuitry of claim 9] (fig. 1, DMA 12)
coupled to the communication circuitry and the memory controller circuitry, and
to operate independently of a main controller (fig. 1, CPU 4) during initialization of the main controller, and
to receive an indication (fig. 1, signal from control 42 of processor 10 to control of DMA 42 with status of buffers 40) from the display controller to load an animation frame (2:42-55, frames of image data) of the plurality of animation frames; and
cause the display controller to output the frame to a display circuit (fig. 1, display 14; 4:8-18).
Holm discloses in response to the indication from the display controller and a loading condition (fig. 5, write_strobe to FIFO 16) being satisfied,
cause the memory controller circuitry to transfer or copy a next animation frame (fig. 5, DATA[7:0] to FIFO 16), of the plurality of animation frames, from the first memory (fig. 5, DATA[7:0] input to FIFO 16; i.e., from Croxford’s buffer 40/45 in DMA 12/IC 22/DMC 24) to the second memory (fig. 5, FIFO 16; i.e., to Croxford’s display processor’s buffer 40), in which
the loading condition is based on a comparison (fig. 5, FRAME_COUNT 98) of a frame counter value (fig. 5, WRITE_INCREMENT 92) to a frame counter threshold (fig. 5, READ_DECREMENT 94) representing a number of animation frames to be displayed (fig. DATA[7:0] output from FIFO 16) before loading a subsequent animation frame (fig. 4, next DATA[7:0] to FIFO 16);
update a frame pointer (fig. 5, FRAME_COUNT_REG from latch 100) [in a register (claims 9 and 15)] used by the display controller to reference the frame;
Croxford and Holm are analogous art because they are from the same field of endeavor in display controller using buffers/FIFOs. At the time of the filing, it would have been obvious to a person of ordinary skill in the art, having the teaching of Croxford and Holm before him or her to modify the DMA controller of Croxford to include the frame counter controlled FIFOs of Holm, thereafter the frames to be displayed are controlled with frame counter. The suggestion and/or motivation for doing so would be obtaining the advantages of improved image data transmission (2:30-42) as suggested by Holm. Therefore, it would have been obvious to combine Croxford with Holm to obtain the invention as specified in the instant application claims.
As to claims 3, 13 and 16-17, Holm discloses the apparatus of claim 1, wherein the DMA controller is to, in response to a determination (fig. 5, up/down counter 88) that the frame counter value has not reached the frame counter threshold, increment (fig. 5, WRITE_INCREMENT 92) the frame counter. [see TSM analysis above]
As to claims 4 and 11, Croxford discloses the apparatus of claim 1, wherein the first memory is a flash memory (3:28-39, flash) and the second memory is a random access memory (3:28-39, SRAM/DRAM).
As to claim 5, Croxford discloses the apparatus of claim 1, wherein the display controller is to access the next animation frame from the second memory (fig. 1, access frame from memory 26 to buffer 40 and display 14).
As to claims 7 and 18-19, Corxford discloses the apparatus of claim 1, wherein
the DMA controller is to transfer or copy the next animation frame from the first memory to the second memory using a first channel (fig. 1, channel between memory 26 to buffer 40),
the DMA controller is to update the frame pointer using a second channel (fig. 1, channel between buffer 40 and control), and
the DMA controller is to cause the display controller to output the next animation frame using a third channel (fig. 1, channel between buffer 40 and display 14).
As to claims 8, 10 and 20, Holm discloses the apparatus of claim 1, wherein the indication from the display controller is a vertical synchronization signal (fig. 6, re-sync 116, WRITE_COUNT_RESYNC 130). [see TSM analysis above]
As to claims 14 and 19, Croxford discloses the controller of claim 12, wherein the animation control circuitry is to modify (4:43-49, alpha blending or compositing) the next animation frame prior to the memory interface circuitry writing the next animation frame to the second memory.
As to claim 21, Holm discloses the apparatus of claim 1, wherein, to cause the display controller to output the next animation frame to the display circuit, the DMA controller is to set a control bit (fig. 5, READ_STROBE to FIFO 16). [see TSM analysis above]
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
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