DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Croxford (US 10,509,743), in view of Kobayashi (US 10,572,967).
Referring to claims 1, 9 and 15, Croxford discloses an apparatus (fig. 1, data processing apparatus 2) comprising:
a display controller (fig. 1, display processor 10, video processor 8, CPU 4, GPU 6);
communication circuitry (fig. 1, interconnect 22) coupled to the display controller;
memory controller circuitry [memory interface circuitry of claim 9] (fig. 1, DMC 24, DMA 12) coupled to a first memory (fig. 1, memory 26) and a second memory (fig. 1, buffer 40); and
programmable circuitry [event receiver/animation control/communication circuitry of claim 9] (fig. 1, control circuitry 42; 6:47-50) coupled to the communication circuitry and the memory controller circuitry to:
cause the display controller to output the frame to a display circuit (fig. 1, output from buffer 40 to display 14).
Kobayashi discloses that receive an indication (fig. 2, vertical synchronization signal; fig. 12) from the display controller (4:38-47) to load a frame (2:42-44, image data frame);
in response to the indication from the display controller and a loading condition (fig. 3, frame count 330; fig. 12, frame count) being satisfied, cause the memory controller circuitry to transfer or copy the frame from the first memory (fig. 1, line buffer 510) to the second memory (fig. 1, line buffer 530);
update a frame pointer (7:59-18, offset address) used by the display controller to reference the frame.
Croxford and Kobayashi are analogous art because they are from the same field of endeavor in display controller. At the time of the filing, it would have been obvious to a person of ordinary skill in the art, having the teaching of Croxford and Kobayashi before him or her to modify the DMA controller of Croxford to include the instruction control section of Kobayashi, thereafter the frames to be displayed are controlled with vertical synchronization signal and frame counter. The suggestion and/or motivation for doing so would be obtaining the advantages of improved image data processing (3:15-22) as suggested by Kobayashi. Therefore, it would have been obvious to combine Croxford with Kobayashi to obtain the invention as specified in the instant application claims.
As to claims 2, 12, 16 and 18, Kobayashi discloses the apparatus of claim 1, including a frame counter (fig. 3, frame counter 310), wherein the loading condition is a frame counter value (fig. 3, frame count 311; 9:27-28), and the programmable circuitry is to cause the memory controller circuitry to transfer or copy the frame from the first memory (fig. 1, buffer 510) to the second memory (fig. 1, buffer 530) in response to a determination that the frame counter value (fig. 3, comparator 314) meets or exceeds a frame counter threshold (fig. 3, reg_fcnt_max). [see TSM analysis as above in claim 1]
As to claims 3, 13 and 17, Kobayashi discloses the apparatus of claim 2, wherein the programmable circuitry is to, in response to a determination that the frame counter value has not reached the frame counter threshold, increment (fig. 3, increment 312) the frame counter (fig. 3, frame count 311; 9:27-28). [see TSM analysis as above in claim 1]
As to claims 4 and 11, Croxford discloses the apparatus of claim 1, wherein the first memory is a flash memory (3:28-39, flash) and the second memory is a random access memory (3:28-39, SRAM/DRAM).
As to claim 5, Croxford discloses the apparatus of claim 1, wherein the display controller is to access the frame from the second memory (fig. 1, access frame from memory 26 to buffer 40 and display 14).
As to claim 6, Croxford discloses the apparatus of claim 1, wherein the programmable circuitry is implemented using a direct memory access controller (fig. 1, direct memory access controller DMC 24).
As to claim 7, Corxford discloses the apparatus of claim 6, wherein the direct memory access controller is to transfer or copy the frame from the first memory to the second memory using a first channel (fig. 1, channel between memory 26 to buffer 40), the direct memory access controller is to update the frame pointer using a second channel (fig. 1, channel between buffer 40 and control), and the direct memory access controller is to cause the display controller to output the frame using a third channel (fig. 1, channel between buffer 40 and display 14).
As to claims 8, 10 and 20, Kobayashi discloses the apparatus of claim 1, wherein the indication from the display controller is a vertical synchronization signal (fig. 2, vertical synchronization signal). [see TSM analysis as above in claim 1]
As to claims 14 and 19, Croxford discloses the controller of claim 12, wherein the animation control circuitry is to modify (4:43-49, alpha blending or compositing) the frame prior to the memory interface circuitry writing the frame to the second memory.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP §706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire in THREE MONTHS from the mailing date of this action. In the event a first reply is filled within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date of the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136 (a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615