DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claim 43 is objected to because it depends a cancelled Claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6, 9, 11-13, 15-21, 31, 33, 36, 39, 43 and 61 are rejected under 35 U.S.C. 103 as being unpatentable over US 20240103238 A1 (Dabral), in view of Liu, D. and Park, S., 2014. Three-dimensional and 2.5 dimensional interconnection technology: State of the art. Journal of Electronic Packaging, 136(1), p.014001 (Liu) and in further view of US 20180331051 A1 (Dogiamis) and US 11183756 B1 (Pond),
Regarding Claims 1, 31 and 61:
A packaged module comprising: a packaging substrate including a plurality of interposer layers; an array of receive elements implemented on a respective interposer layer, each receive element partitioned into a first block configured to provide high-performance functionality, and a second block configured to provide digitally-intensive low-performance functionality, the first and second blocks in combination configured to provide multi-channel beamforming functionality (Dabral: Figs. 4A-B, [0035]-[0042], a 3D multichip module that has a mid-layer interposer 112; the interposer layer 112 comprises of one or more dielectric layers 116 and metal wiring layers 114… A topmost dielectric layer 116 may be an oxide layer and include metal traces and landing pads 117… may additionally include a plurality of devices 113, including passive devices such as MIM capacitors (planar or 3D) or trench capacitors, magnetic elements (inductors, coupled inductors, etc.), or even active devices such as transistors. In an embodiment, the mid-layer interposer includes an array of trench capacitors, which indicates a multi-layer interposer; [0027], 3D module includes high performance components, e.g., HSIO, CPU, GPU, RF antenna and low speed components e.g., LSIO, cache, PMIC, RF baseband and etc.; Liu further illustrates various implementations of using such configuration, e.g., Liu: Fig. 2, interposer layers containing TSVs. It is further noted that for a RF module, integrating power transmitter, receiver, and antenna into a single package is known practice in the field, e.g., Dogiamis: [0013]-[0017]).
It would have been obvious for one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Dabral with an interposer implementation as further taught by Liu and high integration of various RF components as Dogiamis. The advantage of doing so is to enable a 3D manufacturing for higher integration and performance.
Dabral does not teach explicitly on a beamform component on an MCM. However, Pond teaches (Pond: e.g., Figs. 8-11, a MCM module with a beamforming component for a phased array module).
It would have been obvious for one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Dabral with a beamform component on an MCM as further taught by Pond. The advantage of doing so is to enable a small package size for a RF antenna system (Pond: Background).
Regarding Claims 3 and 33, Dabral as modified further teaches:
The packaged module of claim 1 wherein the first block is implemented to occupy a relatively small area on a die formed from a high-cost process technology node (Dogiamis: [0013]-[0017], where particular composition of components are product dependent).
Regarding Claim 6, Dabral as modified further teaches:
6. The packaged module of claim 3 wherein the first block includes at least a portion of a low-noise amplifier (Dogiamis: [0013]-[0017]).
Regarding Claims 9 and 39, Dabral as modified further teaches:
The packaged module of claim 1 wherein the second block is implemented to occupy a relatively large area on a die formed from a low-cost process technology node (Dogiamis: [0013]-[0017], where particular composition of components are product dependent).
Regarding Claim 11, Dabral as modified further teaches:
The packaged module of claim 9 wherein the second block includes a beamformer die (Pond: Figs. 8-11).
Regarding Claim 12, Dabral as modified further teaches:
The packaged module of claim 9 wherein the second block includes a low-performance component (Dabral: Figs. 4A-B, [0027]).
Regarding Claim 13, Dabral as modified further teaches:
The packaged module of claim 12 wherein the low-performance component includes a portion of a low-noise amplifier (Dogiamis: [0013]-[0017]).
Regarding Claim 15, Dabral as modified further teaches:
The packaged module of claim 12 wherein the low-performance component includes a phase shifter (Pond: e.g., Figs. 8-11, a MCM module with a beamforming component for a phased array module).
Regarding Claim 16, Dabral as modified further teaches:
The packaged module of claim 12 wherein the low-performance component includes a variable gain amplifier stage (Dogiamis: [0013]-[0017], where the variable gain amplifier is known practice in the field).
Regarding Claim 17, Dabral as modified further teaches:
The packaged module of claim 12 wherein the low-performance component includes a temperature sensor (Pond: (38), MCM may include temperature sensors).
Regarding Claim 18, Dabral as modified further teaches:
The packaged module of claim 12 wherein the low-performance component includes a bias circuit (Dogiamis: [0013]-[0017], where the bias circuits are widely used in RF circuits).
Regarding Claim 19, Dabral as modified further teaches:
The packaged module of claim 9 wherein the second block includes a digitally-intensive component (Dabral: [0027], RF baseband component).
Regarding Claim 20, Dabral as modified further teaches:
The packaged module of claim 19 wherein the digitally-intensive component includes one or more of a control circuit, a memory circuit, and a lookup table (Dabral: Figs. 4A-B).
Regarding Claim 21, Dabral as modified further teaches:
The packaged module of claim 1 further comprising passive devices implemented on a respective interposer layer and configured to function with either or both of the first and second blocks (Dabral: Figs. 4A-B, [0035]-[0042], caps).
Regarding Claim 36 and 43, Dabral as modified further teaches:
The packaged module of claim 33 wherein the first block includes at least a portion of a power amplifier (Dabral: [0027]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHITONG CHEN whose telephone number is (571) 270-1936. The examiner can normally be reached on M-F 9:30am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yuwen Pan can be reached on 571-272-7855. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHITONG CHEN/
Primary Examiner, Art Unit 2649
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