DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9-14, 22-27, and 35-39 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Srivastava et al., US PGPub 2024/0111700, hereafter “Srivastava.”
With respect to claim 1, Srivastava teaches a device control method, configured for a memory storage device, the device control method comprising:
establishing a connection between the memory storage device and a host system (par. 70 and fig. 5B, a multiple lane data link between the host 542 and an endpoint 506. Par. 40 discloses that a memory subsystem is an example of an endpoint);
performing a first communication with the host system based on the connection and a first connection interface standard (par. 70, the multiple lane data link at a data rate corresponding to a GEN2 interface standard);
performing a data recovery operation between the memory storage device and the host system via the connection during a period of performing the first communication (pars. 70-71, the second set of lanes transition to a recovery state, while the first set of data lanes continue to transmit data traffic at the GEN2 data rate); and
switching to perform a second communication with the host system based on the connection and a second connection interface standard in a case that the data recovery operation is successfully performed, wherein the first connection interface standard is different from the second connection interface standard (par. 72. the second set of data lanes are changed to the new data rate, GEN3).
With respect to claim 9, Srivastava teaches the device control method of claim 1, further comprising:
updating a second parameter during a period of performing the second communication, wherein the second parameter reflects a signal quality of the second communication (par. 37, the data rate demands are the second parameter); and
switching back to perform the first communication with the host system based on the connection and the first connection interface standard in response to the second parameter meeting a second condition (par. 37, the PCIe link is operated at the lower GEN speed until there are high data rate demands on the link, which corresponds to the second parameter meeting a second condition).
With respect to claim 10, Srivastava teaches the device control method of claim 9, wherein the step of switching back to perform the first communication with the host system based on the connection and the first connection interface standard comprises:
switching back to perform the first communication with the host system based on the connection and the first connection interface standard according to log information, wherein the log information is configured to record information of the first connection interface standard previously used (par. 47, the Configuration state 406 is the log information, which stores the GEN speed to switch to, as described previously in par. 37).
With respect to claim 11, Srivastava teaches the device control method of claim 1, wherein the first connection interface standard and the second connection interface standard are two of a first generation, a second generation, a third generation, a fourth generation, and a fifth generation of a high-speed peripheral component interconnect express standard (par. 71, the interface standards are second and third generation (GEN2 and GEN3)).
With respect to claim 12, Srivastava teaches the device control method of claim 11, wherein in a case that the first connection interface standard is the fifth generation of the high-speed peripheral component interconnect express standard, the second connection interface standard is one of the first generation, the second generation, the third generation, and the fourth generation of the high-speed peripheral component interconnection express standard (par. 85, the data rate is decreased from GEN5 to GEN2. Note that this is a conditional limitation and is not required to occur),
in a case that the first connection interface standard is the fourth generation of the high-speed peripheral component interconnect express standard, the second connection interface standard is one of the first generation, the second generation, and the third generation of the high-speed peripheral component interconnection express standard (par. 87, the data rate is decreased from GEN4 to GEN3. Note that this is a conditional limitation and is not required to occur),
in a case that the first connection interface standard is the third generation of the high-speed peripheral component interconnect express standard, the second connection interface standard is one of the first generation and the second generation of the high-speed peripheral component interconnect express standard (par. 85, the data rate is decreased from GEN3 to GEN2. Note that this is a conditional limitation and is not required to occur), and
in a case that the first connection interface standard is the second generation of the high-speed peripheral component interconnect express standard, the second connection interface standard is the first generation of the high-speed peripheral component interconnect express standard (par. 37, the data rate is changed to operate at a lower speed, so changing from GEN2 means changing to GEN1. Note that this is a conditional limitation and is not required to occur).
With respect to claim 13, Srivastava teaches the device control method of claim 1, wherein the first communication performed based on the first connection interface standard and the second communication performed based on the second connection interface standard adopt different data transfer standards (par. 71, the first connection interface standard is GEN2 and the second interface standard is GEN3).
With respect to claim 14, Srivastava teaches a memory storage device, comprising:
a connection interface unit configured to be coupled to a host system (par. 44 and fig. 2, system bus interface 215, connected to host controller 212);
a rewritable non-volatile memory module (par. 44 and fig. 2, host system memory 240. Par. 127 discloses the system memory may be an EEPROM, which is a rewritable non-volatile memory module); and
a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module (par. 44 and fig. 2, PCIe interface 216),
wherein the memory control circuit unit is configured to:
establish a connection between the memory storage device and the host system (par. 70 and fig. 5B, a multiple lane data link between the host 542 and an endpoint 506. Par. 40 discloses that a memory subsystem is an example of an endpoint);
perform a first communication with the host system based on the connection and a first connection interface standard (par. 70, the multiple lane data link at a data rate corresponding to a GEN2 interface standard);
perform a data recovery operation between the memory storage device and the host system via the connection during a period of performing the first communication (pars. 70-71, the second set of lanes transition to a recovery state, while the first set of data lanes continue to transmit data traffic at the GEN2 data rate); and
switch to perform a second communication with the host system based on the connection and a second connection interface standard in a case that the data recovery operation is successfully performed, wherein the first connection interface standard is different from the second connection interface standard (par. 72. the second set of data lanes are changed to the new data rate, GEN3).
Claims 22-26 correspond to claims 9-13, but depend from claim 14, and are rejected using similar logic.
With respect to claim 27, Srivastava teaches a memory control circuit unit, configured to control a rewritable non-volatile memory module in a memory storage device, the memory control circuit unit comprising:
a host interface configured to be coupled to a host system (par. 44 and fig. 2, PCIe Interface 216 is coupled to the host system 212 via the system bus);
a memory interface configured to be coupled to the rewritable non-volatile memory module (par. 44 and fig. 2, system bus interface 215); and
a memory management circuit coupled to the host interface and the memory interface,
wherein the memory management circuit is configured to:
establish a connection between the memory storage device and the host system (par. 70 and fig. 5B, a multiple lane data link between the host 542 and an endpoint 506. Par. 40 discloses that a memory subsystem is an example of an endpoint);
perform a first communication with the host system based on the connection and a first connection interface standard (par. 70, the multiple lane data link at a data rate corresponding to a GEN2 interface standard);
perform a data recovery operation between the memory storage device and the host system via the connection during a period of performing the first communication (pars. 70-71, the second set of lanes transition to a recovery state, while the first set of data lanes continue to transmit data traffic at the GEN2 data rate); and
switch to perform a second communication with the host system based on the connection and a second connection interface standard in a case that the data recovery operation is successfully performed, wherein the first connection interface standard is different from the second connection interface standard (par. 72. the second set of data lanes are changed to the new data rate, GEN3).
Claim 35-39 correspond to claims 9-13, but depend from claim 27, and are rejected using similar logic.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-3, 5, 7-8, 15-16, 18, 20-21, 28-29, 31, and 33-34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Srivastava as applied to claim 1 above, in view of Akavaram et al, US PGPub 2024/0202140, hereafter “Akavaram.”
With respect to claim 2, Srivastava teaches all limitations of the parent claim, but fails to teach performing the data recovery operation in response to a signal quality of the first communication being less than a preset condition during the period of performing the first communication. Akavaram teaches the device control method of claim 1, wherein the step of performing the data recovery operation between the memory storage device and the host system via the connection during the period of performing the first communication comprises:
performing the data recovery operation (par. 66, reconfiguring the link) in response to a signal quality of the first communication being less than a preset condition during the period of performing the first communication (par. 66, determining if the number of lanes in electrical idle are equal or more in number to the currently active lanes).
It would have been obvious to one of ordinary skill in the art, having the teachings of Srivastava an Akavaram before him before the earliest effective filing date, to modify the memory communication method of Srivastava with the memory communication method of Akavaram, in order to reduce power consumption, as taught by Akavaram in par. 65.
With respect to claim 3, Srivastava and Akavaram teach all limitations of the parent claim. Akavaram further teaches the device control method of claim 2, further comprising:
determining that the signal quality of the first communication is less than the preset condition in response to an error event for the first communication during the period of performing the first communication (par. 66, detecting a faulty lane is the error event).
With respect to claim 5, Srivastava teaches all limitations of the parent claim, but fails to teach updating a first parameter during the period of performing the first communication, wherein the first parameter reflects a signal quality of the first communication; and switching to perform the second communication with the host system based on the connection and the second connection interface standard in response to the first parameter meeting a first condition in the case that the data recovery operation is successfully performed. Akavaram teaches the device control method of claim 1, wherein the step of switching to perform the second communication with the host system based on the connection and the second connection interface standard in the case that the data recovery operation is successfully performed comprises:
updating a first parameter during the period of performing the first communication, wherein the first parameter reflects a signal quality of the first communication (par. 66, the first parameter is the link width and reflects the number of lanes in electrical idle); and
switching to perform the second communication with the host system based on the connection and the second connection interface standard in response to the first parameter meeting a first condition in the case that the data recovery operation is successfully performed (pars. 70-72, after reconfiguring the lanes, the lanes are brought up to the requested rate, the GEN speed)).
It would have been obvious to one of ordinary skill in the art, having the teachings of Srivastava an Akavaram before him before the earliest effective filing date, to modify the memory communication method of Srivastava with the memory communication method of Akavaram, in order to reduce power consumption, as taught by Akavaram in par. 65.
With respect to claim 7, Srivastava and Akavaram teach all limitations of the parent claim. Akavaram further teaches the device control method of claim 5, wherein the step of updating the first parameter during the period of performing the first communication comprises:
updating the first parameter according to a proportion of a second signal configured to perform a signal verification among all transferred signals between the memory storage device and the host system during the period of performing the first communication (par. 66, it is determined if the number of lanes in electrical idle are equal or more in number to the currently active lanes, i.e. if the proportion is equal or greater to determine if the link width is acceptable).
With respect to claim 8, Srivastava and Akavaram teach all limitations of the parent claim. Akavaram further teaches the device control method of claim 5, wherein the step of updating the first parameter during the period of performing the first communication comprises:
updating the first parameter according to a total number of times that the data recovery operation is performed during the period of performing the first communication (par. 66, there are a number of retry attempts to make the faulty lane active before determining the link width).
Claims 15-16, 18, and 20-21 correspond to claims 2-3, 5 and 7-8, but depend from claim 14, and are rejected using similar logic.
Claims 28-29, 31, and 33-34 correspond to claims 2-3, 5 and 7-8, but depend from claim 27, and are rejected using similar logic.
Claim(s) 4, 17 and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Srivastava and Akavaram as applied to claims 1-3, 14-16 and 27-29 above, in view of WO 2012/151662, issued to Wollesen, hereafter “Wollesen.”
With respect to claim 4, Srivastava and Akavaram teach the limitations of the parent claims but fail to teach wherein the error event comprises a signal decoding error for the first communication. Wollesen teaches the device control method of claim 3, wherein the error event comprises a signal decoding error for the first communication (par. 69, QoS parameters are based on an error in the decoded signal).
It would have been obvious to one of ordinary skill in the art, having the teachings of Srivastava, Akavaram, and Wollesen before him before the earliest effective filing date, to modify the communication method of Srivastava and Akavaram with the communication method of Wollesen, in order to use QoS parameters to dynamically tune algorithm parameters or processes carried out by a device to minimize time consuming and expensive computations or signal flows as only when needed, as taught by Wollesen in par. 69.
Claim 17 corresponds to claim 4, but depends from claim 16, and is rejected using similar logic.
Claim 30 corresponds to claim 4, but depends from claim 29, and is rejected using similar logic.
Claim(s) 6, 19 and 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Srivastava and Akavaram as applied to claims 1, 5, 14, 18, 27 and 31 above, in view of Daghighian et al., US PGPub 2016/0378132, hereafter “Daghighian.”
With respect to claim 6, Srivastava and Akavaram teach the limitations of the parent claims but fail to teach updating the first parameter according to a measurement parameter of an eye diagram of a first signal transferred between the memory storage device and the host system during the period of performing the first communication. Daghighian teaches the device control method of claim 5, wherein the step of updating the first parameter during the period of performing the first communication comprises:
updating the first parameter according to a measurement parameter of an eye diagram of a first signal transferred between the memory storage device and the host system during the period of performing the first communication (par. 48, performing a signal quality analysis by performing an eye diagram analysis to provide eye quality metrics, the first parameter of the claim).
It would have been obvious to one of ordinary skill in the art, having the teachings of Srivastava, Akavaram, and Daghighian before him before the earliest effective filing date, to modify the communication method of Srivastava and Akavaram with the communication method of Daghighian, in order to use eye quality metrics so a signal monitor may operate faster, consume less power, and have a smaller IC footprint, as taught by Daghighian in par. 21.
Claim 19 corresponds to claim 6, but depends from claim 18, and is rejected using similar logic.
Claim 32 corresponds to claim 6, but depends from claim 31, and is rejected using similar logic.
Response to Arguments
Applicant's arguments filed 09/26/2025 have been fully considered but they are not persuasive. Firstly, the objections to the specification are withdrawn due to the amendments changing the title.
Applicant’s arguments on pages 4-8 are directed towards Srivastava allegedly failing to teach “switching to perform a second communication with the host system based on the connection interface standard in a case that the data recovery operation is successfully performed.” While the link switching process initially begins with receiving a request, the actual switch to perform the second communication occurs only after the recovery and configuration operation (analogous to the claimed data recovery operation), is successfully performed. In other words, the received request triggers step A, and the completion of step A triggers step B. The request doesn’t directly trigger step B.
Applicant’s arguments on pages 8-9 are directed towards Srivastava allegedly failing to teach “performing a first communication with the host system based on the connection and a first connection interface standard; performing a data recovery operation between the memory device and the host system via a connection during a period of performing the first communication; and switching to perform a second communication with the host system based on the connection and a second connection interface standard in a case that the data recovery operation is successfully performed.” Applicant’s arguments are based on mapping “the first connection interface standard” and “the second connection interface standard” to the first set of lanes 511 and second set of lanes 512 of Srivastava. This interpretation is not consistent with what an “interface standard” is. An interface standard is the protocol used- in this case, PCI Express GEN2 and PCI Express GEN3. It does not refer to the actual particular physical lanes used to transfer data, rendering Applicant’s arguments moot.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RYAN DARE/Examiner, Art Unit 2136
/KENNETH M LO/Supervisory Patent Examiner, Art Unit 2136