Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 28 November 2023, 31 July 2024, and 24 April 2025, U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ito et al. (United States Patent Application Publication US20190211475A1), hereinafter referenced as Ito.
In regards to claim 1 (Ito) shows:
A method for designing an integrated circuit layout, comprising: Ito [0038] teaches an ECAD tool that selects standard cells from a library and places and routes them to create the physical design, which is the claimed designing of an integrated circuit layout, because the layout is generated by mapping the circuit onto library standard cells.
generating an analog standard cell library, comprising: creating a target analog standard cell that is included in the analog standard cell library and does not violate layout rules of digital standard cells; and Ito [0071] teaches generating stem cell (analog standard cell) libraries whose cells conform to digital standard cell characteristics and do not violate the design rules when placed or abutted with other cells, thereby providing an analog standard cell library whose cells do not violate the layout rules of digital standard cells.
designing the integrated circuit layout by using at least the analog standard cell library. Ito [0072] teaches an ECAD physical design flow that uses the library of analog standard cells to lay out the physical design of the SoC, which meets designing the integrated circuit layout by using the library.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 - 6 are rejected under 35 U.S.C. 103 as being unpatentable over US20190211475A1 (Ito) in view of US20210224459A1 (Lu).
In regards to claim 2 (Ito) does not show: creating an analog standard cell through modifying a layout of a digital standard cell included in a digital standard cell library; wherein the target analog standard cell is derived from the analog standard cell;
Lu teaches creating an analog standard cell through modifying a layout of a digital standard cell included in a digital standard cell library; wherein the target analog standard cell is derived from the analog standard cell; Lu [0026] teaches forming an analog standard cell from a CMOS transistor pair in which one transistor is configured as a dummy (e.g., a single NMOS with a dummy PMOS), which meets deriving the analog standard cell by modifying the layout of a digital (CMOS/inverter-type) standard cell, because the analog cell reuses the same complementary transistor structure as the digital cell.
It would have been obvious before the effective filing date to combine Ito and Lu to derive the analog standard cell from a digital standard cell, with a reasonable expectation of success as both address analog cells compatible with digital layout rules.
In regards to claim 3 (Ito) does not show: laying a passive component above or below the analog standard cell to create the target analog standard cell;
Lu teaches laying a passive component above or below the analog standard cell to create the target analog standard cell; Lu [0044] teaches implementing a passive component, namely a High-R poly resistor or a MOM capacitor, within the standard cell boundary above the transistor active area, which meets laying a passive component above or below the cell.
It would have been obvious before the effective filing date to combine Ito and Lu to add a passive component to the standard cell, with a reasonable expectation of success as both address analog standard cell layout.
In regards to claim 4 (Ito) does not show: wherein the passive component is one of a resistor, a capacitor, and an inductor;
Lu teaches wherein the passive component is one of a resistor, a capacitor, and an inductor; Lu [0044] teaches implementing a passive component, namely a High-R poly resistor or a MOM capacitor, within the standard cell boundary above the transistor active area, which meets laying a passive component above or below the cell.
It would have been obvious before the effective filing date to combine Ito and Lu to add a passive component to the standard cell, with a reasonable expectation of success as both address analog standard cell layout.
In regards to claim 5 (Ito) shows the method according to claim 2:
wherein the digital standard cell library is in compliance with FinFET technology. Ito [0074] teaches that the standard cell characteristics apply to FinFET technology, so the digital standard cell library is in compliance with FinFET technology.
In regards to claim 6 (Ito) shows the method according to claim 2:
wherein the integrated circuit layout comprises the target analog standard cell selected from the analog standard cell library and one digital standard cell selected from the digital standard cell library that abut each other. Ito [0077] teaches that each analog cell is fully interoperable with digital cells and can be placed directly next to a digital cell without a DRC error, which meets the analog/mixed-signal cell and a digital cell abutting each other.
Claims 7, 8, 11, 12, 15 - 19, and 21 - 23 are rejected under 35 U.S.C. 103 as being unpatentable over US20190211475A1 (Ito) in view of US20190237589A1 (Marzaki).
In regards to claim 7 (Ito) shows:
A method for designing an integrated circuit layout, comprising: Ito [0038] teaches an ECAD tool that selects standard cells from a library and places and routes them to create the physical design, which is the claimed designing of an integrated circuit layout, because the layout is generated by mapping the circuit onto library standard cells.
generating a mixed-signal standard cell library, comprising: Ito [0057] teaches that for a mixed-signal design the standard cell library comprises both digital and analog standard cells, which meets generating a mixed-signal standard cell library because the same rule-compliant library supports mixed-signal circuitry.
designing the integrated circuit layout by using at least the mixed-signal standard cell library. Ito [0072] teaches an ECAD physical design flow that uses the library of analog standard cells to lay out the physical design of the SoC, which meets designing the integrated circuit layout by using the library.
Ito differs from the claimed invention in that it does not explicitly disclose creating a target mixed-signal standard cell that is included in the mixed-signal standard cell library and does not violate layout rules of digital standard cells.
Marzaki teaches creating a target mixed-signal standard cell that is included in the mixed-signal standard cell library and does not violate layout rules of digital standard cells; Marzaki [0106] teaches a standard cell that keeps its logic (digital) function while a capacitor is added to it, yielding a single cell having both a digital and an analog function without enlarging its footprint, which meets creating a mixed-signal standard cell by modifying a digital standard cell without violating its layout rules.
It would have been obvious before the effective filing date to combine Ito and Marzaki to form a mixed-signal cell having both a logic and an analog function, with a reasonable expectation of success as both address standard cells that integrate an added function.
In regards to claim 8 (Ito) does not show: creating a mixed-signal standard cell through modifying a layout of a digital standard cell included in a digital standard cell library; wherein the target mixed-signal standard cell is derived from the mixed-signal standard cell;
Marzaki teaches creating a mixed-signal standard cell through modifying a layout of a digital standard cell included in a digital standard cell library; wherein the target mixed-signal standard cell is derived from the mixed-signal standard cell; Marzaki [0106] teaches a standard cell that keeps its logic (digital) function while a capacitor is added to it, yielding a single cell having both a digital and an analog function without enlarging its footprint, which meets creating a mixed-signal standard cell by modifying a digital standard cell without violating its layout rules.
It would have been obvious before the effective filing date to combine Ito and Marzaki to form a mixed-signal cell having both a logic and an analog function, with a reasonable expectation of success as both address standard cells that integrate an added function.
In regards to claim 11 (Ito) shows the method according to claim 8:
wherein the digital standard cell library is in compliance with FinFET technology. Ito [0074] teaches that the standard cell characteristics apply to FinFET technology, so the digital standard cell library is in compliance with FinFET technology.
In regards to claim 12 (Ito) shows the method according to claim 8:
wherein the integrated circuit layout comprises the target mixed-signal standard cell selected from the mixed-signal standard cell library and one digital standard cell selected from the digital standard cell library that abut each other. Ito [0077] teaches that each analog cell is fully interoperable with digital cells and can be placed directly next to a digital cell without a DRC error, which meets the analog/mixed-signal cell and a digital cell abutting each other.
In regards to claim 15 (Ito) shows:
A method for designing an integrated circuit layout, comprising: Ito [0038] teaches an ECAD tool that selects standard cells from a library and places and routes them to create the physical design, which is the claimed designing of an integrated circuit layout, because the layout is generated by mapping the circuit onto library standard cells.
generating a mixed-signal standard cell library, comprising: Ito [0057] teaches that for a mixed-signal design the standard cell library comprises both digital and analog standard cells, which meets generating a mixed-signal standard cell library because the same rule-compliant library supports mixed-signal circuitry.
designing the integrated circuit layout by using at least the mixed-signal standard cell library. Ito [0072] teaches an ECAD physical design flow that uses the library of analog standard cells to lay out the physical design of the SoC, which meets designing the integrated circuit layout by using the library.
Ito differs from the claimed invention in that it does not explicitly disclose creating a mixed-signal standard cell included in the mixed-signal standard cell library through laying a passive component above or below a digital standard cell included in a digital standard cell library.
Marzaki teaches creating a mixed-signal standard cell included in the mixed-signal standard cell library through laying a passive component above or below a digital standard cell included in a digital standard cell library; Marzaki [0106] teaches a standard cell that keeps its logic (digital) function while a capacitor is added to it, yielding a single cell having both a digital and an analog function without enlarging its footprint, which meets creating a mixed-signal standard cell by modifying a digital standard cell without violating its layout rules.
It would have been obvious before the effective filing date to combine Ito and Marzaki to add a passive component to a digital standard cell, with a reasonable expectation of success as both address standard cells that integrate a passive component.
In regards to claim 16 (Ito) shows the method according to claim 15:
wherein the digital standard cell library is in compliance with FinFET technology. Ito [0074] teaches that the standard cell characteristics apply to FinFET technology, so the digital standard cell library is in compliance with FinFET technology.
In regards to claim 17 (Ito) shows the method according to claim 15:
wherein the integrated circuit layout comprises the mixed-signal standard cell selected from the analog standard cell library and one digital standard cell selected from the digital standard cell library that abut each other. Ito [0077] teaches that each analog cell is fully interoperable with digital cells and can be placed directly next to a digital cell without a DRC error, which meets the analog/mixed-signal cell and a digital cell abutting each other.
In regards to claim 18 (Ito) does not show: wherein the passive component is one of a resistor, a capacitor, and an inductor;
Marzaki teaches wherein the passive component is one of a resistor, a capacitor, and an inductor; Marzaki [0050] teaches that the standard cell includes a capacitive element, which meets the passive component being a capacitor.
It would have been obvious before the effective filing date to combine Ito and Marzaki to add a passive component to a digital standard cell, with a reasonable expectation of success as both address standard cells that integrate a passive component.
In regards to claim 19 (Ito) shows:
A computer system comprising: Ito [0185] teaches a computing system having a processor and a memory and hard disk drive, which meets the claimed computer system with a processor and a storage device.
a storage device, arranged to store a program code, a digital standard cell library, an analog standard cell library, and a mixed-signal standard cell library, wherein the analog standard cell library and the mixed-signal standard cell library comprise at least one analog standard cell and at least one mixed-signal standard cell that do not violate layout rules of digital standard cells; and Ito [0057] teaches that for a mixed-signal design the standard cell library comprises both digital and analog standard cells, which meets generating a mixed-signal standard cell library because the same rule-compliant library supports mixed-signal circuitry.
a processor, arranged to load and execute the program code for designing an integrated circuit layout by using standard cells selected from at least one of the digital standard cell library, the analog standard cell library, and the mixed-signal standard cell library. Ito [0185] teaches the processor loading instructions from memory and executing them to perform the design operations, which meets a processor that loads and executes the program code to design the integrated circuit layout.
Ito differs from the claimed invention in that it does not explicitly disclose at least one mixed-signal standard cell that do not violate layout rules of digital standard cells.
Marzaki teaches at least one mixed-signal standard cell that do not violate layout rules of digital standard cells; Marzaki [0106] teaches a standard cell that keeps its logic (digital) function while a capacitor is added to it, yielding a single cell having both a digital and an analog function without enlarging its footprint, which meets creating a mixed-signal standard cell by modifying a digital standard cell without violating its layout rules.
It would have been obvious before the effective filing date to combine Ito and Marzaki to form a mixed-signal cell having both a logic and an analog function, with a reasonable expectation of success as both address standard cells that integrate an added function.
In regards to claim 21 (Ito) shows the computer system according to claim 19:
wherein the integrated circuit layout comprises one analog standard cell selected from the at least one analog standard cell included in the analog standard cell library and one digital standard cell selected from the digital standard cell library that abut each other. Ito [0077] teaches that each analog cell is fully interoperable with digital cells and can be placed directly next to a digital cell without a DRC error, which meets the analog/mixed-signal cell and a digital cell abutting each other.
In regards to claim 22 (Ito) shows the computer system according to claim 19:
wherein the integrated circuit layout comprises one mixed-signal standard cell selected from the at least one mixed-signal standard cell included in the mixed-signal standard cell library and one digital standard cell selected from the digital standard cell library that abut each other. Ito [0083] teaches that the analog cells abut each other and abut digital cells to construct the layout, which meets the claimed cells abutting each other.
In regards to claim 23 (Ito) shows the computer system according to claim 19:
wherein the integrated circuit layout comprises one analog standard cell selected from the at least one analog standard cell included in the analog standard cell library and one mixed-signal standard cell selected from the at least one mixed-signal standard cell included in the mixed-signal standard cell library that abut each other. Ito [0083] teaches that the analog cells abut each other and abut digital cells to construct the layout, which meets the claimed cells abutting each other.
Claims 9, 10, 13, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over US20190211475A1 (Ito) in view of US20190237589A1 (Marzaki) and further in view of US20210224459A1 (Lu).
In regards to claim 9 (Ito modified by Marzaki) does not show: laying a passive component above or below the mixed-signal standard cell to create the target mixed-signal standard cell;
Lu teaches laying a passive component above or below the mixed-signal standard cell to create the target mixed-signal standard cell; Lu [0044] teaches implementing a passive component, namely a High-R poly resistor or a MOM capacitor, within the standard cell boundary above the transistor active area, which meets laying a passive component above or below the cell.
It would have been obvious before the effective filing date to further combine Ito and Marzaki with Lu to add a passive component to the standard cell, with a reasonable expectation of success as all address analog and mixed-signal cell layout.
In regards to claim 10 (Ito modified by Marzaki) does not show: wherein the passive component is one of a resistor, a capacitor, and an inductor;
Lu teaches wherein the passive component is one of a resistor, a capacitor, and an inductor; Lu [0044] teaches implementing a passive component, namely a High-R poly resistor or a MOM capacitor, within the standard cell boundary above the transistor active area, which meets laying a passive component above or below the cell.
It would have been obvious before the effective filing date to further combine Ito and Marzaki with Lu to add a passive component to the standard cell, with a reasonable expectation of success as all address analog and mixed-signal cell layout.
In regards to claim 13 (Ito modified by Marzaki) does not show: modifying the layout of the digital standard cell to create an analog standard cell; and laying a passive component above or below the analog standard cell to create the mixed-signal standard cell;
Lu teaches modifying the layout of the digital standard cell to create an analog standard cell; and laying a passive component above or below the analog standard cell to create the mixed-signal standard cell; Lu [0026] teaches forming an analog standard cell from a CMOS transistor pair in which one transistor is configured as a dummy (e.g., a single NMOS with a dummy PMOS), which meets deriving the analog standard cell by modifying the layout of a digital (CMOS/inverter-type) standard cell, because the analog cell reuses the same complementary transistor structure as the digital cell. Lu [0044] teaches implementing a passive component, namely a High-R poly resistor or a MOM capacitor, within the standard cell boundary above the transistor active area, which meets laying a passive component above or below the cell.
It would have been obvious before the effective filing date to further combine Ito and Marzaki with Lu to derive an analog cell from a digital cell and add a passive component, with a reasonable expectation of success as all address analog and mixed-signal cell layout.
In regards to claim 14 (Ito modified by Marzaki) does not show: wherein the passive component is one of a resistor, a capacitor, and an inductor;
Lu teaches wherein the passive component is one of a resistor, a capacitor, and an inductor; Lu [0044] teaches implementing a passive component, namely a High-R poly resistor or a MOM capacitor, within the standard cell boundary above the transistor active area, which meets laying a passive component above or below the cell.
It would have been obvious before the effective filing date to further combine Ito and Marzaki with Lu to derive an analog cell from a digital cell and add a passive component, with a reasonable expectation of success as all address analog and mixed-signal cell layout.
In regards to claim 20 (Ito modified by Marzaki) does not show: wherein each of the at least one analog standard cell and the at least one mixed-signal standard cell is derived from a digital standard cell included in the digital standard cell library;
Lu teaches wherein each of the at least one analog standard cell and the at least one mixed-signal standard cell is derived from a digital standard cell included in the digital standard cell library; Lu [0026] teaches forming an analog standard cell from a CMOS transistor pair in which one transistor is configured as a dummy (e.g., a single NMOS with a dummy PMOS), which meets deriving the analog standard cell by modifying the layout of a digital (CMOS/inverter-type) standard cell, because the analog cell reuses the same complementary transistor structure as the digital cell.
It would have been obvious before the effective filing date to further combine Ito and Marzaki with Lu to derive each cell from a digital standard cell, with a reasonable expectation of success as all address cells compatible with digital layout rules.
Conclusion
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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