DETAILED ACTION
Claims 1 and 5 are amended. Claims 2 and 6-10 are cancelled. Claims 1 and 3-5 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Examiner’s Notes
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Response to Amendment
Amendments to Fig. 26-29 are fully considered and are satisfactory to overcome the objections directed to the drawings in the previous Office Action.
Amendments to claims 1 and 5 are fully considered and are satisfactory to overcome the rejections under 35 USC §101 directed to claims 1 and 3-5 in the previous Office Action.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“an accelerator configured to simultaneously execute” in claim 1.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 5 recites a method comprising “simultaneously executing, by an accelerator, multiple programs by executing multiple intermediate representations according to an execution order” as the first method step, “converting the multiple programs to be simultaneously executed by the accelerator into the intermediate representations” as the second method step, and “determining the execution order of the multiple intermediate representations” as the third method step. However, the original disclosure does not provide such an arrangement of method steps where “execution of the intermediate representations according to an execution order” happens before “converting programs into intermediate representations“ and “determining an execution order”.
In particular, Fig. 18 discloses a method with intermediate representation (IR) generation steps S102, S104; follow by execution order determination steps S105, S106, and then an execution of IR step S107. However, the original disclosure does not describe performing step S107 prior to steps S102, S104, S105, S106.
As such, the order of the method steps in claim 5 presents subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites a method comprising “simultaneously executing, by an accelerator, multiple programs by executing multiple intermediate representations according to an execution order” as the first step, “converting the multiple programs to be simultaneously executed by the accelerator into the intermediate representations” as the second step, and “determining the execution order of the multiple intermediate representations” as the third step. The ordering of these steps renders the claim indefinite.
More specifically, the second step indicates multiple programs are “to be executed” and are not in the form of “intermediate representations” prior to this “converting” step which converts the multiple programs into intermediate representations.
Furthermore, the third step determines “execution order” after the converting step indicating that the execution order is not determined prior to this step.
However, the first step indicates “multiple programs” are already “executing” and they are already in the form of “intermediate representations” and the “execution order” is already known prior to the second and third steps.
As such, it is not clear how the first step can be performed before the second and third steps are performed.
For the following analysis, the Examiner will consider the second and third steps as the first and second steps of the method, respectively, and the first step as the last step of the method in view of the method shown in Fig. 18.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (“CASE: A Compiler-Assisted SchEduling Framework for Multi-GPU Systems”; 28 March 2022; hereinafter “Chen”).
With respect to claim 1, Chen teaches: A program control device (see e.g. page 24, column 2, paragraph 3: “servers: Chameleon… Chameleon node”) comprising:
an accelerator (see e.g. page 24, column 2, paragraph 4: “multi-GPU devices”) configured to simultaneously execute multiple programs (see e.g. page 20, Fig. 2: “App 1”, “App 2”, “App 3”…“App k”; page 18, column 2, paragraph 2: “scheduling framework of a multi-GPU system among uncooperative applications”; and page 20, column 1, paragraph 1: “On a multi-GPU system, straight-forward device mapping is the widely utilized method to allocate GPU devices among applications”) by executing multiple intermediate representations (see e.g. page 20, column 2, paragraph 3: “LLVM IR of applications”; and page 21, Fig. 4: “kernel launch in LLVM IR for VecAdd”) according to an execution order (see e.g. page 23, column 1, paragraph 1: “A user-level scheduler is deployed to place GPU tasks on appropriate devices based on their resource requirements (such as memory, CUDA cores, shared memory and execution time of a kernel)”);
a memory configured to store instructions (see e.g. page 24, column 2, paragraph 3: “128GB DRAM”); and
a processor configured to execute the instructions to (see e.g. page 24, column 2, paragraph 3: “an Intel Xeon E5-2670 CPU”):
convert the multiple programs to be simultaneously executed by the accelerator into the intermediate representations (see e.g. page 20, column 2, paragraph 3: “LLVM IR of applications”) indicating computation operations to be executed by programs (see e.g. page 20, Fig. 2: “Compiler Pass” and column 2, paragraph 3: “Task Construction. CASE leverages a compiler pass, coupled with the lazy runtime, to construct GPU tasks and gather their resource requirements. It works on the LLVM IR of applications… CASE builds GPU tasks by searching for kernel launches and related GPU operations leveraging the def-use chain information provided by the compiler. It first searches for kernel launches. In LLVM IR, they are heuristically implied by calls to _cudaPushCall Configuration, followed by calls to host stub functions of kernels”) and memory information indicating an amount of memory required by data used in the computation operations, respectively (see e.g. page 20, column 2, paragraph 3: “construct GPU tasks and gather their resource requirements”; and from page 21, column 2, paragraph 3 to page 22, column 1, paragraph 1: “for a GPUTask, its memory and computing resource requirements are analyzed by examining every memory allocation operation (cudaMalloc) and kernel launch operation (e.g. _cudaPushCallConfiguration) inside the task. All of the analyzed information is presented in the form of symbols… It summarizes memory sizes to get total memory requirements and utilizes the max grid and block dimensions as computing resources”); and
determine the execution order of the multiple intermediate representations (see e.g. page 20, Fig. 2: “Scheduler”; page 23, column 1, paragraph 1: “A user-level scheduler is deployed to place GPU tasks on appropriate devices based on their resource requirements (such as memory, CUDA cores, shared memory and execution time of a kernel)”; and page 21, column 2, paragraph 2: “a process executing two successive GPU kernels, 𝑘1 and 𝑘2, where the output of 𝑘1 (say, array C) is an input to 𝑘2… schedules these two kernel launches on the same device by packing them into one GPU task”) so that an amount of memory usage used by the accelerator when the accelerator executes the multiple programs simultaneously is below a threshold value of the memory (see e.g. page 20, column 2, paragraph 3: “a compiler pass, coupled with the lazy runtime, to construct GPU tasks and gather their resource requirements”; page 22, column 2, paragraph 1: “maximum heap memory size used by dynamic memory allocations inside a GPU is either statically bound to a CUDA task or dynamically intercepted and bound by the lazy runtime by analyzing the call to cudaDeviceSetLimit”; and page 23, column 1, paragraph 1: “A user-level scheduler is deployed to place GPU tasks on appropriate devices based on their resource requirements (such as memory”) based on the converted multiple intermediate representations and multiple memory information (see e.g. page 23, column 1, paragraph 1: “aforementioned compiler pass will automatically insert it at the beginning of each GPU task, and feed it with appropriate parameters, which contain the details about the resources required by the task, including the number of blocks, the threads per block, the total memory size”).
With respect to claim 3, Chen teaches: The program control device according to claim 1, wherein the processor is further configured to execute the instructions to:
include in the multiple intermediate representations a process of saving data used in the computation operations to memory (see e.g. page 21, Fig. 3: “initialize device memory”, “cudaMemcpy(dA, A, N, cudaMemcpyHostToDevice)”, “cudaMemcpy(dB, B, N, cudaMemcpyHostToDevice)” and “retrieve the result”, “cudaMemcpy(C, dC, N, cudaMemcpyDeviceToHost)”) used by a computing device other than the accelerator (see e.g. page 21, Fig. 3: “main is sequential code running on CPU”).
With respect to claim 4, Chen teaches: The program control device according to claim 1, wherein
the memory information includes a range of the computation operations (see e.g. page 21, Fig. 4) in which data is used (see e.g. page 20, column 2, paragraph 1: “constructs GPU tasks and instruments applications with one probe per task. At runtime, the probes convey tasks’ resource requirements to the scheduler before they execute”; and page 21, Fig. 4 and column 2, paragraph 1: “compiler pass identifies involved GPU memory objects, which are pointer variables used by cudaMalloc calls, by walking backward up the def-use chain of each parameter of the kernel’s host-side function, until it meets a terminating instruction, e.g. alloca.As an example, in Figure 4, the pass will visit d_A via a, and determine that d_A represents a GPU memory object since it is used in a call to cudaMalloc. Finally, the related preamble operations (e.g. cudaMalloc, cudaMemcpy) and epilogue operations (e.g. cudaFree) can be easily identified based on the def-use chain of pointers of memory objects, since they are taken as parameters to the calls of these runtime APIs”).
With respect to claim 5: Claim 5 is directed to a program control method corresponding to the active functions implemented by the program control device recited in claim 1; please see the rejection directed claim 1 above which also cover the limitations recited in claim 5.
Response to Arguments
Applicant's arguments filed 06/08/2026 have been fully considered but they are not persuasive. In detail:
(i) Regarding claim 1, Applicants argue that Chen fails to teach the limitation “determine the execution order of the multiple intermediate representations so that an amount of memory usage used by the accelerator” as recited (Remarks, pages 6-9).
However, note that Chen explicitly discloses a GPU which is an accelerator. Specifically, Chen discloses allocating GPU devices to applications for executing GPU tasks (see e.g. page 20, column 1, paragraph 1: “On a multi-GPU system, straight-forward device mapping is the widely utilized method to allocate GPU devices among applications”).
Chen further discloses a scheduler that places GPU tasks (i.e. accelerator tasks) in an order for execution on GPU devices (i.e. accelerators) based on the tasks’ resource requirements for executing on the GPU devices, including memory requirements (see e.g. page 23, column 1, paragraph 1: “A user-level scheduler is deployed to place GPU tasks on appropriate devices based on their resource requirements (such as memory, CUDA cores, shared memory and execution time of a kernel)”).
For example, two successive GPU kernels, k1 and k2, are ordered for execution on the same GPU device (i.e. an accelerator) by the scheduler (see e.g. page 21, column 2, paragraph 2: “a process executing two successive GPU kernels, 𝑘1 and 𝑘2, where the output of 𝑘1 (say, array C) is an input to 𝑘2… schedules these two kernel launches on the same device by packing them into one GPU task”).
That is, Chen discloses a scheduler that determines an execution order of GPU tasks based on amount of memory requirements to execute the tasks on the GPUs.
Therefore, Chen teaches the limitation “determine the execution order of the multiple intermediate representations so that an amount of memory usage used by the accelerator” as recited in claim 1. For more details, please see the corresponding rejection directed to claim 1 above.
(ii) Regarding claim 3, Applicant argues that Chen fails to disclose “saving data used in the computation operations to memory used by a computing device other than the accelerator” (see Remarks, page 9).
However, note that Chen discloses executing a main code on the CPU of the host device (i.e. a computing device other than the accelerator) including a cudaMemcpyDeviceToHost operation to copy results from the GPU memory (i.e. the accelerator) to the host device memory (i.e. a computer device other than the accelerator).
Therefore, Chen teaches the limitation “saving data used in the computation operations to memory used by a computing device other than the accelerator” as recited in claim 3. For more details, please see the corresponding rejection directed to claim 3 above.
CONCLUSION
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Papakipos et al. (US 2007/0294696 A1) discloses a runtime system that receives an intermediate representation in an executable application and performs loop transformations for the intermediate representation (see paragraph 447).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Umut Onat whose telephone number is (571)270-1735. The examiner can normally be reached M-Th 9:00-7:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kevin L Young can be reached at (571) 270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/UMUT ONAT/Primary Examiner, Art Unit 2194
Prosecution Insights