DETAILED ACTION
This Office Action is in response to the application filed on 29 November 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, 6, 8-17, 21-24, and 27-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kinsley (US 2021/0327855 A1; hereinafter Kinsley), in view of Chen et al. (US 2022/0310470 A1; hereinafter Chen), in view of Bai et al. (US 6,326,700 B1; hereinafter Bai).
In regards to claim 1, Kinsley teaches, e.g. in fig. 1A, a method, comprising:
coupling a surface of a first semiconductor component (106a-106d) with a first portion of a surface of a second semiconductor component (104), the first semiconductor component comprising one or more memory arrays ([0019]: DRAM, SRAM, flash memory, etc.), the second semiconductor component comprising control circuitry for accessing the one or more memory arrays ([0019]: high-speed logic die that provides memory control), and the coupling the surface of the first semiconductor component with the first portion of the surface of the second semiconductor component forming a communicative coupling between the one or more memory arrays and the control circuitry (fig. 1A: communicative coupling between (124) and (132)).
Kinsley appears to be silent as to, but does not preclude, the limitations of coupling a surface of a third semiconductor component with a second portion of the surface of the second semiconductor component, without forming a communicative coupling between the third semiconductor component and the second semiconductor component. Chen teaches, e.g. in fig. 15, the limitations of coupling a surface of a third semiconductor component ([0037]: (94) is formed of materials such as silicon) with a second portion of the surface (e.g. surface of (80) that does not have electrical connections) of the second semiconductor component, without forming a communicative coupling between the third semiconductor component and the second semiconductor component (e.g. there is no electrical signal connection between (80) and (94)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kinsley with the aforementioned limitations taught by Chen to optimize a device for smaller semiconductor packages (Chen [0002]).
The combination of Kinsley and Chen appears to be silent as to, but does not preclude, the limitations of fusing a first material at the surface of the third semiconductor component with a second material at the second portion of the surface of the second semiconductor component. Bai teaches the limitations fusing a first material at the surface of the third semiconductor component with a second material at the second portion of the surface of the second semiconductor component (col. 3/lns. 35-45). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitation taught by the combination of Kinsley and Chen with the aforementioned limitations taught by Bai to have a low-profile semiconductor package (Bai col. 2/lns. 44-46).
In regards to claim 2, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 1. Bai further teaches the limitations wherein coupling the surface of the first semiconductor component with the first portion of the surface of the second semiconductor component comprises: fusing one or more portions a first electrically conductive material at the surface of the first semiconductor component with one or more portions of a second electrically conductive material at the first portion of the surface of the second semiconductor component (col. 3/lns. 35-45). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitation taught by the combination of Kinsley and Chen with the aforementioned limitations taught by Bai to have a low-profile semiconductor package (Bai col. 2/lns. 44-46).
In regards to claim 5, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 1. Chen further teaches the limitations further comprising: forming the first material at the surface of the third semiconductor component based at least in part on oxidizing, nitriding, or carbonizing a semiconductor portion of the third semiconductor component, or a combination thereof [0030]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kinsley with the aforementioned limitations taught by Chen to optimize a device for smaller semiconductor packages (Chen [0002]).
In regards to claim 6, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 1. Chen further teaches the limitations further comprising: forming the first material at the surface of the third semiconductor component based at least in part on depositing an oxide material, nitride material, carbide material, or a combination thereof on the surface of the third semiconductor component [0030]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kinsley with the aforementioned limitations taught by Chen to optimize a device for smaller semiconductor packages (Chen [0002]).
In regards to claim 8, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 1. Kinsley further teaches, e.g. in fig. 1A, the limitations further comprising: depositing, after coupling the third semiconductor component (116/118) [0016] with the second portion of the surface of the second semiconductor component (104) [0017], the first semiconductor component (106a-106d) [0018] in an opening through the third semiconductor component (e.g. between elements (118/128a/b)); and coupling the surface of the first semiconductor component with the first portion of the surface of the second semiconductor component with the first semiconductor component in the opening (fig. 1B).
In regards to claim 9, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 1. Kinsley further teaches, e.g. in fig. 1A, the limitations wherein coupling the surface of the third semiconductor component with the second portion of the surface of the second semiconductor component comprises: depositing the third semiconductor component between a set of multiple first semiconductor components after coupling the set of multiple first semiconductor components with the second semiconductor component (figs. 1A-1B: e.g. (114) is deposited after (106a-106b) are coupled).
In regards to claim 10, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 1. Kinsley further teaches the limitations wherein the first semiconductor component comprises: a first semiconductor die (106a-106d) [0019] including a first subset (fig. 1A: e.g. one of (106a-106d)) of the one or more memory arrays; and a second semiconductor die (104) [0017], coupled with the first semiconductor die, including a second subset (fig. 1A: e.g. another one of (106a-106d)) of the one or more memory arrays.
In regards to claim 11, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 1. Kinsley further teaches the limitations further comprising: forming a semiconductor assembly comprising the first semiconductor component (106a-106d) [0019], a portion of the second semiconductor component (104) [0017], and a portion of the third semiconductor component based at least in part on a separation through the second semiconductor component and the third semiconductor component ([0016]; fig. 1A: (116/118) is spaced apart from (104)).
In regards to claim 12, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 1. Kinsley further teaches, e.g. in fig. 1A, the limitations wherein the second semiconductor component (104) comprises a semiconductor wafer configured for coupling with a plurality of first semiconductor components (106a-106d) [0014].
In regards to claim 13, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 1. Chen further teaches the limitations wherein the third semiconductor component is formed without circuitry ([0037] - heat dissipation die). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kinsley with the aforementioned limitations taught by Chen to optimize a device for smaller semiconductor packages (Chen [0002])
In regards to claim 14, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 1. Kinsley further teaches the limitations wherein the first material is formed over a polycrystalline silicon portion of the third semiconductor component [0035].
In regards to claim 15, Kinsley teaches, e.g. in fig. 1A, an apparatus, comprising:
a first semiconductor component (106a-106d) including one or more memory arrays ([0019]: DRAM, SRAM, flash memory, etc.);
a second semiconductor component (104) including control circuitry for accessing the one or more memory arrays ([0019]: high-speed logic die that provides memory control), wherein a surface of the first semiconductor component and a first portion of a surface of the second semiconductor component are coupled with a communicative coupling between the one or more memory arrays and the control circuitry (fig. 1A: communicative coupling between (124) and (132)).
Kinsley appears to be silent as to, but does not preclude, the limitations of a third semiconductor component, wherein a surface of the third semiconductor component and a second portion of the surface of the second semiconductor component are coupled without a communicative coupling between the third semiconductor component and the second semiconductor component. Chen teaches the limitations of a third semiconductor component ([0037]: (94) is formed of materials such as silicon), wherein a surface of the third semiconductor component and a second portion of the surface of the second semiconductor component (e.g. surface of (80) that does not have electrical connections) are coupled without a communicative coupling between the third semiconductor component and the second semiconductor component (e.g. there is no electrical signal connection between (80) and (94)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kinsley with the aforementioned limitations taught by Chen to optimize a device for smaller semiconductor packages (Chen [0002]).
The combination of Kinsley and Chen appears to be silent as to, but does not preclude, the limitations of the coupling of the surface of the third semiconductor component and the second portion of the surface of the second semiconductor component based at least in part on a fusion between a first material at the surface of the third semiconductor component and a second material at the second portion of the surface of the second semiconductor component. Bai teaches the limitations the coupling of the surface of the third semiconductor component and the second portion of the surface of the second semiconductor component based at least in part on a fusion between a first material at the surface of the third semiconductor component and a second material at the second portion of the surface of the second semiconductor component (col. 3/lns. 35-45). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitation taught by the combination of Kinsley and Chen with the aforementioned limitations taught by Bai to have a low-profile semiconductor package (Bai col. 2/lns. 44-46).
In regards to claim 16, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 15. Kinsley further teaches the limitations wherein the first semiconductor component comprises: a first semiconductor die (106a-106d) [0019] including a first subset (fig. 1A: e.g. one of (106a-106d)) of the one or more memory arrays; and a second semiconductor die (104) [0017], coupled between the first semiconductor die and the second semiconductor component, including a second subset (fig. 1A: e.g. another one of (106a-106d)) of the one or more memory arrays.
In regards to claim 17, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 15. Bai further teaches the limitations wherein the coupling of the first portion of the surface of the second semiconductor component with the surface of the first semiconductor component comprises a fusion between a first electrically conductive material at the surface of the first semiconductor component and a second electrically conductive material at the first portion of the surface of the second semiconductor component (col. 3/lns. 35-45). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitation taught by the combination of Kinsley and Chen with the aforementioned limitations taught by Bai to have a low-profile semiconductor package (Bai col. 2/lns. 44-46).
In regards to claim 21, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 15. Chen further teaches the limitations wherein the third semiconductor component is formed without circuitry ([0037] - heat dissipation die). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kinsley with the aforementioned limitations taught by Chen to optimize a device for smaller semiconductor packages (Chen [0002]).
In regards to claim 22, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 15. Kinsley further teaches the limitations wherein the first material is formed over a polycrystalline silicon portion of the third semiconductor component [0035].
In regards to claim 23, Kinsley teaches, e.g. in fig. 1A, an apparatus formed by a process comprising:
coupling a surface of a first semiconductor component (106a-106d) with a first portion of a surface of a second semiconductor component (104), the first semiconductor component comprising one or more memory arrays ([0019]: DRAM, SRAM, flash memory, etc.), the second semiconductor component comprising control circuitry for accessing the one or more memory arrays ([0019]: high-speed logic die that provides memory control), and the coupling of the surface of the first semiconductor component with the first portion of the surface of the second semiconductor component forming a communicative coupling between the one or more memory arrays and the control circuitry (fig. 1A: communicative coupling between (124) and (132)).
Kinsley appears to be silent as to, but does not preclude, the limitations of coupling a surface of a third semiconductor component with a second portion of the surface of the second semiconductor component, without forming a communicative coupling between the third semiconductor component and the second semiconductor component. Chen teaches the limitations of coupling a surface of a third semiconductor component ([0037]: (94) is formed of materials such as silicon) with a second portion of the surface (e.g. surface of (80) that does not have electrical connections) of the second semiconductor component, without forming a communicative coupling between the third semiconductor component and the second semiconductor component (e.g. there is no electrical signal connection between (80) and (94)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kinsley with the aforementioned limitations taught by Chen to optimize a device for smaller semiconductor packages (Chen [0002]).
The combination of Kinsley and Chen appears to be silent as to, but does not preclude, the limitations of fusing a first material at the surface of the third semiconductor component with a second material at the second portion of the surface of the second semiconductor component. Bai teaches the limitations of fusing a first material at the surface of the third semiconductor component with a second material at the second portion of the surface of the second semiconductor component (col. 3/lns. 35-45). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitation taught by the combination of Kinsley and Chen with the aforementioned limitations taught by Bai to have a low-profile semiconductor package (Bai col. 2/lns. 44-46).
In regards to claim 24, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 23. Bai further teaches the limitations comprising: coupling the surface of the first semiconductor component with the first portion of the surface of the second semiconductor component based at least in part on fusing one or more portions a first electrically conductive material at the surface of the first semiconductor component with one or more portions of a second electrically conductive material at the first portion of the surface of the second semiconductor component (col. 3/lns. 35-45). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitation taught by the combination of Kinsley and Chen with the aforementioned limitations taught by Bai to have a low-profile semiconductor package (Bai col. 2/lns. 44-46).
In regards to claim 27, Kinsley teaches, e.g. in fig. 1A, a method, comprising:
coupling a surface of a first semiconductor component (106a-106d) with a first portion of a surface of a second semiconductor component (104), the first semiconductor component comprising one or more memory arrays ([0019]: DRAM, SRAM, flash memory, etc.), the second semiconductor component comprising control circuitry for accessing the one or more memory arrays ([0019]: high-speed logic die that provides memory control), and the coupling the surface of the first semiconductor component with the first portion of the surface of the second semiconductor component forming a communicative coupling between the one or more memory arrays and the control circuitry (fig. 1A: communicative coupling between (124) and (132)).
Kinsley appears to be silent as to, but does not preclude, the limitations of coupling a surface of a third semiconductor component with a second portion of the surface of the second semiconductor component, without forming a communicative coupling between the third semiconductor component and the second semiconductor component. Chen teaches the limitations of coupling a surface of a third semiconductor component ([0037]: (94) is formed of materials such as silicon) with a second portion of the surface (e.g. surface of (80) that does not have electrical connections) of the second semiconductor component, without forming a communicative coupling between the third semiconductor component and the second semiconductor component (e.g. there is no electrical signal connection between (80) and (94)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kinsley with the aforementioned limitations taught by Chen to optimize a device for smaller semiconductor packages (Chen [0002]).
The combination of Kinsley and Chen appears to be silent as to, but does not preclude, the limitations of fusing a first dielectric material at the surface of the third semiconductor component with a second dielectric material at the second portion of the surface of the second semiconductor component. Bai teaches the limitations of fusing a first dielectric material at the surface of the third semiconductor component with a second dielectric material at the second portion of the surface of the second semiconductor component (col. 3/lns. 35-45). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitation taught by the combination of Kinsley and Chen with the aforementioned limitations taught by Bai to have a low-profile semiconductor package (Bai col. 2/lns. 44-46).
In regards to claim 28, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 27. Chen further teaches the limitations wherein the first dielectric material and the second dielectric material comprise an oxide of silicon, a nitride of silicon, a carbide of silicon, or a combination thereof [0030]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kinsley with the aforementioned limitations taught by Chen to optimize a device for smaller semiconductor packages (Chen [0002]).
In regards to claim 29, Kinsley teaches, e.g. in fig. 1A, an apparatus, comprising:
a first semiconductor component (106a-106d) including one or more memory arrays ([0019]: DRAM, SRAM, flash memory, etc.);
a second semiconductor component (104) including control circuitry for accessing the one or more memory arrays ([0019]: high-speed logic die that provides memory control), wherein a surface of the first semiconductor component and a first portion of a surface of the second semiconductor component are coupled with a communicative coupling between the one or more memory arrays and the control circuitry (fig. 1A: communicative coupling between (124) and (132)).
Kinsley appears to be silent as to, but does not preclude, the limitations of a third semiconductor component, wherein a surface of the third semiconductor component and a second portion of the surface of the second semiconductor component are coupled without a communicative coupling between the third semiconductor component and the second semiconductor component. Chen teaches, e.g. in fig. 15, the limitations of a third semiconductor component ([0037]: (94) is formed of materials such as silicon), wherein a surface of the third semiconductor component and a second portion of the surface of the second semiconductor component (e.g. surface of (80) that does not have electrical connections) are coupled without a communicative coupling between the third semiconductor component and the second semiconductor component (e.g. there is no electrical signal connection between (80) and (94)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kinsley with the aforementioned limitations taught by Chen to optimize a device for smaller semiconductor packages (Chen [0002]).
The combination of Kinsley and Chen appears to be silent as to, but does not preclude, the limitations of the coupling of the surface of the third semiconductor component with the second portion of the surface of the second semiconductor component based at least in part on a fusion between a first dielectric material at the surface of the third semiconductor component and a second dielectric material at the second portion of the surface of the second semiconductor component. Bai teaches the limitations of the coupling of the surface of the third semiconductor component with the second portion of the surface of the second semiconductor component based at least in part on a fusion between a first dielectric material at the surface of the third semiconductor component and a second dielectric material at the second portion of the surface of the second semiconductor component (col. 3/lns. 35-45). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitation taught by the combination of Kinsley and Chen with the aforementioned limitations taught by Bai to have a low-profile semiconductor package (Bai col. 2/lns. 44-46).
In regards to claim 30, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 29. Chen further teaches the limitations of wherein the first dielectric material and the second dielectric material comprise an oxide of silicon, a nitride of silicon, a carbide of silicon, or a combination thereof [0030]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Kinsley with the aforementioned limitations taught by Chen to optimize a device for smaller semiconductor packages (Chen [0002]).
Claim(s) 3, 4, 7, 18-20, 25, and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kinsley, Chen, and Bai as applied to claims 1, 2, 15, 17, and 24 above, and further in view of Heinrich et al. (US 2022/0046792 A1; hereinafter Heinrich).
In regards to claim 3, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 2. The combination of Kinsley, Chen, and Bai appears to be silent as to, but does not preclude, the limitations wherein coupling the surface of the first semiconductor component with the first portion of the surface of the second semiconductor component comprises: fusing one or more portions of a first dielectric material at the surface of the first semiconductor component with one or more portions of a second dielectric material at the first portion of the surface of the second semiconductor component. Heinrich teaches the limitations wherein coupling the surface of the first semiconductor component with the first portion of the surface of the second semiconductor component comprises: fusing one or more portions of a first dielectric material at the surface of the first semiconductor component with one or more portions of a second dielectric material at the first portion of the surface of the second semiconductor component ([0032] - bonded device with different discrete elements). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Kinsley, Chen, and Bai with the aforementioned limitations taught by Heinrich to have a bonded device with discrete sub-elements (Heinrich [0032]).
In regards to claim 4, the combination of Kinsley, Chen, Bai, and Heinrich teaches the limitations discussed above in addressing claim 3. Heinrich further teaches the limitations wherein at least a portion of the second material and at least a portion of the second dielectric material are contiguous at the surface of the second semiconductor component [0032]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Kinsley, Chen, and Bai with the aforementioned limitations taught by Heinrich to have a bonded device with discrete sub-elements (Heinrich [0032]).
In regards to claim 7, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 1. The combination of Kinsley, Chen, and Bai appears to be silent as to, but does not preclude, the limitations further comprising: forming a mold compound adjacent to the first semiconductor component, adjacent to the third semiconductor component, or between the first semiconductor component and the third semiconductor component, or a combination thereof. Heinrich teaches the limitations further comprising: forming a mold compound adjacent to the first semiconductor component, adjacent to the third semiconductor component, or between the first semiconductor component and the third semiconductor component, or a combination thereof ([0054]: mold compound to have electrical isolation). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Kinsley, Chen, and Bai with the aforementioned limitations taught by Heinrich to have a bonded device with discrete sub-elements (Heinrich [0032]).
In regards to claim 18, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 17. The combination of Kinsley, Chen, and Bai appears to be silent as to, but does not preclude, the limitations wherein the coupling of the first portion of the surface of the second semiconductor component with the surface of the first semiconductor component comprises a fusion between a first dielectric material at the surface of the first semiconductor component and a second dielectric material at the first portion of the surface of the second semiconductor component. Heinrich teaches the limitations wherein the coupling of the first portion of the surface of the second semiconductor component with the surface of the first semiconductor component comprises a fusion between a first dielectric material at the surface of the first semiconductor component and a second dielectric material at the first portion of the surface of the second semiconductor component [0032]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Kinsley, Chen, and Bai with the aforementioned limitations taught by Heinrich to have a bonded device with discrete sub-elements (Heinrich [0032]).
In regards to claim 19, the combination of Kinsley, Chen, Bai, and Heinrich teaches the limitations discussed above in addressing claim 18. Heinrich further teaches the limitations wherein at least a portion of the second material and at least a portion of the second dielectric material are contiguous at the surface of the second semiconductor component. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Kinsley, Chen, and Bai with the aforementioned limitations taught by Heinrich to have a bonded device with discrete sub-elements (Heinrich [0032]).
In regards to claim 20, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 15. The combination of Kinsley, Chen, and Bai appears to be silent as to, but does not preclude, the limitations further comprising: a mold compound adjacent to the first semiconductor component, adjacent to the third semiconductor component, or between the first semiconductor component and the third semiconductor component, or a combination thereof. Heinrich teaches the limitations further comprising: a mold compound adjacent to the first semiconductor component, adjacent to the third semiconductor component, or between the first semiconductor component and the third semiconductor component, or a combination thereof [0032]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Kinsley, Chen, and Bai with the aforementioned limitations taught by Heinrich to have a bonded device with discrete sub-elements (Heinrich [0032]).
In regards to claim 25, the combination of Kinsley, Chen, and Bai teaches the limitations discussed above in addressing claim 24. The combination of Kinsley, Chen, and Bai appears to be silent as to, but does not preclude, the limitations formed by the process comprising: coupling the surface of the first semiconductor component with the first portion of the surface of the second semiconductor component based at least in part on fusing one or more portions of a first dielectric material at the surface of the first semiconductor component with one or more portions of a second dielectric material at the first portion of the surface of the second semiconductor component. Heinrich teaches the limitations formed by the process comprising: coupling the surface of the first semiconductor component with the first portion of the surface of the second semiconductor component based at least in part on fusing one or more portions of a first dielectric material at the surface of the first semiconductor component with one or more portions of a second dielectric material at the first portion of the surface of the second semiconductor component [0032]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Kinsley, Chen, and Bai with the aforementioned limitations taught by Heinrich to have a bonded device with discrete sub-elements (Heinrich [0032]).
In regards to claim 26, the combination of Kinsley, Chen, Bai, and Heinrich teaches the limitations discussed above in addressing claim 25. Heinrich further teaches the limitations wherein at least a portion of the second material and at least a portion of the second dielectric material component are contiguous at the surface of the second semiconductor component [0032]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Kinsley, Chen, and Bai with the aforementioned limitations taught by Heinrich to have a bonded device with discrete sub-elements (Heinrich [0032]).
Conclusion
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812
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