DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 7, 9 and 11-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (“A Gate Driver with a Negative Turn Off Bias Voltage for GaN HEMTs” cited in the Information Disclosure Statement filed December 13, 2023, hereafter Zhou).
Claims 1 and 18: Zhou teaches a drive voltage generator (Figure 1) for driving a GaN high electron mobility transistor (GaN HEMT in Figure 1; Abstract), comprising:
a fixed input (Vcc) configured to receive a fixed voltage (12V);
an input (U);
a first capacitor (C2) connected to the input (via C1, D1, R1), a first circuit (Dz, D2) connected to the fixed input (via R2), and a first transistor (Q2) connected to the first capacitor and the first circuit (at the gate via C1, D1, R1); and
a second capacitor (C1) connected to the square wave input (via D1, R1), a second circuit (R2) connected the fixed input, and a second transistor (Q1) connected to the second capacitor and the second circuit (at the gate via D1, R1);
wherein the generator is configured to:
load the first capacitor (C2) by the first circuit with a portion of the fixed voltage when the input voltage is low (Vcc, R2 and Dz charge C2 as shown in Figure 4), and keep, by the first circuit, a gate-source voltage of the first transistor below a first threshold voltage of the first transistor (Q2 is off); and
add the high voltage to the portion of the fixed voltage of the first capacitor when the input voltage is high (Q2 is on as shown in Figure 3), and increase the gate-source voltage of the first transistor above the first threshold voltage (Q2 is on), so that the high voltage and the portion of the fixed voltage of the first capacitor is provided through the transistor as an output voltage of the drive voltage generator (to the GaN HEMT via Ron; Figure 3); and
wherein the generator is further configured to:
load the second capacitor (C1) by the second circuit (R2) with a portion of the high voltage (Vcc) when the input voltage is high (Figure 3), and keep, by the second circuit, a gate-source voltage of the second transistor below a second threshold voltage of the first transistor (Q1 is off); and
reduce by the input and the second circuit, the load of the second capacitor by a difference between the high voltage and the low voltage of the input so that the load of the second capacitor becomes a negative voltage when the input voltage is low (Figure 4 and Section II-B, “At the end of the first substage, Vgs equals to Vc1, which is also the magnitude of the negative bias Vn”), and increase the gate-source voltage of the second transistor above the second threshold voltage (Q1 is on), so that the negative voltage of the second capacitor is provided through the second transistor as an output voltage of the drive voltage generator (to GaN HEMT; Figure 4).
Zhou does not specifically teach a square wave input configured to receive a square wave voltage alternating between a high voltage and a low voltage. Zhou teaches an input configured to receive a voltage alternating between a high voltage and a low voltage (Figure 7 and Abstract “This paper rectifies these issues by proposing a negative turn-off bias generator with a new charge pump based approach which offers a stable negative turn-off voltage under different switching frequencies and duty cycles”), where the selection of a square wave input as the duty cycle (where a 50% duty cycle would be a square wave) would have been chosen to ensure an optimal performance of the circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a square wave input when employing the drive voltage generator of Zhou to maximize the overall performance of the circuit. Furthermore, such a provision of selecting a specific switching frequency or duty cycle involves only routine design expedient.
Examiner notes that claim 18 recites the limitations of claim 1 in method form and is rejected on the grounds above.
Claim 2: Zhou teaches the limitations of claim 1 above. Zhou does not specifically teach that the high voltage is 3.3V and the low voltage is 0V. However, the selection of a high voltage of 3.3V and a low voltage of 0V for the driver circuit would have been chosen to ensure an optimal performance of the circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select a high voltage of 3.3V and a low voltage of 0V when employing the driver circuit of Zhou to maximize the overall performance of the driver circuit. Furthermore, such a provision of selecting a specific voltage involves only routine design expedient.
Claim 3: Zhou further teaches that the first circuit further comprises a series connection of a regular diode and a Zener diode connected to the fixed voltage (Vcc is connected to Dz and D2 in series; Figure 1).
Claim 5: Zhou further teaches that the square wave voltage is provided by a microcontroller (Section II, U is the output block of the lower channel of isolated gate driver IC).
Claim 7: Zhou further teaches that the first circuit further comprises a series connection of a regular diode and a Zener diode connected to the fixed voltage (Vcc is connected to Dz and D2 in series; Figure 1 of Zhou).
Claim 9: Zhou further teaches that the square wave voltage is provided by a microcontroller (Section II, U is the output block of the lower channel of isolated gate driver IC).
Claims 11, 14 and 15: Zhou teaches the limitations of claims 2, 12 and 13. Zhou does not specifically teach that the output voltage is in a range of -1.5V to -3.3V, when the square wave voltage is low. However, the selection of an output voltage in a range of -1.5V to -3.3V, when the square wave voltage is low, would have been chosen to ensure an optimal performance of the circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select an output voltage in a range of -1.5V to -3.3V, when the square wave voltage is low, when employing the driver circuit of Zhou to maximize the overall performance of the driver circuit. Furthermore, such a provision of selecting a specific voltage involves only routine design expedient.
Claim 12: Zhou teaches the limitations of claim 2 above. Zhou does not specifically teach the output voltage is in a range from 4.5V to 6.6V, when the square wave voltage is high. However, the selection of an output voltage in a range from 4.5V to 6.6V, when the square wave voltage is high, would have been chosen to ensure an optimal performance of the circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select an output voltage in a range from 4.5V to 6.6V, when the square wave voltage is high, when employing the driver circuit of Zhou to maximize the overall performance of the driver circuit. Furthermore, such a provision of selecting a specific voltage involves only routine design expedient.
Claim 13: Zhou teaches the limitations of claim 12 above. Zhou does not specifically teach the output voltage is in a range from 5V to 6.6V. However, the selection of an output voltage is in a range from 5V to 6.6V would have been chosen to ensure an optimal performance of the circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select an output voltage is in a range from 5V to 6.6V when employing the driver circuit of Zhou to maximize the overall performance of the driver circuit. Furthermore, such a provision of selecting a specific voltage involves only routine design expedient.
Claim 16: Zhou teaches the limitations of claim 14 above. Zhou does not specifically teach the output voltage is in a range from -2V to -3V. However, the selection of an output voltage is in a range from -2V to -3V would have been chosen to ensure an optimal performance of the circuit. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select an output voltage is in a range from -2V to -3V when employing the driver circuit of Zhou to maximize the overall performance of the driver circuit. Furthermore, such a provision of selecting a specific voltage involves only routine design expedient.
Claim 17: Zhou teaches a GaN high electron mobility transistor unit (Figure 1; Abstract) comprising:
a GaN high electron mobility transistor (GaN HEMT); and
the drive voltage generator according to claim 1 (see above), wherein the drive voltage generator is connected to the GaN high electron mobility transistor (at the gate of GaN HEMT), and wherein the output voltage of the drive voltage generator is a supply voltage to the GaN high electron mobility transistor (Figure 1).
Claim(s) 6, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhou in view of Neubarth et al. (U.S. Patent 7,889,477, hereafter Neubarth).
Claims 6 and 10: Zhou teaches the limitations of claims 1 and 2 above. Zhou does not specifically teach the first and second transistors (Q1, Q2) are bipolar junction transistors.
Neubarth teaches that a bipolar junction transistor is an art-recognized equivalent circuit for a switching element (column 5 lines 20-30), and the gate-source voltage is a base-emitter voltage (inherent in the structure of a bipolar junction transistor). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the bipolar junction transistor as switching elements Q1 and Q2 of Zhou as an equivalent switch element.
Allowable Subject Matter
Claims 4 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the reasons set forth in the Non-Final Rejection dated September 5, 2025.
Response to Arguments
Applicant’s arguments filed December 5, 2025, with respect to the rejection(s) of claim(s) 1 and 18 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 U.S.C. 103 as described above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN J O'TOOLE whose telephone number is (571)270-1273. The examiner can normally be reached Monday - Friday, 9:00 am - 6:00pm.
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/C.J.O/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849
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