Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/29/2023, 01/22/2025, and 09/19/2025. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
NOTE: Per MPEP 804, a complete response to a nonstatutory double patenting (NSDP) is either a reply by Applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer. Such a showing or filing will not be held in abeyance.
4. Claims 15-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-4, 8 and 9 of U.S. Patent No. US 11,867,773 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the pending claims are anticipated by the claims of the patent as layout below.
Pending application 18522596 / 2040094310 claims 15-20
16888927 / 11,867,773 claims 1-4, 8 and 9
15. A circuit, comprising: a switched capacitor module configured to receive a positive differential input signal and a negative differential input signal, comprising a switching network, a first sampling capacitor, and a second sampling capacitor; an integrator having a positive input coupled to the first sampling capacitor, a negative input coupled to the second sampling capacitor, a positive output, and a negative output; a first feedback loop, comprising: a first switch coupled between the positive input and the negative output; a second switch coupled to the positive input a first feedback capacitor coupled between the second switch and the negative output; and a second feedback loop, comprising: a third switch coupled between the negative input and the positive output; a fourth switch coupled to the negative input; and a second feedback capacitor coupled between the fourth switch and the positive output.
1. A circuit, comprising: a switched capacitor module configured to receive a positive differential input signal and a negative differential input signal, comprising a switching network, a first sampling capacitor, and a second sampling capacitor; an integrator having a positive input coupled to the first sampling capacitor, a negative input coupled to the second sampling capacitor, a positive output, and a negative output; a first feedback loop, comprising: a first switch coupled between the positive input and the negative output; a second switch coupled to the positive input a first feedback capacitor coupled between the second switch and the negative output; a second feedback loop, comprising: a third switch coupled between the negative input and the positive output; a fourth switch coupled to the negative input; and a second feedback capacitor coupled between the fourth switch and the positive output; a fifth switch coupled between the first feedback capacitor and the negative output; a sixth switch configured to couple the second feedback capacitor to the positive output or to the positive input; a seventh switch coupled between the negative and positive outputs; an output buffer; an eighth switch coupled between the negative output and an input of the output buffer; and a ninth switch configured to couple the first feedback capacitor to an output of the output buffer or to a resistor, wherein the resistor is further coupled to the output of the output buffer.
16. The circuit of claim 15, wherein in a reset operating mode: the switching network disconnects the first and second sampling capacitors from the positive and negative differential input signals and couples the first and second sampling capacitors to each other; and the first, second, third, and fourth switches are closed.
2. The circuit of claim 1, wherein in a reset operating mode: the switching network disconnects the first and second sampling capacitors from the positive and negative differential input signals and couples the first and second sampling capacitors to each other; and the first, second, third, and fourth switches are closed.
17. The circuit of claim 15, wherein in a sampling operating mode: the first and third switches are closed; the second and fourth switches are open; and the switching network provides the positive differential input signal to the first sampling capacitor and the negative differential input signal to the second sampling capacitor and uncouples the first and second sampling capacitors from each other.
3. The circuit of claim 1, wherein in a sampling operating mode: the first and third switches are closed; the second and fourth switches are open; and the switching network provides the positive differential input signal to the first sampling capacitor and the negative differential input signal to the second sampling capacitor and uncouples the first and second sampling capacitors from each other.
18. The circuit of claim 15, wherein in an integrating operating mode: the first and third switches are open; the second and fourth switches are closed; and the switching network disconnects the first and second sampling capacitors from the positive and negative differential input signals and couples the first and second sampling capacitors to each other.
4. The circuit of claim 1, wherein in an integrating operating mode: the first and third switches are open; the second and fourth switches are closed; and the switching network disconnects the first and second sampling capacitors from the positive and negative differential input signals and couples the first and second sampling capacitors to each other.
19. The circuit of claim 15, wherein: the switched capacitor module comprises a first switched capacitor module; the switching network comprises a first switching network; and the circuit further comprises a second switched capacitor module configured to receive a reference voltage, the second switched capacitor module comprising: a second switching network configured to receive the reference voltage and coupled between the positive and negative inputs and the negative output; a first capacitor; and a second capacitor.
8. The circuit of claim 1, wherein: the switched capacitor module comprises a first switched capacitor module; the switching network comprises a first switching network; and the circuit further comprises a second switched capacitor module configured to receive a reference voltage, the second switched capacitor module comprising: a second switching network configured to receive the reference voltage and coupled between the positive and negative inputs and the negative output; a first capacitor; and a second capacitor.
20. The circuit of claim 15, wherein: the switched capacitor module comprises a first switched capacitor module; the switching network comprises a first switching network; and the circuit further comprising a second switched capacitor module, the second switched capacitor module comprising: a second switching network coupled between the positive and negative inputs and the positive and negative outputs; a first capacitor; and a second capacitor.
9. The circuit of claim 1, wherein: the switched capacitor module comprises a first switched capacitor module; the switching network comprises a first switching network; and the circuit further comprising a second switched capacitor module, the second switched capacitor module comprising: a second switching network coupled between the positive and negative inputs and the positive and negative outputs; a first capacitor; and a second capacitor.
Drawings
2. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “fraction 1/N of a reference voltage” and “fraction 1/N of the offset voltage” “switched capacitor module is a fraction 1/N of an offset associated with the second integrator” and “capacitor module is a fraction 1/N of the reference voltage” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3 Claims 4 and 6 and 12 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 4 it is unclear how the “the partial reference voltage signal comprises a fraction 1/N of a reference voltage signal, such that the differential signal comprises the fraction 1/N of the reference voltage signal integrated N times”. Further clarification is needed
Regarding claim 6 it is unclear how the “the partial offset voltage signal comprises a fraction 1/N of an offset voltage associated with the first integrator, such that the differential signal comprises the fraction 1/N of the offset voltage integrated N times ”. Further clarification is needed
Regarding claim 12 it is unclear how the “a capacitance of the switched capacitor module is chosen based on the predetermined number of times N such that the capacitance of the switched capacitor module is a fraction 1/N of an offset associated with the second integrator.”. Further clarification is needed
Regarding claim 14 it is unclear how the “a capacitance of the switched capacitor module is chosen based on the predetermined number of times N such that the capacitance of the switched capacitor module is a fraction 1/N of the reference voltage.”. Further clarification is needed
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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4 Claims 1-3, 5, 7, and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Romero et al. (US 2020/0319272 A1).
5 Regarding to claim 1, Romero discloses a method for operating a dual
integrator system, comprising:
uncoupling a first integrator (Figs. 1-4 & 28 Item 84 discloses the integrators
78,84 in Paragraph [0088-0089]) from an output buffer;
coupling a second integrator to the output buffer;
maintaining, by the second integrator (Figs. 1-4 & 28 Item 78 discloses the
integrators 78,84 in Paragraph [0088-0089]) and the output buffer,
a first output signal based on a first Hall sensor (Figs. 1-4 & 28 Item 52 discloses the Hall Effect element 52 in Paragraph [0085]) input signal (Figs. 1-4 & 28 Item 52 discloses the Hall output 52a in Paragraph [0085]);
resetting the first integrator (Figs. 1-4 & 28 Item 84);
performing, by the first integrator, (Figs. 1-4 & 28 Item 84) a sampling
operation and an integrating operation on a second Hall sensor input signal (Figs. 1-4 & 28 Item 52 discloses the Hall output 52d in Paragraph [0085]) resulting in a differential signal (Figs. 1-4 & 28 Item 14a or 14 b);
converting the first integrator (Figs. 1-4 & 28 Item 84) from a differential to a
single-ended mode to convert the differential signal to a second output signal;
in response to the first integrator (Figs. 1-4 & 28 Item 84) converting to the single
ended mode, uncoupling the second integrator (Figs. 1-4 & 28 Item 78) from the
output buffer;
coupling the first integrator (Figs. 1-4 & 28 Item 84) to the output buffer; and
maintaining, by the first integrator (Figs. 1-4 & 28 Item 84) and the output buffer, the second output signal based on the second Hall sensor input signal (Figs. 1-4 & 28 Item 52 discloses the Hall signal 52 D in Paragraph [0085]).
6 Regarding to claim 2, Romero discloses the method of claim 1, further
comprising performing, by the first integrator (Figs. 1-4 & 28 Item 84 discloses the
integrators 78,84 in Paragraph [0088-0089]), the sampling operation and the
integrating operation, a predetermined number of times N on the second Hall sensor input signal (Figs. 1-4 & 28 Item 52 discloses the Hall Effect element 52 b or d in Paragraph [0085]), wherein: the predetermined number of times N is selected based on a number of Hall spinning phases N in the second Hall sensor input signal (Figs. 1-4 & 28 Item 52 discloses the Hall Effect element 52 b or d in Paragraph [0085]), and
converting the first integrator (Figs. 1-4 & 28 Item 84 discloses the
integrators 78,84 in Paragraph [0088-0089]) from the differential to the single-ended mode comprises converting the first integrator in response to the first integrator performing the sampling operation and the integrating operation for the Nth time.
7 Regarding to claim 3, Romero discloses the method of claim 2, wherein
performing, by the first integrator (Figs. 1-4 & 28 Item 84 discloses the
integrators 78,84 in Paragraph [0088-0089]), the sampling operation and the
integrating operation, the predetermined number of times N on the second Hall
sensor input signal (Figs. 1-4 & 28 Item 52 discloses the Hall Effect element 52 b or d
in Paragraph [0085]), further comprises performing the sampling operation and the
integrating operation (Figs. 1-4 & 28 Item 84 discloses the integrators
78,84 in Paragraph [0088-0089]) the predetermined number of times N on a partial
reference voltage signal.
8 Regarding to claim 5 Romero discloses the method of claim 2, wherein
performing, by the first integrator, (Figs. 1-4 & 28 Item 84 discloses the
integrators 78,84 in Paragraph [0088-0089]), the sampling operation and the
integrating operation, the predetermined number of times N on the second
Hall sensor input signal (Figs. 1-4 & 28 Item 52 discloses the Hall Effect element 52 b
or d in Paragraph [0085]), further comprises performing the sampling
operation and the integrating operation the predetermined number of times
N on a partial offset voltage signal (Figs. 1-4 & 28 Item 84 discloses the
integrator 78 or 84 is coupled to receive the differential switched signal and
configured to generate a differential integrated signal in Paragraph [0087]).
9 Regarding to claim 7, Romero discloses a dual integrator system,
comprising:
a first integrator (Figs. 1-4 & 28 Item 84 discloses the integrators
78,84 in Paragraph [0088-0089]) configured to receive a differential Hall sensor signal (Figs. 1-4 & 28 Item 52 discloses the Hall output 52 a & d in Paragraph [0085]) and
a reference voltage, wherein the first integrator (Figs. 1-4 & 28 Item 84) comprises a first offset cancellation feedback loop (Figs. 1-4 & 28 Item the feedback circuits 116, or 118) and is further configured to output a first integrator signal based on the differential Hall sensor signal (Figs. 1-4 & 28 Item 52 discloses the Hall output 52d in Paragraph [0085]) and the reference voltage;
a second integrator (Figs. 1-4 & 28 Item 78 discloses the integrators
78,84 in Paragraph [0088-0089]) configured to receive the differential Hall sensor signal (Figs. 1-4 & 28 Item 52 discloses the Hall output 52 a & d in Paragraph [0085]) and the reference voltage, wherein the second integrator (Figs. 1-4 & 28 Item 78 ) comprises a second offset cancellation feedback loop (Figs. 1-4 & 28 Item the feedback circuits 116,or 118 ) and is further configured to output a second integrator signal based on the differential Hall sensor signal (Figs. 1-4 & 28 Item 52 discloses the Hall output 52 a & d in Paragraph [0085]) and the reference voltage;
an output stage (Figs. 1-4 & 28 Item 76 discloses he output switching circuit 76
(i.e., a modulator) in Paragraph [0076]); and
a switching network (Figs. 1-4 & 28 Item 64 & 52 output modulator discloses
the switching circuit 64 (i.e., a modulator) in Paragraph [0078]) coupled to the first (Figs. 1-4 & 28 Item 84) and second integrators (Figs. 1-4 & 28 Item 78) and the output stage and configured to alternate which of the first and second integrators is coupled to the output stage (Figs. 1-4 & 28 Item 76 discloses he output switching circuit 76 (i.e., a modulator) in Paragraph [0076]).
10 Regarding to claim 15, Romero discloses a circuit, comprising:
a switched capacitor module (Figs. 1-4 & 28 Item 72 discloses the first and
second capacitors 72, 74, in Paragraph [0087-0088]) configured to receive a positive differential input signal (Figs. 1-4 & 28 Item 72a) and a negative differential input signal, comprising a switching network, a first sampling capacitor (Figs. 1-4 & 28 Item 72), and a second sampling capacitor (Figs. 1-4 & 28 Item 74 discloses the first and second capacitors 72, 74, in Paragraph [0087-0088]);
an integrator (Figs. 1-4 & 28 Item 84 discloses the integrators
78,84 in Paragraph [0088-0089]) having a positive input coupled to the first sampling capacitor (Figs. 1-4 & 28 Item 72) a negative input coupled to the second sampling capacitor (Figs. 1-4 & 28 Item 74), a positive output, and a negative output;
a first feedback loop, (Figs. 1-4 & 28 Item116 discloses the feedback loop in
Paragraph [0088-0089]) comprising:
a first switch (Figs. 1 Item 10 & 12 discloses the switch network 1-4
connected to hall element 10 or 52 in Paragraph [00867]) coupled between the positive input and the negative output;
a second switch (Figs. 1-4 Item 10 & 12 discloses the switch network 1connected to hall element switch 2 in Paragraph [00867]) coupled to the positive input
a first feedback capacitor (Figs. 1-4 & 28 Item 72) a coupled between the
second switch (Figs. 1 Item 10 & 12 discloses the switch network switch 2) and the negative output; and
a second feedback loop (Figs. 1-4 & 28 Item 118 discloses the feedback loop
in Paragraph [0088-0089]), comprising:
a third switch (Figs. 1 Item 10 & 12 discloses the switch network 1-4
connected to hall element switch 3 in Paragraph [00867]) coupled between the negative input and the positive output;
a fourth switch (Figs. 1 Item 10 & 12 discloses the switch network 1-4
connected to hall element switch 4 in Paragraph [00867]) coupled to the negative input; and
a second feedback capacitor (Figs. 1-4 & 28 Item 74) a coupled between the
fourth switch (Figs. 1 Item 10 & 12 discloses the switch network 1-4) and the positive output.
a first integrator (Figs. 1-4 & 28 Item 84 discloses the integrators
78,84 in Paragraph [0088-0089]) configured to receive a differential Hall sensor signal (Figs. 1-4 & 28 Item 52 discloses the Hall output 52 a & d in Paragraph [0085]) and
a reference voltage, wherein the first integrator (Figs. 1-4 & 28 Item 84) comprises a first offset cancellation feedback loop (Figs. 1-4 & 28 Item the feedback circuits 116, or 118) and is further configured to output a first integrator signal based on the differential Hall sensor signal (Figs. 1-4 & 28 Item 52 discloses the Hall output 52d in Paragraph [0085]) and the reference voltage;
a second integrator (Figs. 1-4 & 28 Item 78 discloses the integrators
78,84 in Paragraph [0088-0089]) configured to receive the differential Hall sensor signal (Figs. 1-4 & 28 Item 52 discloses the Hall output 52 a & d in Paragraph [0085]) and the reference voltage, wherein the second integrator (Figs. 1-4 & 28 Item 78 ) comprises a second offset cancellation feedback loop (Figs. 1-4 & 28 Item the feedback circuits 116,or 118 ) and is further configured to output a second integrator signal based on the differential Hall sensor signal (Figs. 1-4 & 28 Item 52 discloses the Hall output 52 a & d in Paragraph [0085]) and the reference voltage;
an output stage (Figs. 1-4 & 28 Item 76 discloses he output switching circuit 76
(i.e., a modulator) in Paragraph [0076]); and
a switching network (Figs. 1-4 & 28 Item 64 & 52 output modulator discloses
the switching circuit 64 (i.e., a modulator) in Paragraph [0078]) coupled to the first (Figs. 1-4 & 28 Item 84) and second integrators (Figs. 1-4 & 28 Item 78) and the output stage and configured to alternate which of the first and second integrators is coupled to the output stage (Figs. 1-4 & 28 Item 76 discloses he output switching circuit 76 (i.e., a modulator) in Paragraph [0076]).
11 Regarding to claim 16, Romero discloses the circuit of claim 15, wherein in a reset operating mode:
the switching network (Figs. 1-4 & 28 Item 76 & 82 a switching circuit
76 & 82 (i.e., a modulator) generate a differential switched signal 82 a, 82
b, in Paragraph [0087 & 0089]) disconnects the first and second sampling
capacitors (Figs. 1-4 & 28 Item 72 discloses the first and second capacitors 72, 74, in Paragraph [0086-0088]) from the positive and negative
differential input signals and couples the first and second sampling capacitors to
each other (Figs. 1-4 & 28 Item 72 discloses the first and second capacitors 72, 74, in
Paragraph [0086-0088]); and
the first, second, (Figs. 1-4 & 28 Item 76 a switching circuit 76 (i.e., a
modulator) generate a differential switched signal 76 a, 76 b, in Paragraph [0087 & 0089]) third, and fourth switches (Figs. 1-4 & 28 Item 82 a switching circuit 82 (i.e., a modulator) generate a differential switched signal 82 a, 82 b, in Paragraph [0087 & 0089]) are closed.
12 Regarding to claim 17, Romero discloses the circuit of claim 15, wherein in a sampling operating mode:
the first and third switches are closed (Figs. 1-4 & 28 Item 76 & 82 a
switching circuit (i.e., a modulator) generate a differential switched signal 76 a, 82 a, in Paragraph [0087 & 0089]);
the second and fourth switches are open (Figs. 1-4 & 28 Item 76 & 82 a
switching circuit (i.e., a modulator) generate a differential switched signal 76 b, 82 b, in Paragraph [0087 & 0089]); and
the switching network (Figs. 1-4 & 28 Item 76 & 82) provides the positive
differential input signal to the first sampling capacitor and the negative differential input signal to the second sampling capacitor and uncouples the first and second sampling capacitors from each other (Figs. 1-4 & 28 Item 72 discloses the first and second capacitors 72, 74, in Paragraph [0086-0088]);
13 Regarding to claim 18, Romero discloses the circuit of claim 15, wherein in an integrating operating mode:
the first and third switches are open (Figs. 1-4 & 28 Item 76 & 82 a
switching circuit (i.e., a modulator) generate a differential switched signal 76 a, 82 a, in Paragraph [0087 & 0089]);
the second and fourth switches are closed (Figs. 1-4 & 28 Item 76 & 82 a
switching circuit (i.e., a modulator) generate a differential switched signal 76 b, 82 b, in Paragraph [0087 & 0089]); and
the switching network (Figs. 1-4 & 28 Item 76 & 82) disconnects the first
and second sampling capacitors from the positive and negative differential input signals and couples the first and second sampling capacitors to each other (Figs. 1-4 & 28 Item 72 discloses the first and second capacitors 72, 74, in Paragraph [0086-0088]).
14 Regarding to claim 19, Romero discloses the circuit of claim 15, wherein:
the switched capacitor module (Figs. 1-4 & 28 Item 72 discloses the first and
second capacitors 72, 74, in Paragraph [0086-0088]) comprises a first switched capacitor module;
the switching network comprises a first switching network (Figs. 1-4 & 28
Item 76 a switching circuit 76 (i.e., a modulator) generate a differential switched signal 76 a, 76 b, in Paragraph [0087 & 0089]); and
the circuit further comprises a second switched capacitor module (Figs. 1-4
& 28 Item 72 discloses the first and second capacitors 72, 74, in Paragraph [0086-0088]). configured to receive a reference voltage, the second switched capacitor module comprising:
a second switching network (Figs. 1-4 & 28 Item 82 a switching circuit 82 (i.e.,
a modulator) generate a differential switched signal 82 a, 82 b, in Paragraph [0087 & 0089]) are configured to receive the reference voltage and coupled between the positive and negative inputs and the negative output;
a first capacitor; and a second capacitor (Figs. 1-4 & 28 Item 72 discloses the first and second capacitors 72, 74, in Paragraph [0086-0088]).
15 Regarding to claim 20, Romero discloses the circuit of claim 15, wherein:
the switched capacitor module (Figs. 1-4 & 28 Item 72 discloses the first and
second capacitors 72, 74, in Paragraph [0086-0088]). comprises a first switched
capacitor module (Figs. 1-4 & 28 Item 72);
the switching network (Figs. 1-4 & 28 Item 76 a switching circuit 76 (i.e., a
modulator) generate a differential switched signal 76 a, 76 b, in Paragraph [0087 & 0089]); comprises a first switching network; and
the circuit further comprising a second switched capacitor module (Figs. 1
4 & 28 Item 74); the
second switched capacitor module (Figs. 1-4 & 28 Item 72 discloses the
first and second capacitors 72, 74, in Paragraph [0086-0088]).
comprising:
a second switching network (Figs. 1-4 & 28 Item 82 a switching circuit 82 (i.e.,
a modulator) generate a differential switched signal 82 a, 82 b, in Paragraph [0087 & 0089]) coupled between the positive and negative
inputs and the positive and negative outputs;
a first capacitor; and a second capacitor. (Figs. 1-4 & 28 Item 72 discloses the
first and second capacitors 72, 74, in Paragraph [0086-0088]).
Claim Rejections - 35 USC § 103
16 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
17 Claims 8-11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Romero et al. (US 2020/0319272 A1) in view of Petrie et al.al. (US 2016/0139230 A1).
18 Regarding to claim 8, Romero discloses the system of claim 7, wherein the
first integrator (Figs. 1-4 & 28 Item 84 discloses the integrators 78,84 in Paragraph [0088-0089]) and wherein the second integrator (Figs. 1-4 & 28 Item 78
discloses the integrators 78,84 in Paragraph [0088-0089]).
Romero fails to teach wherein the first integrator is further configured to perform a reset operation, a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation, and wherein the second integrator is further configured to perform the reset operation, the sampling operation, the integration operation, the differential to single-ended conversion operation, and the holding operation.
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Petrie teaches wherein the first integrator (Figs. 1-8 Item 452 discloses n
integrator circuit 452 is coupled to receive input signal 453 in Paragraph [0094 & 0097]) is further configured to perform a reset operation (Figs. 1-8 Item 452 discloses n
integrator circuit 452 includes anamplifier 464 may be reset and capacitors 454 and 456 in Paragraph [0094 & 0097]) a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation, and wherein the second integrator (Figs. 1-8 Item 452 discloses n integrator circuit 452 is coupled to receive input signal 453 in Paragraph [0094 & 0097]) is further configured to perform the reset operation (Figs. 1-8 Item 452 discloses n integrator circuit 452 includes anamplifier 464 may be reset and capacitors 454 and 456 in Paragraph [0094 & 0097]), the sampling operation, the integration operation, the differential to single-ended conversion operation, and the holding operation.
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Hall sensors used for magnetic field or current sensing in Romero to include an integrator with reset signal as taught by Petrie in order to provide an inputs and outputs of operational amplifier 464 may be reset based on desired output in para [0097]).
19 Regarding to claim 9, Romero discloses the system of claim 8 wherein the
first integrator (Figs. 1-4 & 28 Item 84 discloses the integrators 78,84 in Paragraph [0088-0089]) and wherein the second integrator (Figs. 1-4 & 28 Item 78
discloses the integrators 78,84 in Paragraph [0088-0089]).
Romero fails to teach wherein the switching network is configured to
uncouple the second integrator from the output stage and couple the first integrator to the output stage in response to the first integrator performing the holding operation, and
the second integrator is configured to perform the reset operation, the sampling operation, the integration operation, and the differential to single-ended conversion operation in response to being uncoupled from the output stage.
Petrie teaches wherein the switching network (Figs. 1-8 Item 452 discloses n
integrator circuit 452 including multiple switches in Paragraph [0094 & 0097]) is configured to uncouple the second integrator (Figs. 1-8 Item 452 discloses n
integrator circuit 452 is coupled to receive input signal 453 in Paragraph [0094 & 0097]) from the output stage and couple the first integrator to the output stage in response to the first integrator (Figs. 1-8 Item 452 discloses n integrator circuit 452 is coupled to receive input signal 453 in Paragraph [0094 & 0097]) performing the holding operation, and
the second integrator (Figs. 1-8 Item 452 discloses n integrator circuit 452 is coupled to receive input signal 453 in Paragraph [0094 & 0097]) is configured to perform the reset operation (Figs. 1-8 Item 452 discloses n integrator circuit 452 includes anamplifier 464 may be reset and capacitors 454 and 456 in Paragraph [0094 & 0097]), the sampling operation, the integration operation, and the differential to single-ended conversion operation in response to being uncoupled from the output stage (Figs. 1-8 Item 452 discloses n integrator circuit 452 includes output stage 462 in Paragraph [0094 & 0097]).
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Hall sensors used for magnetic field or current sensing in Romero to include an integrator with reset signal as taught by Petrie in order to provide an inputs and outputs of operational amplifier 464 may be reset based on desired output tin para [0097])
20 Regarding to claim 10, Romero discloses the system of claim 9, wherein the
second integrator (Figs. 1-4 & 28 Item 78 discloses the integrators 78,84 in Paragraph [0088-0089]) is configured to perform the sampling operation and the
integration operation a predetermined number of times N before performing the
differential to single-ended conversion operation, and wherein the predetermined
number of times N is chosen based on a number of Hall spinning phases N in the
differential Hall sensor signal (Figs. 1-4 & 28 Item 10 discloses the Hall element 10
with four-phase current spinning for the four sets of switches, has a frequency of
2fchop/N, where N is a number of phases in the current spinning. For four-phase
chopping, N=4 in Paragraph [0071]).
21 Regarding to claim 11, Romero discloses the system of claim 9, wherein the
second integrator (Figs. 1-4 & 28 Item 78 discloses the integrators 78,84 in Paragraph [0088-0089]) is configured to perform the sampling operation and the
integration operation a predetermined number of times N before performing the
differential to single-ended conversion operation, and wherein the predetermined
number of times N is chosen based on a number of Hall spinning phases N in the
differential Hall sensor signal (Figs. 1-4 & 28 Item 10 discloses the Hall element 10
with four-phase current spinning for the four sets of switches, has a frequency of
2fchop/N, where N is a number of phases in the current spinning. For four-phase
chopping, N=4 in Paragraph [0071]).
22 Regarding to claim 13, Romero discloses the system of claim 10, wherein
the second integrator (Figs. 1-8 Item 452 discloses n integrator circuit 452 is coupled
to receive input signal 453 in Paragraph [0094 & 0097]).
Romero fails to teach wherein the integrator further comprises a
switched capacitor module coupled to an input of the second integrator configured to receive the reference voltage and to an output of the integrator.
Petrie teaches wherein the integrator (Figs. 1-8 Item 452 discloses n
integrator circuit 452 including multiple switches in Paragraph [0094 & 0097]) further comprises a switched capacitor module (Figs. 1-8 Item 452 discloses n
integrator circuit 452 including switched capacitor 454 & 456 in Paragraph [0094 & 0097]) coupled to an input of the second integrator configured to receive the reference voltage and to an output of the integrator. (Figs. 1-8 Item 452 discloses n integrator circuit 452 including multiple switches in Paragraph [0094 & 0097])
It would have been obvious to one skilled in the art before the effective filing date of the invention to modify Hall sensors used for magnetic field or current sensing in Romero to include an integrator with reset signal as taught by Petrie in order to provide an inputs and outputs of operational amplifier 464 may be reset based on desired output in para [0097]).
Conclusion
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/BRENT J ANDREWS/Examiner, Art Unit 2858
/JUDY NGUYEN/Supervisory Patent Examiner, Art Unit 2858