DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 10/27/25. Claims 1-18 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of species II in the reply filed on 10/27/25 is acknowledged. Claims 1-5 and 8-17, are presented for examination consideration. In light of applicants remarks restriction is withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5-6 and 19 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abe (US 20150061752 A1)
Regarding claim 1. Abe teaches a cascade transistor circuit [fig 1] comprising: a depletion mode semiconductor device [q2];
an enhancement mode transistor [q1] having a drain terminal connected in series to a source terminal of the depletion mode semiconductor device, wherein the depletion mode device has a gate [gate of q2] that is coupled with a source of the enhancement mode transistor device;
a gate driver [100 with R1 and D1 excluding G] coupled to a first node [P] between the source of the depletion mode semiconductor device and the drain of the enhancement mode transistor, wherein the gate driver is further coupled to a gate terminal of the enhancement mode transistor;
and a first capacitor [c1] coupled between the gate driver [E] and the source of the cascode transistor circuit [p0], wherein the first capacitor provides a voltage source for the gate driver so that the gate driver is powered by the depletion mode semiconductor device [function of c1];
wherein the gate driver comprises a first diode [D1] coupled between the first node and the first capacitor [cathode is between P and c1], and wherein the gate driver further comprises a switch [G] coupled between the first node and the first capacitor, wherein the switch is connected in parallel with the first diode [connected in parallel through q1 and R1];
and wherein the first diode is configured to allow current to flow from the depletion mode device to the capacitor [function of D1], so that the first capacitor is configured to store energy [stored energy at t3-t4] received from the depletion mode semiconductor device [energy was received from having Vgs2, q2 is normally ON, ¶46] when the enhancement mode transistor [q1] is in the off-state [at t5 q1 is OFF, ¶50 and c1 still has the voltage previously received from q2, thus c1 being configured to keep stored energy V].
Regarding claim 2. Abe teaches the cascode transistor circuit according to claim 1, wherein the gate driver is powered by an energy harvesting mechanism [R1], and wherein the energy harvesting mechanism is configured to collect energy from the first node [i.e. voltage difference at R1].
Regarding claim 5. Abe teaches the cascode transistor circuit according to claim 1, further comprising a first resistor [R1 left terminal is between said nodes] connected between the first node and the switch.
Regarding claim 6. Abe teaches the cascode transistor circuit according to claim 1, wherein the depletion mode semiconductor device has a gate that is biased by a negative power rail [Vgs2 is shown to be biased by a negative voltage, see 2d].
Regarding method claims 19, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device "inherently performs the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 rejected under 35 U.S.C. 103 as being unpatentable over Abe (US 20150061752 A1) in view of NEUDORFHOFER et al. (US 20230095515 A1 and hereinafter as Neu)
Regarding claim 3. Abe teaches the cascode transistor circuit according to claim 1. However, Abe does not explicitly mention wherein the depletion mode semiconductor device comprises a GaN field effect transistor. Neu teaches wherein the depletion mode semiconductor device comprises a GaN field effect transistor [44]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Neu in order to provide a transistor that can withstand higher electric fields, enabling devices to handle more power in smaller package.
Regarding claim 4. Abe teaches the cascode transistor circuit according to claim 1, However, Abe does not explicitly mention wherein the enhancement mode transistor device comprises a Silicon MOSFET. Neu teaches wherein the enhancement mode transistor device comprises a Silicon MOSFET [46]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Neu in order to provide a transistor that is readily available in countless variations for different applications making them a more affordable option.
Claim 8 rejected under 35 U.S.C. 103 as being unpatentable over Abe (US 20150061752 A1) in view of Schenkel (5841643)
Regarding claim 8. Abe teaches the cascode transistor circuit according to claim 1. However, Abe does not explicitly mention wherein the depletion mode semiconductor device, the enhancement mode transistor, and the gate driver are formed in a single package, and wherein the depletion mode semiconductor device, the enhancement mode transistor, and the gate driver are formed on a single chip.
Schenkel teaches wherein the depletion mode semiconductor device, the enhancement mode transistor, and the gate driver are formed in a single package, and wherein the depletion mode semiconductor device, the enhancement mode transistor, and the gate driver are formed on a single chip [col 1 lines 10-25 motivation]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Schenkel in order to integrate all the components in a single circuit, which advantageously reduces the size and complexity of the overall switching regulator circuit.
Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over Abe (US 20150061752 A1) in view of Olyunin et al. (US 20190165779 A1 and hereinafter as Oly)
Regarding claim 18. Abe teaches the circuits according to claim 1. However, Abe does not explicitly mention an AC-DC converter comprising one or more cascode transistor. Oly teaches an AC-DC converter comprising one or more cascode transistor [see fig 6 ACDC with 100d]. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use the features of Oly in order to provide switching device having a high power capacity and a low power loss may be provided [¶22].
Allowable Subject Matter
Claims 7 and 9-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Monica Lewis, can be reached on (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838