DETAILED ACTION
This action is in response to the 02/26/2026 amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US Pub. No. 2012/0293017; (hereinafter Lidsky).
Regarding claim 1, Lidsky [e.g. Fig. 3D, 3E; paragraph 074 recites “In FIG. 3E, each IPAMD 328 can be implemented to protect a respective power supply 332 of the power domain according to the various embodiments disclosed herein”] discloses an apparatus comprising: a first input power bus having a first input terminal coupled to a first input power source [e.g. Fig. 3E; 320], a first output terminal [e.g. output of 336], and a first group of line diodes [e.g. Fig. 3D; intrinsic diodes necessary present in MOSFETs; paragraph 069 recites “transistors 204a and 204b can both be P-channel or N-channel MOSFETs”; similar to instant application which recites in paragraph 037 “to improve efficiency and reduce voltage drop-off across the diodes 112B, 112C, the diodes 112B, 112C and the corresponding switches 114B, 114C can be integrated into metal-oxide-semiconductor-field-effect-transistor (MOSFET) ideal diode circuits”] between the first input terminal and the first output terminal, the first group of line diodes comprising: a first input diode having a cathode coupled to the first input terminal [e.g. Fig. 3D; cathode of intrinsic diode of 204a corresponding to upper IPAMD 336 of Fig. 3E], wherein a first input switch associated with the first input diode is controllable by a first input controller that senses a voltage across the first input diode [e.g. voltage at 397a-b being input to control 394; paragraph 071]; and a first output diode having a cathode coupled to the first output terminal [e.g. Fig. 3D; cathode of intrinsic diode of 204b corresponding to IPAMD 336 of Fig. 3E], wherein a first output switch [e.g. 204a] associated with the first output diode is controllable by a first output controller that senses a voltage across the first output diode [e.g. Fig. 3D; voltage 397a-b correspond to a voltage across 204a and 204b, therefore is a voltage across 204a, said voltage is input to control 394; paragraph 071]; and a second input power bus having a second input terminal coupled to a second input power source [e.g. Fig. 3E; 324], a second output terminal coupled to the first output terminal of the first input power bus [e.g. Fig. 3E; at input node of component C], and a second group of line diodes [e.g. Fig. 3E; lowest IPAMD 336] between the second input terminal and the second output terminal, wherein the first output terminal and the second output terminal are coupled to provide power to a load [e.g. Component C]; wherein the first group of line diodes are separated from the second group of line diodes, from the first input terminal to the first output terminal [e.g. upper and lower IPAMD 336 are separated at its input by 332, and IPAMD 328], and wherein the first group of line diodes are coupled to the second group of line diodes after the first output terminal and after the second output terminal [e.g. upper and lower IPAMD 336 are coupled each after its outputs at node of component C].
Regarding claim 2, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the first input controller is configured to activate the first input switch in response to detecting a forward voltage [e.g. paragraph 071 recites “In FIG. 3D, the controller 394 has a first sensing input 397a coupled at a node between switching mechanism 204 and component 388 to sense a forward current, Iout, passing through switching mechanism 204, as well as a reverse current, Irev, possibly passing in the opposite direction of Iout. In this way, controller 394 is operatively coupled to switch off the load switch 204 responsive to either Iout exceeding a designated threshold or Irev exceeding a designated threshold. In some implementations, controller 394 is also operatively coupled to switch off the switching mechanism 204 if the monitored voltage at the first sensing input 397a or a second sensing input 397b coupled at a node between component 384 and switching mechanism 204 exceeds a threshold, if a monitored temperature exceeds a threshold, and/or the measured power exceeds a threshold”. In paragraph 071 is suggested that if the voltage is forward and below a threshold the switch is turned ON].
Regarding claim 3, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the first input controller is configured to: detect an overcurrent; and deactivate the first input switch in response to detecting the overcurrent [e.g. paragraph 071 recites “controller 394 is operatively coupled to switch off the load switch 204 responsive to either Iout exceeding a designated threshold or Irev exceeding a designated threshold”].
Regarding claim 4, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the first input switch corresponds to a metal-oxide-semiconductor-field-effect transistor (MOSFET) [e.g. Fig. 3D; paragraph 069 recites “transistors 204a and 204b can both be P-channel or N-channel MOSFETs]”.
Regarding claim 5, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the first output diode and the first output switch are integrated into a metal-oxide-semiconductor-field-effect-transistor (MOSFET) ideal diode circuit [e.g. Fig. 3D; intrinsic diodes necessary present in MOSFETs; paragraph 069 recites “transistors 204a and 204b can both be P-channel or N-channel MOSFETs”].
Regarding claim 6, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the first output controller is configured to deactivate the first output switch in response to the voltage across the first output diode indicating a reverse voltage [e.g. paragraph 071 recites “the controller 394 has a first sensing input 397a coupled at a node between switching mechanism 204 and component 388 to sense a forward current, Iout, passing through switching mechanism 204, as well as a reverse current, Irev, possibly passing in the opposite direction of Iout. In this way, controller 394 is operatively coupled to switch off the load switch 204 responsive to either Iout exceeding a designated threshold or Irev exceeding a designated threshold. In some implementations, controller 394 is also operatively coupled to switch off the switching mechanism 204 if the monitored voltage at the first sensing input 397a or a second sensing input 397b coupled at a node between component 384 and switching mechanism 204 exceeds a threshold”].
Regarding claim 7, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the first group of line diodes [e.g. Fig. 3E, upper IPAMD 336-328 corresponding to intrinsic diodes of each one of 204a and 204b (physically separated by electrical conductor at inputs of 328] further comprises: a first middle diode [e.g. intrinsic diode in MOSFET of 204b corresponding to IPAMD 328 of Fig. 3D] having an anode coupled to an anode of the first input diode and having a cathode coupled to an anode of the first output diode [e.g. indirectly coupled via Power Supply 332 (Fig. 3E)], wherein a first middle switch [e.g. 204b of IPAMD 328] associated with the first middle diode is controllable by a first middle controller [e.g. 394] that senses a voltage across the first middle diode, wherein the first middle controller is configured to deactivate the first middle switch in response to the voltage across the first middle diode indicating a reverse voltage [e.g. paragraph 071 recites “the controller 394 has a first sensing input 397a coupled at a node between switching mechanism 204 and component 388 to sense a forward current, Iout, passing through switching mechanism 204, as well as a reverse current, Irev, possibly passing in the opposite direction of Iout. In this way, controller 394 is operatively coupled to switch off the load switch 204 responsive to either Iout exceeding a designated threshold or Irev exceeding a designated threshold. In some implementations, controller 394 is also operatively coupled to switch off the switching mechanism 204 if the monitored voltage at the first sensing input 397a or a second sensing input 397b coupled at a node between component 384 and switching mechanism 204 exceeds a threshold”].
Regarding claim 8, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the first middle diode and the first middle switch are integrated into a metal-oxide-semiconductor-field-effect-transistor (MOSFET) ideal diode circuit [e.g. Fig. 3D; intrinsic diodes necessary present in MOSFETs; paragraph 069 recites “transistors 204a and 204b can both be P-channel or N-channel MOSFETs”].
Regarding claim 9, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the second group of line diodes comprises: a second input diode [e.g. intrinsic diode in MOSFET of 204a (Fig. 3D) in lower 328 (Fig. 3E)] having a cathode coupled to the second input terminal, wherein a second input switch associated with the second input diode is controllable by a second input controller [e.g. 394] that senses a voltage across the second input diode [e.g. 397a-397b]; and a second output diode [e.g. intrinsic diode in MOSFET of 204b in 328] having a cathode coupled to the second output terminal, wherein a second output switch associated with the second output diode is controllable by a second output controller [e.g. 394] that senses a voltage across the second output diode [e.g. 397a-397b].
Regarding claim 10, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the second input controller is configured to activate the second input switch in response to detecting a forward voltage [e.g. paragraph 071 recites “In FIG. 3D, the controller 394 has a first sensing input 397a coupled at a node between switching mechanism 204 and component 388 to sense a forward current, Iout, passing through switching mechanism 204, as well as a reverse current, Irev, possibly passing in the opposite direction of Iout. In this way, controller 394 is operatively coupled to switch off the load switch 204 responsive to either Iout exceeding a designated threshold or Irev exceeding a designated threshold. In some implementations, controller 394 is also operatively coupled to switch off the switching mechanism 204 if the monitored voltage at the first sensing input 397a or a second sensing input 397b coupled at a node between component 384 and switching mechanism 204 exceeds a threshold, if a monitored temperature exceeds a threshold, and/or the measured power exceeds a threshold”. In paragraph 071 is suggested that if the voltage is forward and below a threshold the switch is turned ON].
Regarding claim 11, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the second input controller is configured to: detect an overcurrent; and deactivate the second input switch in response to detecting the overcurrent [e.g. paragraph 071 recites “controller 394 is operatively coupled to switch off the load switch 204 responsive to either Iout exceeding a designated threshold or Irev exceeding a designated threshold”]..
Regarding claim 12, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the second output diode and the second output switch are integrated into a metal-oxide-semiconductor-field-effect-transistor (MOSFET) ideal diode circuit [e.g. Fig. 3D; paragraph 069 recites “transistors 204a and 204b can both be P-channel or N-channel MOSFETs]”.
Regarding claim 13, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the second output controller is configured to deactivate the second output switch in response to the voltage across the second output diode indicating a reverse voltage [e.g. paragraph 071 recites “the controller 394 has a first sensing input 397a coupled at a node between switching mechanism 204 and component 388 to sense a forward current, Iout, passing through switching mechanism 204, as well as a reverse current, Irev, possibly passing in the opposite direction of Iout. In this way, controller 394 is operatively coupled to switch off the load switch 204 responsive to either Iout exceeding a designated threshold or Irev exceeding a designated threshold. In some implementations, controller 394 is also operatively coupled to switch off the switching mechanism 204 if the monitored voltage at the first sensing input 397a or a second sensing input 397b coupled at a node between component 384 and switching mechanism 204 exceeds a threshold”].
Regarding claim 14, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the second group of line diodes [e.g. lower IPAMDs 328 and 336] further comprises: a second middle diode [e.g. intrinsic diode in MOSFET of 204b of IPAMD 328 corresponding to Fig. 3D] having an anode coupled to an anode of the second input diode and having a cathode coupled to an anode of the second output diode, wherein a second middle switch [e.g. 204b] associated with the second middle diode is controllable by a second middle controller [e.g. 394] that senses a voltage across the second middle diode, wherein the second middle controller is configured to deactivate the second middle switch in response to the voltage across the second middle diode indicating a reverse voltage [e.g. paragraph 071 recites “the controller 394 has a first sensing input 397a coupled at a node between switching mechanism 204 and component 388 to sense a forward current, Iout, passing through switching mechanism 204, as well as a reverse current, Irev, possibly passing in the opposite direction of Iout. In this way, controller 394 is operatively coupled to switch off the load switch 204 responsive to either Iout exceeding a designated threshold or Irev exceeding a designated threshold. In some implementations, controller 394 is also operatively coupled to switch off the switching mechanism 204 if the monitored voltage at the first sensing input 397a or a second sensing input 397b coupled at a node between component 384 and switching mechanism 204 exceeds a threshold”].
Regarding claim 15, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the second middle diode and the second middle switch are integrated into a metal-oxide-semiconductor-field-effect-transistor (MOSFET) ideal diode circuit [e.g. Fig. 3D; intrinsic diodes necessary present in MOSFETs; paragraph 069 recites “transistors 204a and 204b can both be P-channel or N-channel MOSFETs”].
Regarding claim 16, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the load corresponds to a power supply or a converter circuit [e.g. paragraph 073 recites “The outputs of the IPAMDs 336 are coupled to a Component C, which can be a load in the form of a device or system to be powered”].
Regarding claim 17, Lidsky [e.g. Fig. 3D, 3E; paragraph 074 recites “In FIG. 3E, each IPAMD 328 can be implemented to protect a respective power supply 332 of the power domain according to the various embodiments disclosed herein”] discloses an aircraft comprising: a load [e.g. Fig. 3E; Component C]; and a dual-input bus comprising: a first input power bus having a first input terminal coupled to a first input power source [e.g. Fig. 3E; 320], a first output terminal [e.g. output of 336], and a first group of line diodes [e.g. Fig. 3D; intrinsic diodes necessary present in MOSFETs; paragraph 069 recites “transistors 204a and 204b can both be P-channel or N-channel MOSFETs”; similar to instant application which recites in paragraph 037 “to improve efficiency and reduce voltage drop-off across the diodes 112B, 112C, the diodes 112B, 112C and the corresponding switches 114B, 114C can be integrated into metal-oxide-semiconductor-field-effect-transistor (MOSFET) ideal diode circuits”] between the first input terminal and the first output terminal, the first group of line diodes comprising: a first input diode having a cathode coupled to the first input terminal [e.g. Fig. 3D; cathode of intrinsic diode of 204a corresponding to upper IPAMD 336 of Fig. 3E], wherein a first input switch associated with the first input diode is controllable by a first input controller that senses a voltage across the first input diode [e.g. voltage at 397a-b being input to control 394; paragraph 071]; and a first output diode having a cathode coupled to the first output terminal [e.g. Fig. 3D; cathode of intrinsic diode of 204b corresponding to IPAMD 336 of Fig. 3E], wherein a first output switch [e.g. 204a] associated with the first output diode is controllable by a first output controller that senses a voltage across the first output diode [e.g. Fig. 3D; voltage 397a-b correspond to a voltage across 204a and 204b, therefore is a voltage across 204a, said voltage is input to control 394; paragraph 071]; and a second input power bus having a second input terminal coupled to a second input power source [e.g. Fig. 3E; 324], a second output terminal coupled to the first output terminal of the first input power bus [e.g. Fig. 3E; at input node of component C], and a second group of line diodes [e.g. Fig. 3E; lowest IPAMD 336] between the second input terminal and the second output terminal, wherein the first output terminal and the second output terminal are coupled to provide power to the load [e.g. Component C], wherein the first group of line diodes are separated from the second group of line diodes, from the first input terminal to the first output terminal [e.g. upper and lower IPAMD 336 are separated at its input by 332, and IPAMD 328], and wherein the first group of line diodes are coupled to the second group of line diodes after the first output terminal and after the second output terminal [e.g. upper and lower IPAMD 336 are coupled each after its outputs at node of component C].
Regarding claim 18, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the first input controller is configured to: detect an overcurrent; and deactivate the first input switch in response to detecting the overcurrent [e.g. paragraph 071 recites “controller 394 is operatively coupled to switch off the load switch 204 responsive to either Iout exceeding a designated threshold or Irev exceeding a designated threshold”].
Regarding claim 19, Lidsky [e.g. Fig. 3D, 3E] discloses wherein the first output controller is configured to deactivate the first output switch in response to the voltage across the first output diode indicating a reverse voltage [e.g. paragraph 071 recites “the controller 394 has a first sensing input 397a coupled at a node between switching mechanism 204 and component 388 to sense a forward current, Iout, passing through switching mechanism 204, as well as a reverse current, Irev, possibly passing in the opposite direction of Iout. In this way, controller 394 is operatively coupled to switch off the load switch 204 responsive to either Iout exceeding a designated threshold or Irev exceeding a designated threshold. In some implementations, controller 394 is also operatively coupled to switch off the switching mechanism 204 if the monitored voltage at the first sensing input 397a or a second sensing input 397b coupled at a node between component 384 and switching mechanism 204 exceeds a threshold”].
Regarding claim 20, Lidsky [e.g. Fig. 3D, 3E; paragraph 074 recites “In FIG. 3E, each IPAMD 328 can be implemented to protect a respective power supply 332 of the power domain according to the various embodiments disclosed herein”] discloses a method comprising: applying power to a load [e.g. Component C] via a first input power bus and based on a first input power source [e.g. Fig. 3E; 320], wherein the first input power bus has a first input terminal [e.g. input terminal of higher IPAMD 336] coupled to the first input power source, a first output terminal [e.g. output terminal of 336], and a first group of line diodes [e.g. Fig. 3D; intrinsic diodes necessary present in MOSFETs; paragraph 069 recites “transistors 204a and 204b can both be P-channel or N-channel MOSFETs”; similar to instant application which recites in paragraph 037 “to improve efficiency and reduce voltage drop-off across the diodes 112B, 112C, the diodes 112B, 112C and the corresponding switches 114B, 114C can be integrated into metal-oxide-semiconductor-field-effect-transistor (MOSFET) ideal diode circuits”] between the first input terminal and the first output terminal, and wherein the first group of line diodes comprises: a first input diode having a cathode coupled to the first input terminal [e.g. Fig. 3D; cathode of intrinsic diode of 204a corresponding to upper IPAMD 336 of Fig. 3E], wherein a first input switch associated with the first input diode is controllable by a first input controller that senses a voltage across the first input diode [e.g. voltage at 397a-b being input to control 394; paragraph 071]; and a first output diode having a cathode coupled to the first output terminal [e.g. Fig. 3D; cathode of intrinsic diode of 204b corresponding to IPAMD 336 of Fig. 3E], wherein a first output switch [e.g. 204a] associated with the first output diode is controllable by a first output controller that senses a voltage across the first output diode [e.g. Fig. 3D; voltage 397a-b correspond to a voltage across 204a and 204b, therefore is a voltage across 204a, said voltage is input to control 394; paragraph 071]; and applying power to the load via a second input power bus and based on a second input power source [e.g. Fig. 3E; 324], wherein the second input power bus has a second input terminal [e.g. input of lower IPAMD 340] coupled to the second input power source, a second output terminal coupled to the first output terminal of the first input power bus [e.g. Fig. 3E; at input node of component C], and a second group of line diodes [e.g. Fig. 3E; IPAMD 336 corresponding to intrinsic diodes of 204a-204b; Fig. 3D] between the second input terminal and the second output terminal, wherein the first output terminal and the second output terminal are coupled to provide power to the load [e.g. at input of Component C], wherein the first group of line diodes are separated from the second group of line diodes, from the first input terminal to the first output terminal [e.g. upper and lower IPAMD 336 are separated at its input by 332, and IPAMD 328], and wherein the first group of line diodes are coupled to the second group of line diodes after the first output terminal and after the second output terminal [e.g. upper and lower IPAMD 336 are coupled each after its outputs at node of component C].
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Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838