Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed December 3, 2025 have been fully considered but they are not persuasive.
In page 1 of the remarks, Applicant states that the drawings of Figs. 1-5 are objected to as not being designated with the “Prior Art” label, and disagrees, pointing out that Figs. 1-5 contain more than “that which is old” as asserted to by the Office Action (“OA”). Furthermore, Figs. 1-17, and 20 were objected to as the figures “should be provided with descriptive text labels”, and requests clarification of the objection.
In page 2 of the remarks, Applicant states that the Abstract was objected to for including the phrase “is described”, and has been amended to remove the objected-to term, and requests withdrawal of the objection to the Abstract. Examiner states that as the Abstract has been amended to remove the term “is described”, the objections to the Abstract are withdrawn.
Applicant simply states “Figures 1-5 contain more than “that which is old”. However, provides no explanation and merely conclusory statement that directly contradicts the originally filed specification. Examiner states that Figs. 1-5 have their objections maintained, as the figures describe conventional systems, as found expressly in the Specification for paragraphs [0109] for Fig. 1, [0115] for Fig. 2, [0119] for Fig. 3, [0121] for Fig. 4, and [0124] for Fig. 5, and paragraph [0105] states “We now describe how prior art systems run computer programs with reference to Figures 1 to 5 […]”. The reply by the Applicant is not fully responsive to the prior Office action, but since the above-mentioned reply to the objection appears to be bona fide, the examiner reminds the Applicant that Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Examiner maintains the objections for a prior art label being required for Figs. 1-5. The objection to the drawings will not be held in abeyance.
With regards to the statement that figures “should be provided with descriptive text labels” for Figs. 1-17, and 20, Applicant’s assertion that the current figures “are labeled with respective element numbers” , however Applicant does not explain how these “numbers” are “descriptive text labels” as so required. The Examiner states that without any descriptive text labels to clarify the figures themselves for the unlabeled boxes present in the aforementioned figures, a person of ordinary skill in the art would not be able to understand the necessary components of the invention, and Examiner states that additional text would be helpful for a person of ordinary skill to understand the figures with “a labeled representation (e.g., a labeled rectangular box)”, and the invention of the Applicant, as stated in MPEP 608.02(d), “Complete Illustration in Drawings”, paragraph (a).
In pages 2-4 of the remarks, Applicant states that claims 1-20 (“stated as claims 3, 8, 9, 16, and 19”) were rejected under 35 U.S.C. 112(b) as being indefinite for failing to distinctly claim the subject matter. Independent claim 1 was rejected for the terms “such that” and “can be” may lead to confusion over the intended scope of the claims, and Applicant replaces the wording of “such that” with “to enable” to place a functional limitation. Furthermore, the term “a computer program executable” of line 6 in claim 1 is unclear if “a computer program executable” being compiled is the same as “a computer program executable” stated in lines 1-2, or a different computer program executable is described. Finally, the term “compatible” in claim 1 is a relative term, with Applicant stating that the compatibility refers to the variation applied to the processing module, and the first variation applied to the at least one programmable element, stating in [0136] and [0137]. and Applicant has amended the independent claims to clarify the rejections. Dependent claims 3, 5, 8-12 inherited the rejections of claim 1, and Applicant requests withdrawal of the rejections. Independent claims 13, and 20, with dependent claims 14-19 inherited the rejections of claim 13, and Applicant also requests withdrawal of the rejections of the claims above. The following claims have been rejected under 112(b) for the following reasons: claim 3 for “[the] application of encryption”, claim 5 for “the ordering of bits”, claim 8 for “the application of the first variation”, and “the application of at least one arithmetic”, claim 9 for “the application of at least one arithmetic or logical operation” and “the respective operation”, claim 14 for “the code generation step”, claim 16 for “the application of the second variation”, and claim 19 for “the application of the second variation”, and “the code generation step”, all for lacking antecedent basis in the claims. Applicant requests withdrawal of the 112(b) rejections for the claims recited above.
Examiner disagrees with the Applicant regarding the withdrawal of all rejections under 112(b). The terms “such that” and “can be” have been removed by the amendment to the independent claim 1, replaced with “to enable” and “to be” and the rejections to these terms have been withdrawn. However, the term “compatible” remains indefinite in the independent claims regarding “compatible compiler” and “compatible computer program executable”, as the term is still not defined in the independent claims, with what types of compilers would be compatible with changes to programmable elements of a processing module being unknown. Furthermore, paragraphs [0136] and [0137] do not clear up a variation being applied to the processing module being compatible to enable only a compatible computer program executable to be run using a processing module. As a result, the independent claims 1, 13, and 20 remain rejected for the term ‘compatible’ still not being described in the claims or the Specification of the Applicant. Furthermore, the dependent claims 3, 5, 8, 9, 14, 16, and 19 were previously rejected for lacking antecedent basis in the claims, and all dependent claims except claim 5 have been amended to traverse the rejections made previously for lacking antecedent basis, and the rejections of claims 3, 8, 9, 14, 16, and 19 have been withdrawn. However, claim 5’s rejections under 112(b) remains, as the phrase of “the ordering of bits” still lacks antecedent basis in the claims is defined implicitly by the presence of bits stored in the memory, and be stored in some order and order exists implicitly. However, Examiner states that the term “ordering of bits” was never explicitly stated in either claim 1 or 5, where the issue of lack of antecedent basis is raised, and an implicit definition is not enough for a term to be defined. As a result, claim 5’s rejection of “the ordering of bits” remains rejected under 112(b) for indefiniteness.
In pages 4-5, Applicant states that claims 1-20 were rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. Applicant simply states that the independent claims were amended to clarify the claims, and requests withdrawal, and states that claim 3 has no need to specify a particular method of encryption, and simply states that a person of ordinary skill in the art would understand the language of claim 3 and paragraph [0164] of the Specification, and requests withdrawal of the rejections of 112(a).
Examiner disagrees with the Applicant regarding the withdrawal of all rejections under 112(a). Applicant has not pointed out where the amendments for independent claim 1 is supported, nor does there appear to be a written description of the claim limitation ‘varying at least one programmable element of the processing module using a first variation applied to the at least one programmable element to modify the processing module to enable only a compatible computer program executable compiled using a compatible compiler to be run using the processing module […]’ in the application as filed. Furthermore, Applicant’s assertion that claim 3 has no need to specify a particular method of encryption is insufficient as, without an explanation or examples on what types of encryption the invention performs, a person of ordinary skill in the art would not understand how to make the invention with regards to what encryption process to use, and it is not enough that one skilled in the art could write a program to achieve the claimed function because the specification must explain how the inventor intends to achieve the claimed function to satisfy the written description requirement. See, e.g., Vasudevan Software, Inc. v. MicroStrategy, Inc., 782 F.3d 671, 681-683, 114 USPQ2d 1349, 1356, 1357 (Fed. Cir. 2015). As a result, Examiner maintains the rejections under 112(a) for claims 1, 3, 5, 8-20 made in the previous OA.
In pages 5-6, Applicant states that claims 1-3, 5-10, and 20 were rejected under 35 U.S.C. 102(a)(1) as being anticipated by Folmsbee (US 6598166 B1), and claim 1 has been amended to include the subject matter of original claims 2 and 7, which have been cancelled, along with claims 4 and 6. Applicant states that claim 1 amended with the limitations of claim 7, that being “the first variation disables or enables instructions in a control unit of the central processing unit”. Applicant states that Folmsbee simply describes compilation and not disablement or enablement of instructions in a CPU by some variation of the programmable element of the processing module, and does not reference a modification which can enable or disable instructions, only stating a CPU and compiler to be consistent. Applicant states that amended claim 1 is novel over Folmsbee, with independent claims 13 and 20 are similar in scope and are novel for the same reasons. Furthermore, Applicant states that claims 3, 5, and 8-12 is novel as independent claim 1 is novel over the prior art, and requests withdrawal of the rejections.
Examiner disagrees with the Applicant regarding the withdrawal of all rejections under 35 U.S.C. 102(a)(1). Applicant has simply moved the limitations that were previously present in claims 2 and 7 to the independent claims 1, 13, and 20, and both dependent claims 2 and 7 were also previously disclosed by Folmsbee. Regarding the claim limitation formerly in claim 7, now part of the independent claims, it states “wherein the first variation disables or enables instructions in a control unit of the central processing unit”, and Examiner has withdrawn the rejection of Folmsbee, which indeed does not contain modification of a processor to enable or disable instructions of the processor. However, the reference of Sutton et al. (US 20030229794 A1), hereinafter Sutton, teaches the claim limitation of a first variation disabling or enabling instructions in a control unit of the CPU in paragraph [0039] of Sutton, where a "virtual machine monitor initialization" (VMMINIT) 624 can disable operations of a PSMBASE register 616 of CPU C 618 to support trusted SMM operations, as shown in Fig. 6, with the VMMINIT corresponding to a first variation that disables instructions in a control unit of the CPU. The primary motivation of Sutton to disable operations of a PSMBASE register in a virtualized instance of a system to redirect all system management interrupts (SMIs) to the secured virtual machine monitor (SVMM) to permit or prevent direct access to hardware resources from an untrusted operations system, as taught by Sutton [0018] and [0023]. As a result, the independent claims 1, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Folmsbee in view of Sutton, and claim 13 remains rejected under 35 U.S.C. 103 over Folmsbee in view of Ruff and Sutton. The dependent claims 3, 5, 8-12 are rejected under 35 U.S.C. 103 as dependent on claim 1 above, and claims 14-19 are rejected under 35 U.S.C. 103 as dependent on claim 13 above.
Finally, in pages 6-7 of the remarks, Applicant states that claims 4, 11, and 12 were rejected under 35 U.S.C. 103 as being unpatentable as being obvious over Folmsbee in view of Ruff (US 20150378674 A1), with claims 13-19 being rejected under 35 U.S.C. 103 as being unpatentable over Folmsbee in view of Guri-1 (US 9703954 B2) and Guri-2 (US 20180137280 A1), and Applicant disagrees with the rejections. Applicant again recites claim 1’s limitations, stating that Folmsbee does not address any such issue regarding disabling instructions that are identified as malicious software and not run. Furthermore, the Applicant states that claims 4, 11-12, and 14-19 should be allowable as the independent claims are also in an allowable state, and requests withdrawal of the rejections of the dependent claims recited above.
Examiner disagrees with the Applicant regarding the withdrawal of all rejections under 35 U.S.C. 103 for claims 4, 11-12, and 14-19. Regarding the independent claims 1, 13, and 20, the amended limitation of “wherein the first variation disables or enables instructions in a control unit of the central processing unit” as taught by Folmsbee in view of Sutton for claims 1 and 20 above, and claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Folmsbee in view of Sutton, Guri-1 and Guri-2. Furthermore, claim 4 has been canceled, claims 11-12, 15-18 remain with the same limitations, and claims 14 and 19 have been amended to clear up the rejection of 112(b) for lack of antecedent basis. As a result, the rejections of claims 11-12, and 14-19 are maintained by the Examiner, with claims 11-12 being rejected under 35 U.S.C. 103 as being dependent on claim 1, now rejected under Folmsbee in view of Sutton, and claims 14-19 being rejected under 35 U.S.C. 103 based on claim 13 as being unpatentable over Folmsbee in view of Sutton, Guri-1 and Guri-2.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. GB1818791.4, filed on November 19, 2018, and parent Application No. GB1818795.5, filed on November 19, 2018.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to because:
Figures 1-5 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
The unlabeled rectangular box(es) shown in the drawings Figs. 1-17 and 20 should be provided with descriptive text labels, without any text labels to clarify the figures themselves for the unlabeled boxes present in the aforementioned figures, a person of ordinary skill in the art would not be able to understand the necessary components of the invention, additional text would be helpful for a person of ordinary skill to understand the figures with “a labeled representation (e.g., a labeled rectangular box)”, and the invention of the Applicant, as stated in MPEP 608.02(d), “Complete Illustration in Drawings”, paragraph (a).
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3, 5, 8-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “compatible” in claim 1 is a relative term which renders the claim indefinite. The term “compatible” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term ‘compatible’ is not defined in the claim with regards as to what types of compilers would be compatible with changes to programmable elements of a processing module, and while paragraph [0195] recites the claim language, it does not provide examples of what a compatible compiler is intended to be with regards to varying to the processing module.
Claims 3, 5, 8-12 are dependent claims of independent claim 1, and dependent claims inherit the deficiencies of their respective independent claims. As a result, dependent claims 3, 5, 8-12 are also rejected under 35 U.S.C. 112(b) based on the indefiniteness rejection of independent claim 1.
Claim 5 recites the limitation "the ordering of bits" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites similar limitations as in claim 1 above, and as a result, the deficiencies of the independent claim 13 are inherited from independent claim 1.
Claims 14-19 are dependent claims of independent claim 13, and dependent claims inherit the deficiencies of their respective independent claims. As a result, dependent claims 14-19 are also rejected under 35 U.S.C. 112(b) based on the indefiniteness rejection of independent claim 13.
Claim 20 recites similar limitations as in claims 1 and 13 above, and as a result, the deficiencies of the independent claim 20 are inherited from independent claims 1 and 13.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites ‘varying at least one programmable element of the processing module using a first variation applied to the at least one programmable element to modify the processing module […]’ and ‘to enable only a compatible computer program executable compiled using a compatible compiler to be run using the processing module’ in lines 4-7, and are not sufficiently explained in the specification of the Applicant. The limitations in question do not satisfy the written description requirement under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph. The specification does not describe the limitation in sufficient detail so that one of ordinary skill in the art would recognize that the applicant had possession of the claimed invention. The only forms of support found within the specification to support the claimed functionality are in paragraphs [0042], [0043], [0246], and Figure 14.
Paragraph [0042] of the specification recites a first variation may be applied to at least one of opcodes of the central processing unit (CPU), the addressing modes of the CPU, the number, function, format or size of registers of the CPU, among other functions. There is no disclosure of an algorithm or method step regarding how the Inventor intended to first variation is to be applied to one of several elements (opcodes, addressing modes, number, function, format or size of registers) of the CPU.
Paragraph [0043] of the specification recites a first variation may also be the application of encryption to data stored in main memory by the central processing unit (CPU), may be applied to the ordering of bits stored in memory by the CPU, a change between little endian or big endian representations of data stored on the CPU, or applied to microcode on the CPU. There is no disclosure of an algorithm or method step regarding how the inventor intended to apply a first variation to the CPU.
Paragraphs [0246] and [0247] points toward Figure 14 for support and provide examples of algorithms for compatibility with a compiler with regards to a first variation, but still fail to disclose a method step or algorithm regarding how the claimed functionality of ‘computer program executable compiled using a compatible compiler to be run using the processing module’ is actually achieved.
Figure 2 is also deficient in providing support for the claim limitation as loader 31 retrieves files from a secondary storage 30 into main memory 45, as stated in paragraph [0248], of a flow-diagram which recites “computer program executable compiled using a compatible compiler to be run using the processing module”. This recitation fails to support the claim limitation because it merely repeats the claimed functionality and is silent with regards to how the computer program executable is made compatible with a compatible compiler that to be run using the processing module. Therefore, the specification is not commensurate with the full scope of the claims.
In MPEP 2161.01, "computer-implemented functional claim language must still be evaluated for sufficient disclosure under the written description".
Claim 3 recites the limitations of ‘wherein the first variation is the application of encryption to data stored in main memory by the central processing unit’ in the claim. In paragraphs [0043] and [0164] of the Specification of the Applicant, it is described that ‘CPU 2 is configured to use […] the use of encryption in the storage of data in main memory’ in [0164], but the Specification does not provide an indication as to what type of encryption of data is performed on the CPU.
Independent claim 13 recites similar claim limitations as independent claim 1 above, and as a result, inherit the deficiencies of independent claim 1 and is, therefore, rejected as well.
Independent claim 20 recites similar claim limitations as independent claims 1 and 13 above, and as a result, inherit the deficiencies of independent claims 1 and 13 and is, therefore, rejected as well.
Dependent claims 3, 5, 8-12, and 14-19 do not disclose any details which cure the deficiencies found in the claims they depend upon and are therefore rejected as well.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 8-10, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Folmsbee (US 6598166 B1), in view of Sutton et al. (US 20030229794 A1), hereinafter Sutton.
Regarding claim 1, Folmsbee discloses ‘a computer-implemented method of configuring a computer system comprising a processing module operable to run a computer program executable, the method comprising’ ([Col. 3, line 64-Col. 4, line 5] Security system of Folmsbee allows for software variations in memory. Configuration of logic architecture of a CPU is varied/changed according to keys, corresponding to varying at least one programmable element of a processing module of the Applicant. Furthermore, software compiled according to one key does not work with a CPU varied according to another key, corresponding to a computer program executable using a compiler to only be run using the respective processing module. [Col. 2, lines 17-20] Software can be executed on the system.):
‘varying at least one programmable element of the processing module using a first variation applied to the at least one programmable element to modify the processing module to enable only a compatible computer program executable compiled using a compatible compiler to be run using the processing module, wherein the processing module is a central processing unit,’ ([Col. 18, line 65-Col. 19, line 8] Compiler 41 is designed to comprehend all aspects of a CPU 11, with a key being shared across the compiler and CPU. Furthermore, in section [Col. 6, lines 10-18], software is executable on one microprocessor chip, in which software is compiled via a compiler to run on a modified processor. [Col. 21, lines 36-38] Data representation in a processor changes during execution of a program, corresponding to a first variation applied to at least one programmable element of the Applicant. [Col. 2, lines 53-55] Microprocessor CPU has ability to modify its operation in according with an encryption key.).
Folmsbee does not appear to disclose, but Sutton teaches the limitation of ‘and wherein the first variation disables or enables instructions in a control unit of the central processing unit’ ([0039] Modifications to processors can include new or modified instructions. In one embodiment, in Fig. 6, a "virtual machine monitor initialization" (VMMINIT) 624 can disable operations of a PSMBASE register 616 of CPU C 618 to support trusted SMM operations. VMMINIT corresponds to a first variation that disables instructions of a control unit of the CPU.).
Therefore, one of ordinary skill in the art would have been capable of applying this known method of ‘and wherein the first variation disables or enables instructions in a control unit of the central processing unit’ in a computer-implemented method for and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to disable operations of a PSMBASE register in a virtualized instance of a system to redirect all system management interrupts (SMIs) to the secured virtual machine monitor (SVMM) to permit or prevent direct access to hardware resources from an untrusted operations system, as taught by Sutton [0018] and [0023] (Sutton [0018], [0023]).
Regarding claim 3, Folmsbee in view of Sutton teaches the method of claim 1 as recited above. Folmsbee also discloses ‘wherein the first variation is the application of encryption to data stored in main memory by the central processing unit’ ([Col. 2, lines 53-55] Microprocessor CPU has ability to modify its operation in according with an encryption key. [Col. 2, lines 61-63] Modification of operations is done to predetermined memory stores of a processor.);
Regarding claim 5, Folmsbee in view of Sutton teaches the method of claims 1 and 2 as recited above. Folmsbee also discloses ‘wherein the first variation is applied to the ordering of bits stored in memory by the central processing unit’ ([Col. 8, lines 56-60] An instruction can be 128 bits/16 bytes wide, and wire crossings will permute the 128-bit instructions when compiler creates instruction, and CPU will reverse the wire crossing before utilizing op-codes, corresponding to varying order of bits stored in memory of the Applicant. [Col. 17, lines 7-8] RAM for data and instructions is part of CPU 11.);
Regarding claim 8, Folmsbee in view of Sutton teaches the method of claims 1 and 2 as recited above. Folmsbee also discloses ‘wherein the application of the first variation comprises the application of at least one arithmetic or logical operation to the programmable element of the central processing unit’ ([Col. 17, lines 30-35] Dynamically varying representations can be used for data processed in a CPU, and can be used with arithmetic or logical representations without decryption.);
Regarding claim 9, Folmsbee in view of Sutton teaches the method of claims 1, 2, and 8 as recited above. Folmsbee also discloses ‘wherein the application of at least one arithmetic or logical operation is based on a central processing configuration key used as an operand in the respective operation’ ([Col. 17, lines 30-35] Dynamically varying representations can be used for data processed in a CPU, and can be used with arithmetic or logical representations without decryption. [Col. 12, lines 18-33] Logic gates can be configured to change operations with a key, changing between AND, OR, ADD, and COMPARE. [Col. 17, lines 9-16] When two values are added, the two operands, which are values, can have extra bits that are not used, and the result is randomized. The extra bits configured to the values correspond to central processing configuration key of the Applicant, as the process is performed on the CPU.);
Regarding claim 10, Folmsbee in view of Sutton teaches the method of claims 1, and 8 as recited above. Folmsbee also discloses ‘wherein the at least one arithmetic or logical operation comprises a series of arithmetic or logical operations each based on a different operand’ ([Col. 12, line 64-Col. 13, line 7] Fig. 9, logical operation of A and B comprises of multiple arithmetic operations utilizing reconfigurable logic gates, performing different operands with correct and possibly incorrect answers for each. [Col. 17, lines 9-16] When two values are added, the two operands, which are values, can have extra bits that are not used, and the result is randomized.).
Regarding claim 20, Folmsbee in view of Sutton teaches similar limitations present in independent claim 1 above, and Folmsbee also discloses ‘a system for configuring a computer system comprising a processing module operable to run a computer program executable, the system configured to’ ([Col. 3, line 64-Col. 4, line 5] Security system of Folmsbee allows for software variations in memory. Configuration of logic architecture of a CPU is varied/changed according to keys, corresponding to varying at least one programmable element of a processing module of the Applicant. Furthermore, software compiled according to one key does not work with a CPU varied according to another key, corresponding to a computer program executable using a compiler to only be run using the respective processing module. [Col. 2, lines 17-20] Software can be executed on software. [Col. 3, lines 35-39] Microprocessor system for executing the encrypted software that was compiled, able to execute the software.):
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Folmsbee in view of Sutton, further in view of Ruff (US 20150378674 A1).
Regarding claim 11, Folmsbee in view of Sutton teaches the method of claims 1 as recited above. Folmsbee in view of Sutton does not appear to disclose, but Ruff teaches ‘wherein the processing module is a virtual machine’ ([0022] Executable is used to include code that can run on a virtual machine. A virtual machine can include the equivalent of virtual components, including a virtual processor equivalent of processor 112.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Folmsbee, Sutton, and Ruff before them, to include Ruff’s ‘wherein the processing module is a virtual machine’ in Folmsbee’s ‘computer-implemented method of configuring a computer system comprising a processing module operable to run a computer program executable’. One would have been motivated to make such a combination to increase efficiency by having instructions be executable by a processor 112, and this can be done by executing machine code, bytecode, or other types of code in a virtual machine to have another method for running and executing code of software, as taught by Ruff [0022].
Regarding claim 12, Folmsbee in view of Sutton teaches the method of claims 1 and 11 as recited above. Folmsbee in view of Sutton does not appear to fully disclose, but Ruff also teaches ‘wherein the programmable element is a module of a virtual central processing unit’ (Section [Col. 21, lines 36-38] of Folmsbee states that data representation in a processor changes during execution of a program. In combination with paragraph [0022] of Ruff describing a virtual machine that can be utilized, and a virtual machine can contain a virtual processor, teaches this limitation of the Applicant.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Folmsbee, Sutton, and Ruff before them, to include Ruff’s ‘wherein the programmable element is a module of a virtual central processing unit’ in Folmsbee’s ‘computer-implemented method of configuring a computer system comprising a processing module operable to run a computer program executable’. One would have been motivated to make such a combination to increase efficiency by having instructions be executable by a processor 112, and this can be done by executing machine code, bytecode, or other types of code in a virtual machine, and as a virtual machine contains all the necessary components as a real system, includes a virtual processor, as taught by Ruff [0022].
Claims 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Folmsbee in view of Sutton, Guri et al. (US 9703954 B2), hereinafter Guri-1, and Guri et al. (US 20180137280 A1), hereinafter Guri-2.
Regarding claim 13, Folmsbee in view of Sutton teaches similar limitations present in independent claim 1 above, and Folmsbee also discloses ‘a computer-implemented method of generating computer program executables which can be executed on a computer system, the computer system comprising a processing module operable to run a computer program executable, the method comprising’ ([Col. 3, line 64-Col. 4, line 5] Security system of Folmsbee allows for software variations in memory. Configuration of logic architecture of a CPU is varied/changed according to keys, corresponding to varying at least one programmable element of a processing module of the Applicant. Furthermore, software compiled according to one key does not work with a CPU varied according to another key, corresponding to a computer program executable using a compiler to only be run using the respective processing module. [Col. 2, lines 17-20] Software can be executed on software.):
Folmsbee in view of Sutton does not appear to teach the following limitations, but Guri-1 and Guri-2 teaches the following limitations of independent claim 13.
Guri-1 and Guri-2 teach ‘varying a compilation step of a compiler using a second variation to modify the compiler, wherein the second variation is compatible with the first variation’ (Guri-1's [Col. 12, lines 28-32] Modifications to essential elements involve modifications to a JIT compiler, and involve a compatible modification to bytecode used by a program, corresponding to a second variation applicable to a compiler of the Applicant. In combination with Guri-2’s [0059] Mutator 321 is part of a modified compiler 320, and the mutator is a modular part of the compiler, corresponding to varying a compilation step of the Applicant, teaches the limitation of this claim.);
‘and compiling a computer program written in a first programming language into a second programming language using the modified compiler to generate a computer program executable which can be run using the modified processing module’ (Guri-1's [Col. 10, lines 26-33] Fig. 7b, modified bytecode 7200 is processed by modified JIT compiler 7210, and is compiled into native machine code 7220, which can be executed normally. In combination with Guri-2’s [0059] Mutator 321 is part of a modified compiler 320, and the mutator is a modular part of the compiler, corresponding to varying a compilation step of the Applicant, teaches the limitation of this claim.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Folmsbee, Sutton, Guri-1 and Guri-2 before them, to include Guri-1 and Guri-2’s ‘varying a compilation step of a compiler using a second variation to modify the compiler, wherein the second variation is compatible with the first variation’ and ‘and compiling a computer program written in a first programming language into a second programming language using the modified compiler to generate a computer program executable which can be run using the modified processing module’ in Folmsbee’s ’computer-implemented method of generating computer program executables which can be executed on a computer system’. One would have been motivated to make such a combination to increase efficiency by modifying essential elements to disallow malicious programs to not run on the modified portions of a computer, including a modified operating system, with programs that were properly modified as well being able to run, as stated by Guri-1 [Col. 7, lines 7-15], and to increase efficiency by modifying a compiler that was previously included with a mutator via a mutation engine to alter a standard compiler to a non-standard compiler, as taught by Guri-2 [0034].
Regarding claim 14, Folmsbee in view of Sutton, Guri-1, and Guri-2 teaches the method of claim 13 as recited above. Folmsbee in view of Sutton does not appear to disclose, but Guri-2 teaches ‘wherein the second variation is applied to a code generation step of the compiler’ ([0059] Mutator 321 is part of a modified compiler 320, and the mutator is a modular part of the compiler. This aspect of Guri-2 corresponds to a second variation applied to code generation step of a compiler of the Applicant.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Folmsbee, Sutton, Guri-1 and Guri-2 before them, to include Guri-2’s ‘wherein the second variation is applied to the code generation step of the compiler’ in Folmsbee’s ’computer-implemented method of generating computer program executables which can be executed on a computer system’. One would have been motivated to make such a combination to increase efficiency by modifying a compiler that was previously included with a mutator via a mutation engine to alter a standard compiler to a non-standard compiler, as taught by Guri-2 [0034].
Regarding claim 15, Folmsbee in view of Sutton, Guri-1, and Guri-2 teaches the method of claim 13 as recited above. Folmsbee in view of Sutton does not appear to disclose, but Guri-1 teaches ‘wherein the second programming language is one of machine code or bytecode’ ([Col. 10, lines 26-33] Native machine code 7220 corresponds to a second programming language, that being machine code.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Folmsbee, Sutton, Guri-1 and Guri-2 before them, to include Guri-1’s ‘wherein the second programming language is one of machine code or bytecode’ in Folmsbee’s ’computer-implemented method of generating computer program executables which can be executed on a computer system’. One would have been motivated to make such a combination to increase efficiency by compiling a program with modified code to be processed by a system's processor by machine code that a machine can read and execute, as taught by Guri-1 [Col. 10, lines 26-33].
Regarding claim 16, Folmsbee in view of Sutton, Guri-1, and Guri-2 teaches the method of claim 13 as recited above. Folmsbee also discloses ‘wherein the application of the second variation comprises at least one arithmetic or logical operation’ ([Col. 17, lines 30-35] Dynamically varying representations can be used for data processed in a CPU, and can be used with arithmetic or logical representations without decryption. [Col. 12, lines 18-33] Logic gates can be configured to change operations with a key, changing between AND, OR, ADD, and COMPARE.).
Regarding claim 17, Folmsbee in view of Sutton, Guri-1, and Guri-2 teaches the method of claims 13 and 16 as recited above. Folmsbee also discloses ‘wherein the arithmetic or logical operation uses a variation key as an operand’ ([Col. 12, lines 18-33] Logic gates can be configured to change operations with a key, changing between AND, OR, ADD, and COMPARE. [Col. 17, lines 9-16] When two values are added, the two operands, which are values, can have extra bits that are not used, and the result is randomized. The extra bits configured to the values correspond to variation key of the Applicant, as the process is performed on the CPU.).
Regarding claim 18, Folmsbee in view of Sutton, Guri-1, and Guri-2 teaches the method of claims 13, 16, and 17 as recited above. Folmsbee also discloses ‘wherein the variation key is randomly generated or pseudo-randomly generated’ ([Col. 17, lines 9-16] When two values are added, two operands can have extra bits that are not used, and the result is randomized.).
Regarding claim 19, Folmsbee in view of Sutton, Guri-1, and Guri-2 teaches the method of claim 13 as recited above. Folmsbee in view of Sutton does not appear to disclose, but Guri-1 and Guri-2 teach ‘wherein the second variation is compatible with the first variation if the application of the second variation to the compiler modifies a part of a code generation step corresponding to the at least one programmable element modified by the first variation’ (Guri-1’s [Col. 10, lines 26-33] Fig. 7b, modified bytecode 7200 is processed by modified JIT compiler 7210, and is compiled into native machine code 7220, which can be executed normally. Guri-1’s [Col. 12, lines 28-32] Modifications to essential elements involve modifications to a JIT compiler, and involve a compatible modification to bytecode used by a program, corresponding to a second variation applicable to a compiler of the Applicant, and contains a first variation to a programmable element of the Applicant. In combination with Guri-2’s [0059] Mutator 321 is part of a modified compiler 320, and the mutator is a modular part of the compiler, corresponding to varying a compilation step of the Applicant.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Folmsbee, Sutton, Guri-1 and Guri-2 before them, to include Guri-1 and Guri-2’s ‘wherein the second variation is compatible with the first variation if the application of the second variation to the compiler modifies a part of the code generation step corresponding to the at least one programmable element modified by the first variation’ in Folmsbee’s ’computer-implemented method of generating computer program executables which can be executed on a computer system’. One would have been motivated to make such a combination to increase efficiency by modifying essential elements to disallow malicious programs to not run on the modified portions of a computer, including a modified operating system, with programs that were properly modified as well being able to run, as stated by Guri-1 [Col. 7, lines 7-15], and to increase efficiency by mofidying a compiler that was previously included with a mutator via a mutation engine to alter a standard compiler to a non-standard compiler, as taught by Guri-2 [0034].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/T.M./ Examiner, Art Unit 2496
/JORGE L ORTIZ CRIADO/Supervisory Patent Examiner, Art Unit 2496