Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 12, 2026 has been entered.
Response to Arguments
Applicant's arguments filed May 12, 2026 have been fully considered but they are not persuasive.
In page 1 of the remarks, Applicant states that the drawings of Figs. 1-5 are objected to as not being designated with the “Prior Art” label, and disagrees, pointing out that Figs. 1-5 contain more than “that which is old” as asserted to by the Office Action (“OA”). Furthermore, Figs. 1-17, and 20 were objected to as the figures “should be provided with descriptive text labels”, and requests clarification of the objection. The Applicant has submitted replacement sheets on May 12, 2026, and as a result of the “Prior Art” label being added for Figs. 1-5, and descriptive text labels provided for Figs. 1-17A and Fig. 20 were added, and as a result, the objections to the drawings for these figures are withdrawn.
In pages 1-2, Applicant states that claims 1, 5, and 8-20 were rejected under 35 U.S.C. § 112(b) (“112(b)”) as being indefinite for failing to particularly point out and distinctly claim the subject matter. In particular, the Office Action dated May 12, 2026 (“OA”) states that the term “compatible” is not defined in the claims in regards to what types of compilers would be compatible with changes to programmable elements of a processing module, with the claims amended to recite “wherein the compatible compiler and the compatible computer program executable are compatible when a particular variation applied to the compatible computer program executable is consistent with the plurality of variations applied to the at least one programmable element”, with support for the amendments found in paragraph [0170], with compatibility referring to the variation applied to the processing module (such as the variation described in paragraphs [0136] and [0137]). With regard to claim 5, the OA asserts insufficient antecedent basis for the limitation "the ordering of bits”, and amends claim 5 to recite “an ordering of bits” to traverse the rejection.
Examiner states that although the claims have been amended to specify what it means for a compiler and a computer program to be compatible means, it still does not provide sufficient detail as to how the computer program is made compatible with the modified processor when variation is applied, as described in paragraph [0170]. When viewing Fig. 6, showing transformation process 17a, steps S600-S612, in particular, steps S602-S606 of transforming the instructions to work with the variations to the processor applied, it does not describe, in sufficient detail, how the opcodes are modified by the table of instructions, as stated in paragraph [0134], even with an introduction of the variation key to the transformation process, in paragraph [0065]. Examiner maintains the rejection of 112(b) for the term “compatible”, as well as “consistent”, as how the modified computer program is consistent with the modified processor or compiler is not sufficiently described in the passages of the Specification described above. However, the 112(b) rejection for the limitation of “an ordering of bits”, which has been amended to remove the antecedent basis limitation rejection, has been withdrawn.
In pages 3-7 of the remarks, Applicant states that all of the pending claims were rejected under 35 U.S.C. § 112(a) (“112(a)”) as failing to comply with the written description requirement, with the OA claiming that the recitation in claim 1 of "varying at least one programmable element of the processing module using a first variation applied to the at least one programmable element to modify the processing module [...]" and "to enable only a compatible computer program executable compiled using a compatible compiler to be run using the processing module" are not sufficiently explained, and Applicant disagrees, citing paragraphs [0045]-[0046], [0131]-[0136], and [0139] of the Specification of the Applicant for support of the aforementioned limitation of "varying at least one programmable element of the processing module using a first variation applied […]", where Applicant further states that at least one arithmetic or logical operation is applied to each of the opcodes of a set of instructions for the CPU, and is performed to avoid collision, such as to add “1” to each of the opcodes, as stated in paragraph [0046]. In pages 5-7 of the remarks, Applicant cites paragraphs [0181], [0184], and [0249]-[0251] for support for the limitation of "to enable only a compatible computer program executable compiled using a compatible compiler to be run using the processing module". Applicant states that the paragraphs [0181] and [0184] describe a transformation process is applied to the machine code of the computer program executable corresponding to instructions validated on the modified CPU, and paragraph [0251] stating that the invalid opcodes are mapped to an interrupt module which "generates an interrupt during the running of a computer program executable which has one of the unused opcodes". As a result, Applicant requests withdrawal of the 112(a) rejections for claims 1, 5, and 8-20.
Examiner states that the amended limitation of “varying at least one programmable element of the processing module using a plurality of variations applied to the at least one programmable element to modify the processing module”, which is recited in paragraph [0170], Fig. 6, which displays transformation process 17a, steps S600-S612, in particular, steps S602-S606 of transforming the instructions to work with the variations to the processor applied, it does not describe, in sufficient detail, how the opcodes are modified by the table of instructions, as stated in paragraph [0134], even with an introduction of the variation key to the transformation process, in paragraph [0065]. While it is also described in paragraph [0046] that an arithmetic or logical operation, such as adding “1” to each of the opcodes so that only the compiler that generates computer program executables shifts all the output instructions by the compatible amount and can be run on the transformed processing module, it is not explained how the compatible computer program and compatible compiler communicate with one another. Also, the Examiner states that the amended limitation of “to enable only a compatible computer program executable compiled using a compatible compiler to be run using the processing module, wherein the compatible compiler and the compatible computer program executable are compatible when a particular variation applied to the compatible computer program executable is consistent with the plurality of variations applied to the at least one programmable element […]” is described in paragraphs [0249]-[0251], with a look-up table being utilizing with valid instructions used by the control unit, and an interrupt module is used to handle events that correspond to unused opcodes. As a result, Examiner maintains the 112(a) rejection of “varying at least one programmable element of the processing module using a plurality of variations applied to the at least one programmable element to modify the processing module”, as per the reasons described above.
In pages 8-9 of the remarks, Applicant states that claims 1, 5, 8-10, and 20 were rejected under 35 U.S.C. § 103 as being unpatentable as obvious over Folmsbee (U.S. Patent No. 6598166) in view of Sutton et al. (U.S. Patent Application Publication No. 2003/0229794). Claims 11 and 12 were rejected under 35 U.S.C. § 103 over Folmsbee in view of Sutton, and further in view of Ruff (U.S. Patent Application Publication No. 2015/0378674). Claims 13-19 were rejected under 35 U.S.C. § 103 in view of Folmsbee in view of Sutton, and further in view of Guri et al. (U.S. Patent No. 9,703,954) (hereinafter Guri-1) and Guri et al. (U.S. Patent Application Publication No. 2018/0137280) (hereinafter Guri-2). Applicant states that Folmsbee does not disclose "...varying at least one programmable element of the processing module using a plurality of variations applied to the at least one programmable element to modify....", or use of a key which determines various aspects of the compilation of a set of instructions, with Sutton also not teaching these limitations. Claims 13 and 20 recite similar limitations to claim 1, and requests withdrawal of the 103 rejections for claims 1, 5, 8-20.
Examiner states that as per the amended limitation of the independent claim 1, “varying at least one programmable element of the processing module using a plurality of variations applied to the at least one programmable element to modify the processing module to enable only a compatible computer program executable compiled using a compatible compiler to be run using the processing module, wherein the compatible compiler and the compatible computer program executable are compatible when a particular variation applied to the compatible computer program executable is consistent with the plurality of variations applied to the at least one programmable element, wherein the processing module is a central processing unit”, the passage of Folmsbee [Col. 6, lines 10-18], software is executable on one microprocessor chip, in which software is compiled via a compiler to run on a modified processor, where program instructions of the software are modified based on how the CPU was configured, such as operation codes ("op codes") being modified by the control circuit, as described in [Col. 2, lines 38-42], corresponding to consistency between the compatible computer program and the compatible compiler based on the modified programmable element of the processor. Furthermore, in [Col. 18, line 65-Col. 19, line 8] of Folmsbee, compiler 41 is designed to comprehend all aspects of a CPU 11, with a key being shared across the compiler and CPU, and in [Col. 3, lines 35-52], it is described in the invention of Folmsbee has a secure key that is used in configuring encrypted software with a compiler and microprocessor system executing the encrypted software so that the instructions from the compiler are only executable by the IC (integrated circuit) that uses the same key for the software, with the key located in RAM, as shown in Fig. 1 of Folmsbee, and as also stated in [Col. 11, lines 50-53], an encrypted key is sent to the software vendor so that a purchased program is compiled to produce instructions that only the given IC can execute the program. Therefore, Folmsbee describes the use of a key which determines various aspects of the compilation of a set of instructions for software. While Folmsbee does not appear to teach, the reference of Sutton teaches the limitations of “plurality of variations” in paragraph [0039] where modifications to processors include changes to behavior of registers, or new or modified instructions, and as there are at least two types of modifications described in the invention of Sutton, describes a “plurality of variations” for modification of the processor, and this is done to ensure to execute secure/trusted operations, as shown in Fig. 2 of Sutton, paragraph [0028]. As paragraph [0024] describes further, this is also performed so that the SVMM (secured virtual machine monitor) 250 permits or prevents direct access to hardware resources 280 from one or more trusted or secure kernels 260. As a result, Examiner maintains the 103 rejections based upon the claims’ respective rejections from the previous OA, including independent claim 1 remaining rejected over Folmsbee in view of Sutton.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. GB1818791.4, filed on November 19, 2018, and parent Application No. GB1818795.5, filed on November 19, 2018.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 5, 8-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The terms “compatible” and “consistent” in claim 1 are relative terms which renders the claim indefinite. The terms “compatible” and “consistent” are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term ‘compatible’ is not defined in the claim with regards as to what types of compilers would be compatible with changes to programmable elements of a processing module, and while paragraph [0195] recites the claim language, it does not provide examples of what a compatible compiler is intended to be with regards to varying to the processing module. Furthermore, how the modified computer program is ‘consistent’ with the modified processor or compiler is not sufficiently described in the passages of the Specification described above, including paragraphs [0180] and [0283], when in Fig. 6, showing transformation process 17a, steps S600-S612, in particular, steps S602-S606 of transforming the instructions to work with the variations to the processor applied, it does not describe, in sufficient detail, how the opcodes are modified by the table of instructions, as stated in paragraph [0134], even with an introduction of the variation key to the transformation process, in paragraph [0065].
Claims 5, 8-12 are dependent claims of independent claim 1, and dependent claims inherit the deficiencies of their respective independent claims. As a result, dependent claims 5, 8-12 are also rejected under 35 U.S.C. 112(b) based on the indefiniteness rejection of independent claim 1.
Claim 13 recites similar limitations as in claim 1 above, and as a result, the deficiencies of the independent claim 13 are inherited from independent claim 1.
Claims 14-19 are dependent claims of independent claim 13, and dependent claims inherit the deficiencies of their respective independent claims. As a result, dependent claims 14-19 are also rejected under 35 U.S.C. 112(b) based on the indefiniteness rejection of independent claim 13.
Claim 20 recites similar limitations as in claims 1 and 13 above, and as a result, the deficiencies of the independent claim 20 are inherited from independent claims 1 and 13.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 5, 8-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites ‘varying at least one programmable element of the processing module using a plurality of variations applied to the at least one programmable element to modify the processing module’ is not sufficiently explained in the specification of the Applicant. The limitations in question do not satisfy the written description requirement under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph. The specification does not describe the limitation in sufficient detail so that one of ordinary skill in the art would recognize that the applicant had possession of the claimed invention. The only forms of support found within the specification to support the claimed functionality are in paragraphs [0042], [0043], [0246], and Figure 14.
Paragraph [0042] of the specification recites a first variation may be applied to at least one of opcodes of the central processing unit (CPU), the addressing modes of the CPU, the number, function, format or size of registers of the CPU, among other functions. There is no disclosure of an algorithm or method step regarding how the Inventor intended to first variation is to be applied to one of several elements (opcodes, addressing modes, number, function, format or size of registers) of the CPU.
Paragraph [0043] of the specification recites a first variation may also be the application of encryption to data stored in main memory by the central processing unit (CPU), may be applied to the ordering of bits stored in memory by the CPU, a change between little endian or big endian representations of data stored on the CPU, or applied to microcode on the CPU. There is no disclosure of an algorithm or method step regarding how the inventor intended to apply a first variation to the CPU.
In steps S602-S606, Fig. 6, transforming the instructions to work with the variations to the processor applied, it does not describe, in sufficient detail, how the opcodes are modified by the table of instructions, as stated in paragraph [0134], even with an introduction of the variation key to the transformation process, in paragraph [0065]. While it is also described in paragraph [0046] that an arithmetic or logical operation, such as adding “1” to each of the opcodes so that only the compiler that generates computer program executables shifts all the output instructions by the compatible amount and can be run on the transformed processing module, it is not explained how the compatible computer program and compatible compiler communicate with one another.
Figure 2 is also deficient in providing support for the claim limitation as loader 31 retrieves files from a secondary storage 30 into main memory 45, as stated in paragraph [0248], of a flow-diagram which recites “computer program executable compiled using a compatible compiler to be run using the processing module”. This recitation fails to support the claim limitation because it merely repeats the claimed functionality and is silent with regards to how the computer program executable is made compatible with a compatible compiler that to be run using the processing module. Therefore, the specification is not commensurate with the full scope of the claims.
In MPEP 2161.01, "computer-implemented functional claim language must still be evaluated for sufficient disclosure under the written description".
Independent claim 13 recites similar claim limitations as independent claim 1 above, and as a result, inherit the deficiencies of independent claim 1 and is, therefore, rejected as well.
Independent claim 20 recites similar claim limitations as independent claims 1 and 13 above, and as a result, inherit the deficiencies of independent claims 1 and 13 and is, therefore, rejected as well.
Dependent claims 3, 5, 8-12, and 14-19 do not disclose any details which cure the deficiencies found in the claims they depend upon and are therefore rejected as well.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 8-10, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Folmsbee (US 6598166 B1), in view of Sutton et al. (US 20030229794 A1), hereinafter Sutton.
Regarding claim 1, Folmsbee discloses ‘a computer-implemented method of configuring a computer system comprising a processing module operable to run a computer program executable, the method comprising’ ([Col. 3, line 64-Col. 4, line 5] Security system of Folmsbee allows for software variations in memory. Configuration of logic architecture of a CPU is varied/changed according to keys, corresponding to varying at least one programmable element of a processing module of the Applicant. Furthermore, software compiled according to one key does not work with a CPU varied according to another key, corresponding to a computer program executable using a compiler to only be run using the respective processing module. [Col. 2, lines 17-20] Software can be executed on the system.):
‘varying at least one programmable element of the processing module using a variation applied to the at least one programmable element to modify the processing module to enable only a compatible computer program executable compiled using a compatible compiler to be run using the processing module, wherein the compatible compiler and the compatible computer program executable are compatible when a particular variation applied to the compatible computer program executable is consistent with the variations applied to the at least one programmable element, wherein the processing module is a central processing unit,’ ([Col. 18, line 65-Col. 19, line 8] Compiler 41 is designed to comprehend all aspects of a CPU 11, with a key being shared across the compiler and CPU. Furthermore, in section [Col. 6, lines 10-18], software is executable on one microprocessor chip, in which software is compiled via a compiler to run on a modified processor, where program instructions of the software are modified based on how the CPU was configured, such as operation codes ("op codes") being modified by the control circuit, as described in [Col. 2, lines 38-42], corresponding to consistency between the compatible computer program and the compatible compiler based on the modified programmable element of the processor. [Col. 21, lines 36-38] Data representation in a processor changes during execution of a program, corresponding to a first variation applied to at least one programmable element of the Applicant. [Col. 2, lines 53-55] Microprocessor CPU has ability to modify its operation in according with an encryption key.).
Folmsbee does not appear to disclose, but Sutton teaches the limitation of “plurality of variations” ([0039] Modifications to processors include changes to behavior of registers, such as the SMBASE register of each processor in the system as described in paragraph [0021], or new or modified instructions. As there are at least two types of modifications listed, this corresponds to a plurality of variations on the processors.);
‘and wherein the plurality of variations disables or enables instructions in a control unit of the central processing unit’ ([0039] Modifications to processors can include new or modified instructions. In one embodiment, in Fig. 6, a "virtual machine monitor initialization" (VMMINIT) 624 can disable operations of a PSMBASE register 616 of CPU C 618 to support trusted SMM operations. VMMINIT corresponds to a first variation that disables instructions of a control unit of the CPU.).
Therefore, one of ordinary skill in the art would have been capable of applying this known method of “plurality of variations” and ‘wherein the first variation disables or enables instructions in a control unit of the central processing unit’ in a computer-implemented method for configuring a computer system comprising a processing module operable to run a computer program executable and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to disable operations of a PSMBASE register in a virtualized instance of a system to redirect all system management interrupts (SMIs) to the secured virtual machine monitor (SVMM) to permit or prevent direct access to hardware resources from an untrusted operations system, as taught by Sutton [0018] and [0023] (Sutton [0018], [0023]).
Regarding claim 5, Folmsbee in view of Sutton teaches the method of claims 1 and 2 as recited above. Folmsbee also discloses ‘wherein the variations is applied to an ordering of bits stored in memory by the central processing unit’ ([Col. 8, lines 56-60] An instruction can be 128 bits/16 bytes wide, and wire crossings will permute the 128-bit instructions when compiler creates instruction, and CPU will reverse the wire crossing before utilizing op-codes, corresponding to varying order of bits stored in memory of the Applicant. [Col. 17, lines 7-8] RAM for data and instructions is part of CPU 11.);
Folmsbee does not appear to disclose, but Sutton teaches the limitation of “plurality of variations” ([0039] Modifications to processors include changes to behavior of registers, such as the SMBASE register of each processor in the system as described in paragraph [0021], or new or modified instructions. As there are at least two types of modifications listed, this corresponds to a plurality of variations on the processors.);
Therefore, one of ordinary skill in the art would have been capable of applying this known method of "plurality of variations" in a computer-implemented method for configuring a computer system comprising a processing module operable to run a computer program executable and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to ensure execution of secure/trusted operations, as shown in Fig. 2 of Sutton, paragraph [0028]. As paragraph [0024] of Sutton describes further, this is also performed so that the SVMM (secured virtual machine monitor) 250 permits or prevents direct access to hardware resources 280 from one or more trusted or secure kernels 260.
Regarding claim 8, Folmsbee in view of Sutton teaches the method of claims 1 and 2 as recited above. Folmsbee also discloses ‘wherein the application of the variations comprises the application of at least one arithmetic or logical operation to the programmable element of the central processing unit’ ([Col. 17, lines 30-35] Dynamically varying representations can be used for data processed in a CPU, and can be used with arithmetic or logical representations without decryption.);
Folmsbee does not appear to disclose, but Sutton teaches the limitation of “plurality of variations” ([0039] Modifications to processors include changes to behavior of registers, such as the SMBASE register of each processor in the system as described in paragraph [0021], or new or modified instructions. As there are at least two types of modifications listed, this corresponds to a plurality of variations on the processors.);
Therefore, one of ordinary skill in the art would have been capable of applying this known method of "plurality of variations" in a computer-implemented method for configuring a computer system comprising a processing module operable to run a computer program executable and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to ensure execution of secure/trusted operations, as shown in Fig. 2 of Sutton, paragraph [0028]. As paragraph [0024] of Sutton describes further, this is also performed so that the SVMM (secured virtual machine monitor) 250 permits or prevents direct access to hardware resources 280 from one or more trusted or secure kernels 260.
Regarding claim 9, Folmsbee in view of Sutton teaches the method of claims 1, 2, and 8 as recited above. Folmsbee also discloses ‘wherein the application of at least one arithmetic or logical operation is based on a central processing configuration key used as an operand in the respective operation’ ([Col. 17, lines 30-35] Dynamically varying representations can be used for data processed in a CPU, and can be used with arithmetic or logical representations without decryption. [Col. 12, lines 18-33] Logic gates can be configured to change operations with a key, changing between AND, OR, ADD, and COMPARE. [Col. 17, lines 9-16] When two values are added, the two operands, which are values, can have extra bits that are not used, and the result is randomized. The extra bits configured to the values correspond to central processing configuration key of the Applicant, as the process is performed on the CPU.);
Regarding claim 10, Folmsbee in view of Sutton teaches the method of claims 1, and 8 as recited above. Folmsbee also discloses ‘wherein the at least one arithmetic or logical operation comprises a series of arithmetic or logical operations each based on a different operand’ ([Col. 12, line 64-Col. 13, line 7] Fig. 9, logical operation of A and B comprises of multiple arithmetic operations utilizing reconfigurable logic gates, performing different operands with correct and possibly incorrect answers for each. [Col. 17, lines 9-16] When two values are added, the two operands, which are values, can have extra bits that are not used, and the result is randomized.).
Regarding claim 20, Folmsbee in view of Sutton teaches similar limitations present in independent claim 1 above, and Folmsbee also discloses ‘a system for configuring a computer system comprising a processing module operable to run a computer program executable, the system configured to’ ([Col. 3, line 64-Col. 4, line 5] Security system of Folmsbee allows for software variations in memory. Configuration of logic architecture of a CPU is varied/changed according to keys, corresponding to varying at least one programmable element of a processing module of the Applicant. Furthermore, software compiled according to one key does not work with a CPU varied according to another key, corresponding to a computer program executable using a compiler to only be run using the respective processing module. [Col. 2, lines 17-20] Software can be executed on software. [Col. 3, lines 35-39] Microprocessor system for executing the encrypted software that was compiled, able to execute the software.):
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Folmsbee in view of Sutton, further in view of Ruff (US 20150378674 A1).
Regarding claim 11, Folmsbee in view of Sutton teaches the method of claims 1 as recited above. Folmsbee in view of Sutton does not appear to disclose, but Ruff teaches ‘wherein the processing module is a virtual machine’ ([0022] Executable is used to include code that can run on a virtual machine. A virtual machine can include the equivalent of virtual components, including a virtual processor equivalent of processor 112.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Folmsbee, Sutton, and Ruff before them, to include Ruff’s ‘wherein the processing module is a virtual machine’ in Folmsbee’s ‘computer-implemented method of configuring a computer system comprising a processing module operable to run a computer program executable’. One would have been motivated to make such a combination to increase efficiency by having instructions be executable by a processor 112, and this can be done by executing machine code, bytecode, or other types of code in a virtual machine to have another method for running and executing code of software, as taught by Ruff [0022].
Regarding claim 12, Folmsbee in view of Sutton teaches the method of claims 1 and 11 as recited above. Folmsbee in view of Sutton does not appear to fully disclose, but Ruff also teaches ‘wherein the programmable element is a module of a virtual central processing unit’ (Section [Col. 21, lines 36-38] of Folmsbee states that data representation in a processor changes during execution of a program. In combination with paragraph [0022] of Ruff describing a virtual machine that can be utilized, and a virtual machine can contain a virtual processor, teaches this limitation of the Applicant.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Folmsbee, Sutton, and Ruff before them, to include Ruff’s ‘wherein the programmable element is a module of a virtual central processing unit’ in Folmsbee’s ‘computer-implemented method of configuring a computer system comprising a processing module operable to run a computer program executable’. One would have been motivated to make such a combination to increase efficiency by having instructions be executable by a processor 112, and this can be done by executing machine code, bytecode, or other types of code in a virtual machine, and as a virtual machine contains all the necessary components as a real system, includes a virtual processor, as taught by Ruff [0022].
Claims 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Folmsbee in view of Sutton, Guri et al. (US 9703954 B2), hereinafter Guri-1, and Guri et al. (US 20180137280 A1), hereinafter Guri-2.
Regarding claim 13, Folmsbee in view of Sutton teaches similar limitations present in independent claim 1 above, and Folmsbee also discloses ‘a computer-implemented method of generating computer program executables which can be executed on a computer system, the computer system comprising a processing module operable to run a computer program executable, the method comprising’ ([Col. 3, line 64-Col. 4, line 5] Security system of Folmsbee allows for software variations in memory. Configuration of logic architecture of a CPU is varied/changed according to keys, corresponding to varying at least one programmable element of a processing module of the Applicant. Furthermore, software compiled according to one key does not work with a CPU varied according to another key, corresponding to a computer program executable using a compiler to only be run using the respective processing module. [Col. 2, lines 17-20] Software can be executed on software.):
Folmsbee in view of Sutton does not appear to teach the following limitations, but Guri-1 and Guri-2 teaches the following limitations of independent claim 13.
Guri-1 and Guri-2 teach ‘varying a compilation step of the compatible compiler using the second variation to modify the compatible compiler, wherein the second variation is consistent with the variations’ (Guri-1's [Col. 12, lines 28-32] Modifications to essential elements involve modifications to a JIT compiler, and involve a compatible modification to bytecode used by a program, corresponding to a second variation applicable to a compiler of the Applicant. In combination with Guri-2’s [0059] Mutator 321 is part of a modified compiler 320, and the mutator is a modular part of the compiler, corresponding to varying a compilation step of the Applicant, teaches the limitation of this claim.);
‘and compiling a computer program written in a first programming language into a second programming language using the modified compatible compiler to generate a modified computer program executable which can be run using the modified processing module’ (Guri-1's [Col. 10, lines 26-33] Fig. 7b, modified bytecode 7200 is processed by modified JIT compiler 7210, and is compiled into native machine code 7220, which can be executed normally. In combination with Guri-2’s [0059] Mutator 321 is part of a modified compiler 320, and the mutator is a modular part of the compiler, corresponding to varying a compilation step of the Applicant, teaches the limitation of this claim.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Folmsbee, Sutton, Guri-1 and Guri-2 before them, to include Guri-1 and Guri-2’s ‘varying a compilation step of a compiler using a second variation to modify the compiler, wherein the second variation is compatible with the first variation’ and ‘and compiling a computer program written in a first programming language into a second programming language using the modified compiler to generate a computer program executable which can be run using the modified processing module’ in Folmsbee’s ’computer-implemented method of generating computer program executables which can be executed on a computer system’. One would have been motivated to make such a combination to increase efficiency by modifying essential elements to disallow malicious programs to not run on the modified portions of a computer, including a modified operating system, with programs that were properly modified as well being able to run, as stated by Guri-1 [Col. 7, lines 7-15], and to increase efficiency by modifying a compiler that was previously included with a mutator via a mutation engine to alter a standard compiler to a non-standard compiler, as taught by Guri-2 [0034].
Folmsbee, Guri-1 and Guri-2 do not appear to disclose, but Sutton teaches the limitation of “plurality of variations” ([0039] Modifications to processors include changes to behavior of registers, such as the SMBASE register of each processor in the system as described in paragraph [0021], or new or modified instructions. As there are at least two types of modifications listed, this corresponds to a plurality of variations on the processors.);
Therefore, one of ordinary skill in the art would have been capable of applying this known method of "plurality of variations" in a computer-implemented method for configuring a computer system comprising a processing module operable to run a computer program executable and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to ensure execution of secure/trusted operations, as shown in Fig. 2 of Sutton, paragraph [0028]. As paragraph [0024] of Sutton describes further, this is also performed so that the SVMM (secured virtual machine monitor) 250 permits or prevents direct access to hardware resources 280 from one or more trusted or secure kernels 260.
Regarding claim 14, Folmsbee in view of Sutton, Guri-1, and Guri-2 teaches the method of claim 13 as recited above. Folmsbee in view of Sutton does not appear to disclose, but Guri-2 teaches ‘wherein the second variation is applied to a code generation step of the compatible compiler’ ([0059] Mutator 321 is part of a modified compiler 320, and the mutator is a modular part of the compiler. This aspect of Guri-2 corresponds to a second variation applied to code generation step of a compiler of the Applicant.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Folmsbee, Sutton, Guri-1 and Guri-2 before them, to include Guri-2’s ‘wherein the second variation is applied to the code generation step of the compiler’ in Folmsbee’s ’computer-implemented method of generating computer program executables which can be executed on a computer system’. One would have been motivated to make such a combination to increase efficiency by modifying a compiler that was previously included with a mutator via a mutation engine to alter a standard compiler to a non-standard compiler, as taught by Guri-2 [0034].
Regarding claim 15, Folmsbee in view of Sutton, Guri-1, and Guri-2 teaches the method of claim 13 as recited above. Folmsbee in view of Sutton does not appear to disclose, but Guri-1 teaches ‘wherein the second programming language is one of machine code or bytecode’ ([Col. 10, lines 26-33] Native machine code 7220 corresponds to a second programming language, that being machine code.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Folmsbee, Sutton, Guri-1 and Guri-2 before them, to include Guri-1’s ‘wherein the second programming language is one of machine code or bytecode’ in Folmsbee’s ’computer-implemented method of generating computer program executables which can be executed on a computer system’. One would have been motivated to make such a combination to increase efficiency by compiling a program with modified code to be processed by a system's processor by machine code that a machine can read and execute, as taught by Guri-1 [Col. 10, lines 26-33].
Regarding claim 16, Folmsbee in view of Sutton, Guri-1, and Guri-2 teaches the method of claim 13 as recited above. Folmsbee also discloses ‘wherein the application of the second variation comprises at least one arithmetic or logical operation’ ([Col. 17, lines 30-35] Dynamically varying representations can be used for data processed in a CPU, and can be used with arithmetic or logical representations without decryption. [Col. 12, lines 18-33] Logic gates can be configured to change operations with a key, changing between AND, OR, ADD, and COMPARE.).
Regarding claim 17, Folmsbee in view of Sutton, Guri-1, and Guri-2 teaches the method of claims 13 and 16 as recited above. Folmsbee also discloses ‘wherein the arithmetic or logical operation uses a variation key as an operand’ ([Col. 12, lines 18-33] Logic gates can be configured to change operations with a key, changing between AND, OR, ADD, and COMPARE. [Col. 17, lines 9-16] When two values are added, the two operands, which are values, can have extra bits that are not used, and the result is randomized. The extra bits configured to the values correspond to variation key of the Applicant, as the process is performed on the CPU.).
Regarding claim 18, Folmsbee in view of Sutton, Guri-1, and Guri-2 teaches the method of claims 13, 16, and 17 as recited above. Folmsbee also discloses ‘wherein the variation key is randomly generated or pseudo-randomly generated’ ([Col. 17, lines 9-16] When two values are added, two operands can have extra bits that are not used, and the result is randomized.).
Regarding claim 19, Folmsbee in view of Sutton, Guri-1, and Guri-2 teaches the method of claim 13 as recited above. Folmsbee in view of Sutton does not appear to disclose, but Guri-1 and Guri-2 teach ‘wherein the second variation is compatible with the first variation if the application of the second variation to the compiler modifies a part of a code generation step corresponding to the at least one programmable element modified by the first variation’ (Guri-1’s [Col. 10, lines 26-33] Fig. 7b, modified bytecode 7200 is processed by modified JIT compiler 7210, and is compiled into native machine code 7220, which can be executed normally. Guri-1’s [Col. 12, lines 28-32] Modifications to essential elements involve modifications to a JIT compiler, and involve a compatible modification to bytecode used by a program, corresponding to a second variation applicable to a compiler of the Applicant, and contains a first variation to a programmable element of the Applicant. In combination with Guri-2’s [0059] Mutator 321 is part of a modified compiler 320, and the mutator is a modular part of the compiler, corresponding to varying a compilation step of the Applicant.).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Folmsbee, Sutton, Guri-1 and Guri-2 before them, to include Guri-1 and Guri-2’s ‘wherein the second variation is compatible with the first variation if the application of the second variation to the compiler modifies a part of the code generation step corresponding to the at least one programmable element modified by the first variation’ in Folmsbee’s ’computer-implemented method of generating computer program executables which can be executed on a computer system’. One would have been motivated to make such a combination to increase efficiency by modifying essential elements to disallow malicious programs to not run on the modified portions of a computer, including a modified operating system, with programs that were properly modified as well being able to run, as stated by Guri-1 [Col. 7, lines 7-15], and to increase efficiency by mofidying a compiler that was previously included with a mutator via a mutation engine to alter a standard compiler to a non-standard compiler, as taught by Guri-2 [0034].
Folmsbee, Guri-1 and Guri-2 do not appear to disclose, but Sutton teaches the limitation of “plurality of variations” ([0039] Modifications to processors include changes to behavior of registers, such as the SMBASE register of each processor in the system as described in paragraph [0021], or new or modified instructions. As there are at least two types of modifications listed, this corresponds to a plurality of variations on the processors.);
Therefore, one of ordinary skill in the art would have been capable of applying this known method of "plurality of variations" in a computer-implemented method for configuring a computer system comprising a processing module operable to run a computer program executable and the results would have been predictable to one of ordinary skill in the art. The one of ordinary skill in the art would have been motivated to ensure execution of secure/trusted operations, as shown in Fig. 2 of Sutton, paragraph [0028]. As paragraph [0024] of Sutton describes further, this is also performed so that the SVMM (secured virtual machine monitor) 250 permits or prevents direct access to hardware resources 280 from one or more trusted or secure kernels 260.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lukacs et al. (US 20150013008 A1, “Process Evaluation For Malware Detection In Virtual Machines”)
Candelore et al. (US 20040158721 A1, “System, Method And Apparatus For Secure Digital Content Transmission”)
Nojiri et al. (US 20110131657 A1, “HOOKING NONEXPORTED FUNCTIONS BY THE OFFSET OF THE FUNCTION”)
Cosgrove et al. (US 20220360594 A1, “MITIGATING THREATS ASSOCIATED WITH TAMPERING ATTEMPTS”)
Andión et al. (NPL, “A novel compiler support for automatic parallelization on multicore systems”, 2013)
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/T.M./Examiner, Art Unit 2496
/JORGE L ORTIZ CRIADO/Supervisory Patent Examiner, Art Unit 2496
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