DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/14/2024, 09/18/2024, 10/25/2024, and 11/21/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Claim Objections
Claims 6 and 16-20 are objected to because of the following informalities:
Claim 6 recites “wherein the capacitor bank is formed with respect to a ground plane on a first side of the bias line, further comprising a second capacitor bank…..”. This should be amended to clarify that the reconfigurable intelligent surface further comprises a second capacitor bank.
Claim 16 (lines 9-10) recites “a first capacitor bank connected to the first bias line with a first switch, wherein the second capacitor bank comprises selectable capacitors”. “The second capacitor bank” should be corrected to “the first capacitor bank”.
Appropriate correction is required.
Claims 17-20 are objected to due to their dependency on claim 16.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites “wherein the second bias line is connected with a capacitor bank through a third switch formed of a chalcogenide material”. However, it is not clear if this capacitor bank refers to the capacitor bank of claim 1, or a different capacitor bank. Clarification is required.
Allowable Subject Matter
Claims 1-8 and 10-20 are allowable.
Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Regarding claim 1, IDS document “Metasurface with Reconfigurable Reflection Phase for High-Power Microwave Applications” (hereinafter NPL_Morgan) discloses (figs. 1&2 shown below) “a reconfigurable intelligent surface (metasurface with reconfigurable reflection phase) comprising:
a substrate (p. 1230, “the printed circuit board structure”) comprising a plurality of unit cells (p. 1230, “The PCB structure features a top layer of periodically arranged circular metallic patches”), wherein each of the unit cells comprises:
a metal element formed on a first surface of the substrate (p. 1230, “circular metal patches”) and configured to be resonant with a frequency or a range of frequencies (p. 1230, “Respective geometries [of the circular patches] are selected to optimize for a desired frequency”);
a radio frequency component connected with the metal element (fig. 2, and p. 1231, “using PIN diode controlled capacitor networks as the tuning mechanism”. The PIN diodes are connected with the metal elements via the capacitors); and
a capacitor bank (capacitors C0, C1, C2….CN), wherein the capacitor bank comprises selectable capacitors (p. 1231, “the PIN diodes effectively act as electrically controlled switches”)”.
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NPL_Morgan does not teach, or suggest, “a bias line formed on a second surface of the substrate; and the capacitor bank is connected to the bias line with a first switch”.
Regarding claim 1, IDS document Gupta et al. (US 2023/0352834; hereinafter Gupta) discloses (fig. 1, fig. 3E shown below, & fig. 21) “A reconfigurable intelligent surface (¶121, “smart metasurface reflectarray”, ¶6, “a reflective unit cells with independently controllable parameters allows for control of the magnitude and phase of the reflected wave”) comprising:
a substrate (fig. 1, metasurface reflector) comprising a plurality of unit cells (¶67, “the reflective surface can consist of an arbitrary number of unit cells forming an array”), wherein each of the unit cells comprises:
a metal element (fig. 3E, resonator) formed on a first surface of the substrate (upper surface of layer 1) and configured to be resonant with a frequency or a range of frequencies (figs. 3B & 3C; ¶66, “the unit cell can be operated at one of these resonant frequencies”);
a radio frequency component (fig. 3E, PIN diode) connected with the metal element (resonator);
a bias line formed on a second surface of the substrate (fig. 21 shows a bias-T configuration on the bottom view of the resonator)”.
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Gupta does not teach, or suggest, “a capacitor bank connected to the bias line with a first switch, wherein the capacitor bank comprises selectable capacitors”.
Claims 2-8 and 10-15 are allowable due to their dependency on claim 1.
Regarding claim 16, NPL_Morgan discloses (figs. 1&2) “a reconfigurable intelligent surface (metasurface with reconfigurable reflection phase) comprising:
a substrate (p. 1230, “the printed circuit board structure”) comprising a plurality of unit cells (p. 1230, “The PCB structure features a top layer of periodically arranged circular metallic patches”), wherein each of the unit cells comprises:
a metal element formed on a first surface of the substrate (p. 1230, “circular metal patches”) and configured to be resonant with a frequency or a range of frequencies (p. 1230, “Respective geometries [of the circular patches] are selected to optimize for a desired frequency”);
a radio frequency component connected with the metal element (fig. 2, and p. 1231, “using PIN diode controlled capacitor networks as the tuning mechanism”. The PIN diodes are connected with the metal elements via the capacitors); and
a first capacitor bank (capacitors C0, C1, C2….CN), wherein the first capacitor bank comprises selectable capacitors that are each associated with a switch (p. 1231, “the PIN diodes effectively act as electrically controlled switches”. Fig. 2 shows that each selectable capacitor C1-CN is associated with a PIN diode);
a second capacitor bank (multiple capacitor networks are shown in fig. 1), wherein the second capacitor bank comprises selectable capacitors that are each associated with a switch”.
NPL_Morgan does not teach, or suggest, “a first bias line formed on a second surface of the substrate; a second bias line formed on the second surface; and the first capacitor bank is connected to the first bias line with a first switch; and the second capacitor bank is connected to the second bias line with a second switch”.
Regarding claim 16, Gupta discloses (fig. 1, fig. 3E & fig. 21) “A reconfigurable intelligent surface (¶121, “smart metasurface reflectarray”, ¶6, “a reflective unit cells with independently controllable parameters allows for control of the magnitude and phase of the reflected wave”) comprising:
a substrate (fig. 1, metasurface reflector) comprising a plurality of unit cells (¶67, “the reflective surface can consist of an arbitrary number of unit cells forming an array”), wherein each of the unit cells comprises:
a metal element (fig. 3E, resonator) formed on a first surface of the substrate (upper surface of layer 1) and configured to be resonant with a frequency or a range of frequencies (figs. 3B & 3C; ¶66, “the unit cell can be operated at one of these resonant frequencies”);
a radio frequency component (fig. 3E, PIN diode) connected with the metal element (resonator);
a first bias line formed on a second surface of the substrate;
a second bias line formed on the second surface of the substrate (fig. 21 shows two bias lines on the bottom view of the resonator)”.
Gupta does not teach, or suggest, “a first capacitor bank connected to the first bias line with a first switch, wherein the first capacitor bank comprises selectable capacitors that are each associated with a switch; a second capacitor bank connected to the second bias line with a second switch, wherein the second capacitor bank comprises selectable capacitors that are each associated with a switch”.
Claims 17-20 are allowable due to their dependency on claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wu et al. (“Programmable terahertz chip-scale sensing interface with direct digital reconfiguration at sub-wavelength scales”) disclose (see fig. 1 below) a reconfigurable intelligent surface (THz surface) comprising a capacitor bank.
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Kim et al. (KR20180076359A) disclose “an active meta-material device capable of frequency selection in a wireless charging system and a wireless power transfer system using the same. A variable capacitor capable of varying the capacitance of the meta-material device and an adaptive capacitance control unit capable of varying the capacitance thereof are introduced. By adjusting the capacitance of the variable capacitor, the resonance frequency may be actively varied to refract an incident magnetic field in a desired direction to form a beam in a desired shape.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANNA N HAMADYK whose telephone number is (703)756-1672. The examiner can normally be reached 7:30 am - 5:00 pm.
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/ANNA N HAMADYK/Examiner, Art Unit 2845
/HOANG V NGUYEN/Primary Examiner, Art Unit 2845