DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) (177 U.S. Patents Documents) submitted on December 4, 2023 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) (196 U.S. Patents Applications Publications and 41 Foreign Patent Documents) submitted on December 4, 2023 was in compliance with the provisions of 37 CFR 1.97, except the Foreign Patent Documents JP 2013230034 A, JP 2014030355 A, and JP 06053779 A that fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in § 1.56(c) most knowledgeable about the content of the information, of each patent, publication, or other information listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
Examiner’s Note: As a courtesy and for applicant’s convenience the Foreign Patent Documents and machine translations of the non-English documents JP 2013230034 A, JP 2014030355 A, and JP 06053779 A have been attached to the current Office Action.
Drawings
The drawings were received on November 29, 2023. These drawings are acceptable.
Examination Notice
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 6-9, and 15-18 are rejected under 35 U.S.C. 102 (a)(1) and 35 U.S.C. 102 (a)(2) as being anticipated by Telefus (US WO 2021/112870 A1) (IDS Record).
With regard to claim 1, Telefus teaches a device (Fig. 2, Fig. 5) (Abstract, line 1), comprising:
current sense circuitry (201, 202 – Fig. 2) configured to sense a first current flowing in a first wire (103 – Fig. 2) and to sense a second current flowing in a second wire (104 – Fig. 2), the first and second wires (103, 104 – Fig. 2) being configured to supply alternative current (AC) power (101 – Fig. 2) to a load (102 – Fig. 2) coupled to the device;
analog-to-digital converter circuitry (504 – Fig. 5) configured to generate first digital data (signal conducted via bidirectional digital line 210 – Fig. 2, Fig. 5) corresponding to the first current (page 10, lines 16-25, “digital signal”), and to generate second digital (signal conducted via bidirectional digital line 211 – Fig. 2, Fig. 5) data corresponding to the second current (page 10, lines 16-25, “digital signal”); and
digital signal processing circuitry (206 – Fig. 2) configured to (i) process the first digital data (first digital data conducted via bidirectional digital line 210 – Fig. 2, Fig. 5) and the second digital data (second digital data conducted via bidirectional digital line 211 – Fig. 2, Fig. 5) to determine a difference between the first current and the second current (page 9, lines 5-12), and (ii) generate a control signal to interrupt current flow (by opening 111A, 111B – Fig. 2) in the first and second wires (103, 104 – Fig. 2), in response to determining that the difference between the first current and the second current meets or exceeds a difference threshold (claim 1, lines 13-19; page 9, lines 5-12; page 8, lines 3-7; page 8, lines 23-28).
With regard to claim 4, Telefus teaches all the limitations of claim 1, and further teaches the current sense circuitry (201, 202 – Fig. 2; Fig. 5) comprises:
a first current sense resistor (501 – Fig. 5) configured to generate a first sense voltage which corresponds to the first current flowing in the first wire (103 – Fig. 2) (page 10, lines 16-20); and
a second current sense resistor (502 – Fig. 5) configured to generate a second sense voltage which corresponds to the first current flowing in the second wire (104 – Fig. 2) (103 – Fig. 2) (page 10, lines 16-20).
With regard to claim 6, Telefus teaches all the limitations of claim 4, and further teaches the analog-to-digital converter circuitry (504 – Fig. 5) comprises:
a first analog-to-digital converter circuit (504 – Fig. 5) (first analog-to-digital converter circuit in current sensing 201 – Fig. 5) configured to digitize the first sense voltage to generate the first digital data (page 10, lines 16-25); and
a second analog-to-digital converter circuit (504 – Fig. 5) (first analog-to-digital converter circuit in current sensing 202 – Fig. 5) configured to digitize the second sense voltage to generate the second digital data (page 10, lines 16-25).
With regard to claim 7, Telefus teaches all the limitations of claim 1, and further teaches the device comprises a ground fault circuit interrupter outlet device (Abstract, line1; page 21, lines 2-6).
With regard to claim 8, Telefus teaches all the limitations of claim 1, and further teaches the device comprises a ground fault circuit interrupter circuit breaker device (Abstract, line 1; page 1, lines 12-13).
With regard to claim 9, Telefus teaches a device (Fig. 2, Fig. 5) (Abstract, line 1), comprising:
a first electrical path (103 – Fig. 2) and a second electrical path (102 – Fig. 2) configured to supply alternative current (AC) power (101 – Fig. 2) to a load (102 – Fig. 2) coupled to the device;
a first current sense resistor (501 – Fig. 5) configured to generate a first sense voltage corresponding to a first current flowing in the first electrical path (103 – Fig. 2) (page 10, lines 16-20);
a second current sense resistor (502 – Fig. 5) configured to generate a second sense voltage corresponding to a second current flowing in the second electrical path (104 – Fig. 2) (page 10, lines 16-20);
a first analog-to-digital converter circuit (504 – Fig. 5) (first analog-to-digital converter circuit in current sensing 201 – Fig. 5) configured to convert the first sense voltage to a first digital voltage (page 10, lines 16-25);
a second analog-to-digital converter circuit (504 – Fig. 5) (second analog-to-digital converter circuit in current sensing 202 – Fig. 5) configured to convert the second sense voltage to a second digital voltage (page 10, lines 16-25); and
control circuitry (206 – Fig. 2) configured to (i) process the first digital voltage and the second digital voltage to determine a difference between the first current and the second current (page 10, lines 16-25), and (ii) generate a control signal to interrupt current flow (by opening 111A, 111B – Fig. 2) in the first and second electrical paths (103, 104 – Fig. 2), in response to determining that the difference between the first current and the second current meets or exceeds a difference threshold (claim 1, lines 13-19; page 9, lines 5-12; page 8, lines 3-7; page 8, lines 23-28).
With regard to claim 15, Telefus teaches all the limitations of claim 9, and further teaches the device comprises a ground fault circuit interrupter outlet device (Abstract, line1; page 21, lines 2-6).
With regard to claim 16, Telefus teaches all the limitations of claim 9, and further teaches the device comprises a ground fault circuit interrupter circuit breaker device (Abstract, line 1; page 1, lines 12-13).
With regard to claim 17, Telefus teaches all the limitations of claim 9, and further teaches the device comprises at least one of an electromechanical switch (111A, 111B – Fig. 2; 401, 402 – Fig. 4) and a solid-state switch (301, 302 – Fig. 4) that is responsive to the control signal to interrupt the current flow in the first and second electrical paths (103, 104 – Fig. 4) through the device.
With regard to claim 18, Telefus teaches a method, comprising:
sensing a first current (201 – Fig. 2) flowing in a first wire (103 – Fig. 2) and a second current (202 – Fig. 2) flowing in a second wire (104 – Fig. 2), the first and second wires (103, 104 – Fig. 2) being configured to supply alternative current (AC) power (101 – Fig. 2) to a load (102 – Fig. 2);
generating first digital data corresponding to the first current (page 10, lines 16-25, “digital signal”), and second digital data corresponding to the second current (page 10, lines 16-25, “digital signal”); and
processing (206 – Fig. 2) the first digital data (first digital data conducted via bidirectional digital line 210 – Fig. 2, Fig. 5) and the second digital data (second digital data conducted via bidirectional digital line 211 – Fig. 2, Fig. 5) to determine a difference between the first current and the second current (page 9, lines 5-12), and generate a control signal to interrupt current flow (by opening 111A, 111B – Fig. 2) in the first and second wires (103, 104 – Fig. 2), in response to determining that the difference between the first current and the second current meets or exceeds a difference threshold (claim 1, lines 13-19; page 9, lines 5-12; page 8, lines 3-7; page 8, lines 23-28).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Telefus (US WO 2021/112870 A1) (IDS Record) in view of Kojori (US 2008/0084201 A1).
With regard to claim 5, Telefus teaches all the limitations of claim 1, and further teaches the first current sense resistor (501 – Fig. 5) and the second current sense resistor (502 – Fig. 5); but do not teach each comprises a four-terminal Kelvin resistor.
Kojori teaches an integrated current sensor (Abstract, lines 1-2) comprises a four-terminal Kelvin resistor ([0071] lines 1-5; [0076] lines 1-10).
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the first current sense resistor and the second current sense resistor of Telefus, to have a four-terminal Kelvin resistor, as taught by Kojori, in order to improve the accuracy, precision of the current sense resistor and take advantage of their improved design for high current that separates the high-current path from the low-current sensing path, making it ideal for current sensing/shunt resistors.
With regard to claim 10, Telefus teaches all the limitations of claim 9, and further teaches the first current sense resistor (501 – Fig. 5) and the second current sense resistor (502 – Fig. 5); but do not teach each comprises a four-terminal Kelvin resistor.
Kojori teaches an integrated current sensor (Abstract, lines 1-2) comprises a four-terminal Kelvin resistor ([0071] lines 1-5; [0076] lines 1-10).
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the first current sense resistor and the second current sense resistor of Telefus, to have a four-terminal Kelvin resistor, as taught by Kojori, in order to improve the accuracy, precision of the current sense resistor and take advantage of their improved design for high current that separates the high-current path from the low-current sensing path, making it ideal for current sensing/shunt resistors.
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Telefus (US WO 2021/112870 A1) (IDS Record) in view of Miller (US 2017/0063070 A1).
With regard to claim 14, Telefus teaches all the limitations of claim 9, and further teaches the first analog-to-digital converter circuit (504 – Fig. 5) (first analog-to-digital converter circuit in current sensing 201 – Fig. 5) and the second analog-to-digital converter circuit (504 – Fig. 5) (second analog-to-digital converter circuit in current sensing 202 – Fig. 5), but do not teach each comprise a delta-sigma analog-to-digital converter.
Miller teaches analog-to-digital converter circuit (58 – Fig. 2) which is a delta-sigma analog-to-digital converter ([0029] lines 7-10; claim 5, lines 1-2).
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the first analog-to-digital converter circuit and the second analog-to-digital converter circuit of Telefus, to have a delta-sigma analog-to-digital converter, as taught by Miller, in order to the device by providing accurate readings for rapid fault detection, crucial for sensitive human safety applications where detecting current imbalances that could produce dangerous ground faults.
Allowable Subject Matter
Claim(s) 2-3, 11-13, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With regard to claim 2, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “the digital signal processing circuitry is configured to: process the first digital data to determine a first peak current in each cycle of the AC power; process the second digital data to determine a second peak current in each cycle of the AC power; determine a difference between the first current and the second current as a difference between the first peak current and the second peak current in each cycle of the AC power; and generate the control signal to interrupt the current flow in the first and second wires, at least in response to determining that the difference between the first peak current and the second peak current meets or exceeds the difference threshold over a specified number of consecutive cycles of the AC power.”
With regard to claim 3, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “wherein the digital signal processing circuitry is configured to: process the first digital data to determine a first root mean square (RMS) current in each cycle of the AC power; process the second digital data to determine a second RMS current in each cycle of the AC power; determine a difference between the first current and the second current as a difference between the first RMS current and the second RMS current in each cycle of the AC power; and generate the control signal to interrupt the current flow in the first and second wires, at least in response to determining that the difference between the first RMS current and the second RMS current meets or exceeds the difference threshold over a specified number of consecutive cycles of the AC power.”
With regard to claim 11, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “the control circuitry is configured to: process the first digital voltage to determine a first peak voltage in each cycle of the AC power, and determine a first peak current which corresponds to the first peak voltage based on a resistance of the first current sense resistor; process the second digital voltage to determine a second peak voltage in each cycle of the AC power, and determine a second peak current which corresponds to the second peak voltage based on a resistance of the second current sense resistor; determine a difference between the first current and the second current as a difference between the first peak current and the second peak current in each cycle of the AC power; and generate the control signal to interrupt the current flow in the first and second electrical paths through the device, at least in response to determining that the difference between the first peak current and the second peak current meets or exceeds the difference threshold over a specified number of consecutive cycles of the AC power.”
With regard to claim 12, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “the control circuitry is configured to: process the first digital voltage to determine a first root mean square (RMS) voltage in each cycle of the AC power, and determine a first RMS current which corresponds to the first RMS voltage based on a resistance of the first current sense resistor; process the second digital voltage to determine a second RMS voltage in each cycle of the AC power, and determine a second RMS current which corresponds to the second RMS voltage based on a resistance of the second current sense resistor; determine a difference between the first current and the second current as a difference between the first RMS current and the second RMS current in each cycle of the AC power; and generate the control signal to interrupt the current flow in the first and second electrical paths through the device, at least in response to determining that the difference between the first RMS current and the second RMS current meets or exceeds the difference threshold over a specified number of consecutive cycles of the AC power.”
With regard to claim 13, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “a first dual-ported memory device configured enable the first analog-to-digital converter circuit to store digital values of the first digital voltage in a current cycle of the AC power, while the control circuitry reads digital values of the first digital voltage stored in a previous cycle of the AC power; and a second dual-ported memory device configured enable the second analog-to-digital converter circuit to store digital values of the second digital voltage in the current cycle of the AC power, while the control circuitry reads digital values of the second digital voltage stored in the previous cycle of the AC power.”
With regard to claim 19, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “wherein processing the first digital data and the second digital data comprises: processing the first digital data to determine a first peak current in each cycle of the AC power; processing the second digital data to determine a second peak current in each cycle of the AC power; determining a difference between the first current and the second current as a difference between the first peak current and the second peak current in each cycle of the AC power; and generating the control signal to interrupt the current flow in the first and second wires, at least in response to determining that the difference between the first peak current and the second peak current meets or exceeds the difference threshold over a specified number of consecutive cycles of the AC power.”
With regard to claim 20, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “wherein processing the first digital data and the second digital data comprises: processing the first digital data to determine a first root mean square (RMS) current in each cycle of the AC power; processing the second digital data to determine a second RMS current in each cycle of the AC power; determining a difference between the first current and the second current as a difference between the first RMS current and the second RMS current in each cycle of the AC power; and generating the control signal to interrupt the current flow in the first and second wires, at least in response to determining that the difference between the first RMS current and the second RMS current meets or exceeds the difference threshold over a specified number of consecutive cycles of the AC power.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see attached PTO-892.
Wood (US 2014/0253102 A1) teaches a current measurement apparatus 100 comprises a measurement arrangement 110, 114 which is configured to be disposed in relation to a load 108 which draws a current signal, the measurement arrangement being operative when so disposed to measure the load drawn current signal. The current measurement apparatus 100 also comprises a signal source 112 which is operative to apply a reference input signal to the measurement arrangement 110, 114 whereby an output signal from the measurement arrangement comprises a load output signal corresponding to the load drawn current signal and a reference output signal corresponding to the reference input signal. The current measurement apparatus 100 further comprises processing apparatus 116 which is operative to receive the output signal and to make a determination in dependence on the reference output signal and the load output signal, the determination being in respect of at least one of the load drawn current signal and electrical power consumed by the load.
Wood (EP 3736578 B1) teaches an apparatus for detecting a change in a transfer function of a current measurement arrangement (118) comprising a current transducer (110) arranged to measure a first current passing through a first conductor (104), the apparatus comprising: a signal source (112) configured to apply a reference signal to the current transducer such a transducer output signal from the current transducer comprises: a current measurement signal indicative of the first current passing through the first conductor; and a reference signal component resulting from the reference signal; and signal processing circuitry (116) configured to: extract the reference signal component from the transducer output signal; and detect a change in the transfer function of the current measurement arrangement by comparing the extracted reference signal component to an earlier extracted reference signal component.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas Bellido whose telephone number is (571) 272-5034. The examiner can normally be reached Monday to Friday from 9:00 am to 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/N.B./Examiner, Art Unit 2838
/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838