Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114.
Response to Arguments
Examiner thank applicant’s representative for courtesy extended during interview after previous final rejection. Upon further search and consideration, while newly amended subject matter appear to overcome previously cited prior art, it is noted the specification of pending application lacks verbatim support outlining the added negative limitation of “wherein the first subpixel is not connected to the second reference line and the second subpixel is not connected to the first reference line”. In addition, in applicant’s remark on 9/15/26, no specific paragraph of specification is referenced to state on record as to which particular section or embodiment of specification provide support for the newly amended subject matter. For these reasons, 35 U.S.C. 112 rejection is raised for applicant to provide further evidence on written description of newly amended subject matter.
Furthermore, additional prior art is cited upon further search and consideration, applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant is encouraged to review specification and corresponding subject matter as claimed in previously object claims 18 and 20 from previous office action and consider amending claims to provide support and/or overcome cited prior arts.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-11, and 13-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Amended independent claims 1 and 13 additional recites, inter alia:
wherein the first subpixel is not connected to the second reference line and the second subpixel is not connected to the first reference line.
However, the aforementioned limitation is not found verbatim from text of originally filed specification, and applicant has not provided on record corresponding section or embodiment from original specification that clearly map to the newly added subject matter. Therefore, claims 1 and 13 are rejected for introduction of new matter as subject matter was not described in the specification in such a way as to reasonably convey that the inventor, at the time the application was filed, had possession of the claimed invention.
Claims 2-11, and 14-20 are rejected for dependency on rejected claims 1 and 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 3, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al., US 20230140902 A1 (hereinafter “Park”), in further view of Kim et al., US 20210272505 A1 (hereinafter “Kim”), and Moradi et al., US 20190114970 A1 (hereinafter “Moradi”).
Regarding claim 1, Park discloses a display device (see abstract, an organic light emitting display device, fig. 3), comprising:
a plurality of subpixels (fig. 3, paragraphs 60-67 pixels PX) electrically connected to a plurality of gate lines (fig. 3, paragraphs 60-67, gate lines SWL0~SWLn), a plurality of data lines (fig. 3, paragraphs 60-67, data lines DL1~DLm) and a plurality of reference voltage lines (fig. 3, 4, paragraphs 65, 71, 79, 89, 90, plurality of reference voltage lines supplying signal VINT1, VINT2);
wherein a first subpixel located in a first pixel row is electrically connected to a first data line and a first reference voltage line and a first gate line (see annotated fig. 3, 4 below, first pixel electrically connected with first data line DL1, first reference line IVL1 and first gate line SWL1),
wherein a second subpixel located in a second pixel row immediately below the first pixel row is electrically connected to the first data line and a second reference voltage line different from the first reference voltage line and a second gate line (see annotated fig. 3, 4 below, first pixel electrically connected with first data line DL1, second reference line IVL2 and first gate line SWL2), and
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wherein the first reference voltage line and the second reference voltage line are configured to receive voltages of magnitudes different from each other (paragraphs 96-115, IVL1 and IVL2 configured to apply reference voltage VINT1 and VINT2 of different magnitudes, paragraphs 99, “the first initialization voltage VINT1 may have a first voltage level V1 during the first frame OF, and the second initialization voltage VINT2 has a second voltage level V2 different from the first voltage level V1”, paragraph 113, “when the first frame OF ends and the second frame EF starts, the first initialization voltage VINT1 changes from the first voltage level V1 to the second voltage level V2, and the second initialization voltage VINT2 changes from the second voltage level V2 to the first voltage level V1”);
wherein the first subpixel comprises:
a light emitting element (fig. 4, light emitting element ED).
a driving transistor (fig. 4, driving transistors T1_O, T1_E) connected to the light emitting element (fig. 4, light emitting element ED);
a scan transistor (fig. 4, transistor SWj) connected between the first data line (fig. 4, data line DLi) and a first node (fig. 4, node N1) of the driving transistor,
a sensing transistor (fig. 4, transistor SILj) connected between the first reference voltage line (fig. 4, reference line IVL1) and a second node (fig. 4, node N2) of the driving transistor (fig. 4, transistor T1_O, T1_E).
Park does not disclose in particular: the first node being a gate node of the driving transistor.
In other word, Park does not disclose in particular the concept of the data line signal is being supplied to the gate node of the driving transistor instead of source node of the driving transistor, that the scan transistor supplies the data signal to the gate of driving transistor.
The concept of supplying image data signal to the gate of driving transistor via scan transistor, however, is well known in the display art, such as disclosed by
Kim, which discloses scan transistor T2 supplying data signal DLj to gate of driving transistor T1 of pixel circuit instead of source/drain (fig. 2, paragraphs 81, “Referring to FIGS. 2 and 3, the pixel PXij may include a light emitting element LD, a first transistor T1 (or driving transistor), a second transistor T2, a third transistor T3, and a storage capacitor Cst.”, “The first electrode of the first transistor T1 may be connected to the first driving power supply VDD, and the second electrode thereof may be connected to the first electrode of the light emitting element LD. A gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 controls an amount of current flowing to the light emitting element LD in response to the voltage of the first node N1.”, “The first electrode of the second transistor T2 may be connected to the data line DLj, and the second electrode may be connected to the first node N1. A gate electrode of the second transistor T2 may be connected to the scan line SLi. The second transistor T2 may be turned on when the scan signal is supplied to the scan line SLi to transfer the data voltage from the data line DLj to the first node N1, “the circuit structure of the pixel PXij according to some example embodiments of the present invention is not limited to FIG. 2. For example, the light emitting element LD may be disposed between the first driving power supply VDD and the first electrode of the first transistor T1. In addition, in FIG. 2, the transistors T1 to T3 are shown as an NMOS, but embodiments according to the present invention are not limited thereto. For example, at least one of the transistors T1 to T3 may be formed of a PMOS.”)
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of configuring the data line signal to be supplied to the gate node of the driving transistor instead of source node of the driving transistor by scan transistor, such as disclosed by Kim, into the device of Park, to constitute the first node being a gate node of the driving transistor, such is replacement of a known technique with another known technique to drive pixel circuit to display image according to data signal, the result would have been predictable and the intended function of controlling pixel to emit light and display image would have been the same.
Park in view of Kim does not disclose in particular wherein the first subpixel is not connected to the second reference line and the second subpixel is not connected to the first reference line.
In similar field of endeavor of display art, Moradi discloses a display device (see abstract, fig. 1, display 100) comprising a plurality of subpixels electrically connected to a plurality of gate lines (fig. 1, paragraph 45, 60 gate lines S[i] ~ S[n]), a plurality of data lines (fig. 1, paragraph 62, data lines Vdata[j] ~ Vdata[m]) and a plurality of reference voltage lines (fig. 1, paragraphs 55, 62, reference lines Vref[i] ~ Vref[n]); wherein a first subpixel located in a first pixel row is electrically connected to a first data line and a first reference voltage line and a first gate line (fig. 1, first subpixel 200 located at first row connected to S[i], Vdata[j] and Vref[i]), wherein a second subpixel located in a second pixel row immediately below the first pixel row is electrically connected to the first data line and a second reference voltage line different from the first reference voltage line and a second gate line (fig. 1, second subpixel 200 in a row below first subpixel 200 in second row, connected to S[i+1], Vdata[j] and Vref[i+1]), wherein the first subpixel is not connected to the second reference line and the second subpixel is not connected to the first reference line (see fig. 1, note each segment of reference line Vref corresponding to different rows is individually connected to single row and not connected to another row), and wherein the first reference voltage line and the second reference voltage line are configured to receive voltages of magnitudes different from each other (Moradi, paragraph 100, “with reference to FIG. 1, in embodiments wherein the reference voltage Vref provided to a pixel circuit 200 varies depending on a particular stage of operation, the reference voltage source 108 may provide different values of the reference voltage Vref to different pixel rows, so that for example the reference lines 126i and 126n may be at different values of the reference voltage Vref at a particular moment of time”).
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It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of configuring a reference voltage generator that individually supply dedicated reference line to each individual pixel row, such as disclosed by Moradi, into the display device of Park in view of Kim, to constitute wherein the first subpixel is not connected to the second reference line and the second subpixel is not connected to the first reference line, such is incorporation of a known concept into a know device to yield predictable result, the result would have been predictable and would allow references line of display device to be more versatile and configurable with different reference voltage that is dedicated to be supplied to each individual pixel rows of display device.
Regarding claim 2, Park in view of Kim and Moradi discloses the display device of claim 1, wherein in operation,
in a first sub frame period (Park, fig. 5A, frame period EF) of a main frame period in which the plurality of subpixels emit light, a first reference voltage is supplied to the first reference voltage line and a second reference voltage is supplied to the second reference voltage line (Park, paragraphs 96-115, voltage of VINT1 and VINT2 alternate during frame period EF and OF, paragraph 99, “the first initialization voltage VINT1 may have a first voltage level V1 during the first frame OF, and the second initialization voltage VINT2 has a second voltage level V2 different from the first voltage level V1”); and
in a second sub frame period (Park, fig. 5A, frame period OF) of the main frame period, the second reference voltage is supplied to the first reference voltage line and the first reference voltage is supplied to the second reference voltage line (Park, paragraphs 96-115, voltage of VINT1 and VINT2 alternate during frame period EF and OF, “when the first frame OF ends and the second frame EF starts, the first initialization voltage VINT1 changes from the first voltage level V1 to the second voltage level V2, and the second initialization voltage VINT2 changes from the second voltage level V2 to the first voltage level V1”).
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Regarding claim 3, Park in view of Kim and Moradi discloses the display device of claim 2, wherein the second reference voltage is higher than the first reference voltage (Park, paragraph 100, “For example, the first voltage level V1 may be about −4.5 V, and the second voltage level V2 may be about 4.6 V”).
Regarding claim 13, this is a method claim counterpart of device claim 2, with all claimed elements in claim 13 already addressed in rejection of claims 1 and 2 above (claim 2 depends on claim 1). Accordingly, claim 13 is rejected for the same reasons as claim 2.
Regarding claim 14, this is a method claim counterpart of device claim 3, with all claimed elements in claim 14 already addressed in rejection of claim 3 above. Accordingly, claim 14 is rejected for the same reasons as claim 3.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kim and Moradi, as in claim 3 above, and in further view of Lee, US 20120162177 A1 (hereinafter “Lee”).
Regarding claim 4, Park in view of Kim and Moradi discloses the display device of claim 3.
Park in view of Kim and Moradi does not specifically outline wherein a magnitude of the second reference voltage is greater than a magnitude of a first data voltage supplied to a first data lines in the main frame period, or the magnitude of the second reference voltage is same as the magnitude of the data voltage.
In similar field of endeavor of supplying initialization voltage to pixel circuit, Lee discloses initialization voltage may be configured to be higher than magnitude of data voltage supplied to data line of display device (paragraph 59, ““According to an exemplary embodiment, the transistors configuring the pixel are realized as NMOS transistors, and the first power source voltage ELVDD of 12V, the second power source voltage ELVSS of 0V, the initialization voltage VINT of 20V, and the data voltage of the range of 10V to 15V may be set. However, the type of the transistor and the voltage values may be varied, and it is not limited to the above-described exemplary embodiment. However, in some embodiments, the initialization voltage is higher than the data voltage range.”)
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of configuring reference voltage to be greater than a magnitude of data voltage supplied to data line of display device, such as disclosed by Lee, into the display device of Park in view of Kim and Moradi, to constitute wherein a magnitude of the second reference voltage is greater than a magnitude of a first data voltage supplied to a first data lines in the main frame period, or the magnitude of the second reference voltage is same as the magnitude of the data voltage, in order to achieve the predictable result of allowing pixel driving circuit to be initialized prior to supplying pixel circuit with data voltage, while preforming the intended function of controlling pixel to emit light and display image.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kim and Moradi, as in claim 3 above, and in further view of Yun et al., US 20240046848 A1 (hereinafter “Yun”).
Regarding claim 5, Park in view of Kim and Moradi discloses the display device of claim 3.
Park in view of Kim and Moradi does not disclose in particular wherein the second reference voltage is lower than a threshold voltage of a light emitting element supplied with the second reference voltage.
In similar field of endeavor of supplying reference voltage to pixel circuit (paragraph 47, the power management block 124 may provide the transistor off voltage VGH, the transistor on voltage VGL, and the initialization voltage VINT to the pixel PX), Yun discloses the concept that reference voltage may be set to lower than a threshold voltage of the light emitting element of pixel to suppress emission of light emitting element (paragraph 49, “the initialization voltage VINT may initialize an amount of charge accumulated in an organic light emitting diode. In an example, the initialization voltage VINT may be applied to a gate electrode of a transistor to initialize an amount of charge … A light emitting control signal of a turn off level may be applied through the gate driver 121, and the initialization voltage VINT may be applied through the gate driver 121. The initialization voltage VINT may be transmitted to an anode of a light emitting element (EL) to initialize an amount of charge accumulated in the light emitting element (EL). … the initialization voltage VINT may be set lower than a threshold voltage Vth of the light emitting element (EL) to suppress light emission of the light emitting element (EL)).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of configuring reference voltage to be lower than a threshold voltage of light emitting element supplied with the second reference voltage, such as disclosed by Yun, into the device of Park in view of Kim and Moradi, to constitute wherein the second reference voltage is lower than a threshold voltage of a light emitting element supplied with the second reference voltage, in order to achieve the predictable result of allowing control of emission state of pixel circuit, while preforming the intended function of controlling pixel to emit light and display image.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kim and Moradi, as in claim 3 above, and in further view of Kim et al., US 20230206819 A1 (hereinafter “Kim’819”).
Regarding claim 6, Park in view of Kim and Moradi discloses the display device of claim 3.
Park in view of Kim and Moradi does not disclose in particular wherein the second reference voltage is higher than a threshold voltage of a light emitting element supplied with the second reference voltage.
In similar field of endeavor of supplying reference voltage to pixel circuit (paragraphs 44, 46, The power supply 304 may generate power needed for driving of the pixel array of the display panel 100, the gate driver 120, and the drive IC 300 by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, and a boost converter. The power supply 304 may adjust an input voltage to generate direct current (DC) powers such as a gamma reference voltage, a gate on voltage VGL, a gate off voltage VGH, a pixel driving voltage ELVDD, a low level source voltage ELVSS, and an initialization voltage Vini … The initialization voltage Vini may be a voltage for initializing main nodes of the pixel circuit), Kim’819 discloses the concept that reference voltage may be set to lower than a threshold voltage of the light emitting element of pixel (paragraph 49, the initialization voltage Vini may be set to a DC voltage greater than a threshold voltage of light emitting device EL).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of configuring reference voltage to be higher than a threshold voltage of light emitting element supplied with the second reference voltage, such as disclosed by Kim’819, into the device of Park in view of Kim and Moradi, to constitute wherein the second reference voltage is higher than a threshold voltage of a light emitting element supplied with the second reference voltage, in order to achieve the predictable result of allowing control of emission state of pixel circuit, while preforming the intended function of controlling pixel to emit light and display image.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kim and Moradi, as in claim 1 above, and in further view of Kim et al. US 20150009194 A1 (hereinafter “Kim’194”)
Regarding claim 7, Park in view of Kim and Moradi discloses the display device of claim 1.
Park in view of Kim and Moradi does not disclose in particular wherein: the plurality of subpixels are electrically connected to a plurality of base voltage lines, the first subpixel is electrically connected to a first base voltage line, the second subpixel is electrically connected to a second base voltage line different from the first base voltage line, and the first base voltage line and the second base voltage line are configured to receive voltages of magnitudes different from each other.
In similar field of endeavor, Kim’819 discloses a display device (see abstract, an organic light emitting display device), comprising: a plurality of subpixels (fig. 1, 4, paragraphs 37, sub-pixels / pixels 140, “the organic light emitting display device according to this embodiment includes a display unit 130 configured to include pixels 140 positioned in an area defined by scan lines S1 to Sn and data lines D1 to Dm”) electrically connected to a plurality of gate lines (fig. 1, 4, scan lines S1 to Sn, paragraph 38), a plurality of data lines (fig. 1, 2, data lines D1 to Dm, paragraph 39) and a plurality of reference voltage lines (fig. 1, 2A, Vint1-Vint3, paragraph 45, “Here, the first initialization voltage Vint1 may be supplied to the red and green sub-pixels. The second initialization voltage Vint2 may be supplied to the first blue sub-pixel, and the third initialization voltage Vint3 may be supplied to the second blue sub-pixel. Additionally, the initialization power unit 160 may control the second and third initialization voltages Vint2 and Vint3 so that the first blue sub-pixel and/or the second blue sub-pixel becomes an emission state and/or a non-emission state, under the control of the timing controller 150”); wherein: the plurality of subpixels are electrically connected to a plurality of base voltage lines (fig. 1, 2A, Vint1-Vint3, paragraph 45, “Here, the first initialization voltage Vint1 may be supplied to the red and green sub-pixels. The second initialization voltage Vint2 may be supplied to the first blue sub-pixel, and the third initialization voltage Vint3 may be supplied to the second blue sub-pixel. Additionally, the initialization power unit 160 may control the second and third initialization voltages Vint2 and Vint3 so that the first blue sub-pixel and/or the second blue sub-pixel becomes an emission state and/or a non-emission state, under the control of the timing controller 150”, examiner under plain meaning base voltage lines may be simply interpreted as any voltage line which provide a reference voltage as basis for operation, and that absent further limitation, the base voltage lines can be sections of reference voltages lines Vint1-Vint3 supplied to pixels),
the first subpixel is electrically connected to a first base voltage line (fig. 4, example blue pixel with first blue sub-pixel 142 connected to voltage line Vint2, wherein sections of voltage line Vint2 may be interpreted as first base voltage line),
the second subpixel is electrically connected to a second base voltage line different from the first base voltage line (fig. 4, example blue pixel with second sub-pixel 144, connected to voltage line Vint3, wherein sections of voltage line Vint3 may be interpreted as second base voltage line), and
the first base voltage line and the second base voltage line are configured to receive voltages of magnitudes different from each other (paragraph 45, “the initialization power unit 160 may control the second and third initialization voltages Vint2 and Vint3 so that the first blue sub-pixel and/or the second blue sub-pixel becomes an emission state and/or a non-emission state, under the control of the timing controller 150”, see fig. 7, paragraphs 79-80, voltage of different magnitude low/high are supplied to Vint2 and Vint3).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of controlling magnitude of voltage supplied to base voltage lines of pixels, such as disclosed by Kim’819, into the display device Park in view of Kim and Moradi, to constitute wherein: the plurality of subpixels are electrically connected to a plurality of base voltage lines, the first subpixel is electrically connected to a first base voltage line, the second subpixel is electrically connected to a second base voltage line different from the first base voltage line, and the first base voltage line and the second base voltage line are configured to receive voltages of magnitudes different from each other, such is incorporation of a known technique into a known device to yield predictable result, the result would have been predictable and would allow display device to control emission state of pixel light emitting element in different frame period by adjusting base voltage wherein light emitting element is connected to.
Claims 8, 9, 10 11, 15, 16, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Kim and Moradi, as in claim 1 above, and in further view of Senda US 20140306946 A1 (hereinafter “Senda”).
Regarding claim 8, Park in view of Kim and Moradi discloses the display device of claim 1, wherein: the first subpixel is electrically connected to the first gate line, the second subpixel is electrically connected to the second gate line (Park, fig. 3, see annotated figure below)
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Park in view of Kim and Moradi does not disclose in particular: in operation, gate signals are supplied to the first gate line and the second gate line at a same time point.
In similar field of endeavor, Senda disclose display device wherein a first subpixel is electrically connected to a first gate line, the second subpixel is electrically connected to a second gate line (fig. 1, first and second pixel 140 connected to first and second gate line S1 and S2 respectively), and in operation, gate signals are supplied to the first gate line and the second gate line at a same time point (fig. 6, paragraph 69, initialization and stabilization stage wherein all scan line are activate simultaneously for a period at beginning of frame period).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of activating gate line simultaneously during a frame period to initialize pixel circuit, such as disclosed by Senda, into the display device of Park in view of Kim and Moradi, to constitute in operation, gate signals are supplied to the first gate line and the second gate line at a same time point, such is incorporation of a known technique into a known device to yield predictable result, the result would have been predictable and would allow pixel circuit to be initialized at beginning of a frame period.
Regarding claim 9, Park in view of Kim, Moradi, and Senda discloses the display device of claim 8, further comprising: a third subpixel electrically connected to the first gate line and a second data line; and a fourth subpixel electrically connected to the second gate line and the second data line (Park, fig. 3, see annotated figure below).
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Regarding claim 10, Park in view of Kim, Moradi, and Senda discloses the display device of claim 9, wherein: the third subpixel is electrically connected to the first reference voltage line, and the fourth subpixel is electrically connected to the second reference voltage line (see Park, fig. 4, each pixel of display device is connected to the first reference line IVL1 and second reference line IVL2, including the third and fourth subpixels).
Regarding claim 11, Park in view of Kim, Moradi, and Senda discloses the display device of claim 9, wherein the third subpixel is electrically connected to the second reference voltage line, and the fourth subpixel is electrically connected to the first reference voltage line (see Park, fig. 4, each pixel of display device is connected to the first reference line IVL1 and second reference line IVL2, including the third and fourth subpixels).
Regarding claim 15, this is a method claim counterpart of device claim 8, with all claimed elements in claim 15 already addressed in rejection of claim 8 above. Accordingly, claim 15 is rejected for the same reasons as claim 8.
Regarding claim 16, this is a method claim counterpart of device claim 9, with all claimed elements in claim 16 already addressed in rejection of claims 9 and 1 above (claim 9 depends on claims 1 and 8). Accordingly, claim 16 is rejected for the same reasons as claim 9.
Regarding claim 17, this is a method claim counterpart of device claim 10, with all claimed elements in claim 17 already addressed in rejection of claim 10 above. Accordingly, claim 17 is rejected for the same reasons as claim 10.
Regarding claim 19, this is a method claim counterpart of device claim 11, with all claimed elements in claim 19 already addressed in rejection of claim 11 above. Accordingly, claim 19 is rejected for the same reasons as claim 11.
ConclusionAny inquiry concerning this communication or earlier communications from the examiner should be directed to PEIJIE SHEN whose telephone number is (571)272-5522. The examiner can normally be reached Monday - Friday 10AM - 6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 5712727603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PEIJIE SHEN/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622
