Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 3, 12, 13 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al., US 20230140902 A1 (hereinafter “Park”).
Regarding claim 1, Park discloses a display device (see abstract, an organic light emitting display device, fig. 3), comprising:
a plurality of subpixels (fig. 3, paragraphs 60-67 pixels PX) electrically connected to a plurality of gate lines (fig. 3, paragraphs 60-67, gate lines SWL0~SWLn), a plurality of data lines (fig. 3, paragraphs 60-67, data lines DL1~DLm) and a plurality of reference voltage lines (fig. 3, 4, paragraphs 65, 71, 79, 89, 90, plurality of reference voltage lines supplying signal VINT1, VINT2);
wherein a first subpixel located in a first pixel row is electrically connected to a first data line and a first reference voltage line and a first gate line (see annotated fig. 3, 4 below, first pixel electrically connected with first data line DL1, first reference line IVL1 and first gate line SWL1),
wherein a second subpixel located in a second pixel row immediately below the first pixel row is electrically connected to the first data line and a second reference voltage line different from the first reference voltage line and a second gate line (see annotated fig. 3, 4 below, first pixel electrically connected with first data line DL1, second reference line IVL2 and first gate line SWL2), and
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wherein the first reference voltage line and the second reference voltage line are configured to receive voltages of magnitudes different from each other (paragraphs 96-115, IVL1 and IVL2 configured to apply reference voltage VINT1 and VINT2 of different magnitudes, paragraphs 99, “the first initialization voltage VINT1 may have a first voltage level V1 during the first frame OF, and the second initialization voltage VINT2 has a second voltage level V2 different from the first voltage level V1”, paragraph 113, “when the first frame OF ends and the second frame EF starts, the first initialization voltage VINT1 changes from the first voltage level V1 to the second voltage level V2, and the second initialization voltage VINT2 changes from the second voltage level V2 to the first voltage level V1”).
Regarding claim 2, Kim discloses the display device of claim 1, wherein in operation,
in a first sub frame period (fig. 5A, frame period EF) of a main frame period in which the plurality of subpixels emit light, a first reference voltage is supplied to the first reference voltage line and a second reference voltage is supplied to the second reference voltage line (paragraphs 96-115, voltage of VINT1 and VINT2 alternate during frame period EF and OF, paragraph 99, “the first initialization voltage VINT1 may have a first voltage level V1 during the first frame OF, and the second initialization voltage VINT2 has a second voltage level V2 different from the first voltage level V1”); and
in a second sub frame period (fig. 5A, frame period OF) of the main frame period, the second reference voltage is supplied to the first reference voltage line and the first reference voltage is supplied to the second reference voltage line (paragraphs 96-115, voltage of VINT1 and VINT2 alternate during frame period EF and OF, “when the first frame OF ends and the second frame EF starts, the first initialization voltage VINT1 changes from the first voltage level V1 to the second voltage level V2, and the second initialization voltage VINT2 changes from the second voltage level V2 to the first voltage level V1”).
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Regarding claim 3, Park discloses the display device of claim 2, wherein the second reference voltage is higher than the first reference voltage (paragraph 100, “For example, the first voltage level V1 may be about −4.5 V, and the second voltage level V2 may be about 4.6 V”).
Regarding claim 12, Park discloses the display device of claim 1, wherein the first subpixel comprises:
a driving transistor (fig. 4, driving transistors T1_O, T1_E) for driving a light emitting element (fig. 4, light emitting element ED);
a scan transistor (fig. 4, transistor SWj) electrically connected between a first node (fig. 4, node N1) of the driving transistor and the first data line (fig. 4, data line DLi), and
a sensing transistor (fig. 4, transistor SILj) electrically connected to a second node (fig. 4, node N2) of the driving transistor (fig. 4, transistor T1_O, T1_E) and the first reference voltage line (fig. 4, reference line IVL1).
Regarding claim 13, this is a method claim counterpart of device claim 2, with all claimed elements in claim 13 already addressed in rejection of claims 1 and 2 above (claim 2 depends on claim 1). Accordingly, claim 13 is rejected for the same reasons as claim 2.
Regarding claim 14, this is a method claim counterpart of device claim 3, with all claimed elements in claim 14 already addressed in rejection of claim 3 above. Accordingly, claim 14 is rejected for the same reasons as claim 3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Park, as in claim 3 above, and in further view of Lee, US 20120162177 A1 (hereinafter “Lee”).
Regarding claim 4, Park discloses the display device of claim 3.
Park does not specifically outline wherein a magnitude of the second reference voltage is greater than a magnitude of a first data voltage supplied to a first data lines in the main frame period, or the magnitude of the second reference voltage is same as the magnitude of the data voltage.
In similar field of endeavor of supplying initialization voltage to pixel circuit, Lee discloses initialization voltage may be configured to be higher than magnitude of data voltage supplied to data line of display device (paragraph 59, ““According to an exemplary embodiment, the transistors configuring the pixel are realized as NMOS transistors, and the first power source voltage ELVDD of 12V, the second power source voltage ELVSS of 0V, the initialization voltage VINT of 20V, and the data voltage of the range of 10V to 15V may be set. However, the type of the transistor and the voltage values may be varied, and it is not limited to the above-described exemplary embodiment. However, in some embodiments, the initialization voltage is higher than the data voltage range.”)
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of configuring reference voltage to be greater than a magnitude of data voltage supplied to data line of display device, such as disclosed by Lee, into the display device of Park, to constitute wherein a magnitude of the second reference voltage is greater than a magnitude of a first data voltage supplied to a first data lines in the main frame period, or the magnitude of the second reference voltage is same as the magnitude of the data voltage, in order to achieve the predictable result of allowing pixel driving circuit to be initialized prior to supplying pixel circuit with data voltage, while preforming the intended function of controlling pixel to emit light and display image.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Park, as in claim 3 above, and in further view of Yun et al., US 20240046848 A1 (hereinafter “Yun”).
Regarding claim 5, Park discloses the display device of claim 3.
Kim does not disclose in particular wherein the second reference voltage is lower than a threshold voltage of a light emitting element supplied with the second reference voltage.
In similar field of endeavor of supplying reference voltage to pixel circuit (paragraph 47, the power management block 124 may provide the transistor off voltage VGH, the transistor on voltage VGL, and the initialization voltage VINT to the pixel PX), Yun discloses the concept that reference voltage may be set to lower than a threshold voltage of the light emitting element of pixel to suppress emission of light emitting element (paragraph 49, “the initialization voltage VINT may initialize an amount of charge accumulated in an organic light emitting diode. In an example, the initialization voltage VINT may be applied to a gate electrode of a transistor to initialize an amount of charge … A light emitting control signal of a turn off level may be applied through the gate driver 121, and the initialization voltage VINT may be applied through the gate driver 121. The initialization voltage VINT may be transmitted to an anode of a light emitting element (EL) to initialize an amount of charge accumulated in the light emitting element (EL). … the initialization voltage VINT may be set lower than a threshold voltage Vth of the light emitting element (EL) to suppress light emission of the light emitting element (EL)).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of configuring reference voltage to be lower than a threshold voltage of light emitting element supplied with the second reference voltage, such as disclosed by Yun, into the device of Park, to constitute wherein the second reference voltage is lower than a threshold voltage of a light emitting element supplied with the second reference voltage, in order to achieve the predictable result of allowing control of emission state of pixel circuit, while preforming the intended function of controlling pixel to emit light and display image.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Park, as in claim 3 above, and in further view of Kim et al., US 20230206819 A1 (hereinafter “Kim”).
Regarding claim 6, Park discloses the display device of claim 3.
Park does not disclose in particular wherein the second reference voltage is higher than a threshold voltage of a light emitting element supplied with the second reference voltage.
In similar field of endeavor of supplying reference voltage to pixel circuit (paragraphs 44, 46, The power supply 304 may generate power needed for driving of the pixel array of the display panel 100, the gate driver 120, and the drive IC 300 by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, and a boost converter. The power supply 304 may adjust an input voltage to generate direct current (DC) powers such as a gamma reference voltage, a gate on voltage VGL, a gate off voltage VGH, a pixel driving voltage ELVDD, a low level source voltage ELVSS, and an initialization voltage Vini … The initialization voltage Vini may be a voltage for initializing main nodes of the pixel circuit), Kim discloses the concept that reference voltage may be set to lower than a threshold voltage of the light emitting element of pixel (paragraph 49, the initialization voltage Vini may be set to a DC voltage greater than a threshold voltage of light emitting device EL).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of configuring reference voltage to be higher than a threshold voltage of light emitting element supplied with the second reference voltage, such as disclosed by Kim, into the device of Park, to constitute wherein the second reference voltage is higher than a threshold voltage of a light emitting element supplied with the second reference voltage, in order to achieve the predictable result of allowing control of emission state of pixel circuit, while preforming the intended function of controlling pixel to emit light and display image.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Park, as in claim 1 above, and in further view of Kim et al. US 20150009194 A1 (hereinafter “Kim”)
Regarding claim 7, Park discloses the display device of claim 1.
Park does not disclose in particular wherein: the plurality of subpixels are electrically connected to a plurality of base voltage lines, the first subpixel is electrically connected to a first base voltage line, the second subpixel is electrically connected to a second base voltage line different from the first base voltage line, and the first base voltage line and the second base voltage line are configured to receive voltages of magnitudes different from each other.
In similar field of endeavor, Kim discloses a display device (see abstract, an organic light emitting display device), comprising: a plurality of subpixels (fig. 1, 4, paragraphs 37, sub-pixels / pixels 140, “the organic light emitting display device according to this embodiment includes a display unit 130 configured to include pixels 140 positioned in an area defined by scan lines S1 to Sn and data lines D1 to Dm”) electrically connected to a plurality of gate lines (fig. 1, 4, scan lines S1 to Sn, paragraph 38), a plurality of data lines (fig. 1, 2, data lines D1 to Dm, paragraph 39) and a plurality of reference voltage lines (fig. 1, 2A, Vint1-Vint3, paragraph 45, “Here, the first initialization voltage Vint1 may be supplied to the red and green sub-pixels. The second initialization voltage Vint2 may be supplied to the first blue sub-pixel, and the third initialization voltage Vint3 may be supplied to the second blue sub-pixel. Additionally, the initialization power unit 160 may control the second and third initialization voltages Vint2 and Vint3 so that the first blue sub-pixel and/or the second blue sub-pixel becomes an emission state and/or a non-emission state, under the control of the timing controller 150”); wherein: the plurality of subpixels are electrically connected to a plurality of base voltage lines (fig. 1, 2A, Vint1-Vint3, paragraph 45, “Here, the first initialization voltage Vint1 may be supplied to the red and green sub-pixels. The second initialization voltage Vint2 may be supplied to the first blue sub-pixel, and the third initialization voltage Vint3 may be supplied to the second blue sub-pixel. Additionally, the initialization power unit 160 may control the second and third initialization voltages Vint2 and Vint3 so that the first blue sub-pixel and/or the second blue sub-pixel becomes an emission state and/or a non-emission state, under the control of the timing controller 150”, examiner under plain meaning base voltage lines may be simply interpreted as any voltage line which provide a reference voltage as basis for operation, and that absent further limitation, the base voltage lines can be sections of reference voltages lines Vint1-Vint3 supplied to pixels),
the first subpixel is electrically connected to a first base voltage line (fig. 4, example blue pixel with first blue sub-pixel 142 connected to voltage line Vint2, wherein sections of voltage line Vint2 may be interpreted as first base voltage line),
the second subpixel is electrically connected to a second base voltage line different from the first base voltage line (fig. 4, example blue pixel with second sub-pixel 144, connected to voltage line Vint3, wherein sections of voltage line Vint3 may be interpreted as second base voltage line), and
the first base voltage line and the second base voltage line are configured to receive voltages of magnitudes different from each other (paragraph 45, “the initialization power unit 160 may control the second and third initialization voltages Vint2 and Vint3 so that the first blue sub-pixel and/or the second blue sub-pixel becomes an emission state and/or a non-emission state, under the control of the timing controller 150”, see fig. 7, paragraphs 79-80, voltage of different magnitude low/high are supplied to Vint2 and Vint3).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of controlling magnitude of voltage supplied to base voltage lines of pixels, such as disclosed by Kim, into the display device Park, to constitute wherein: the plurality of subpixels are electrically connected to a plurality of base voltage lines, the first subpixel is electrically connected to a first base voltage line, the second subpixel is electrically connected to a second base voltage line different from the first base voltage line, and the first base voltage line and the second base voltage line are configured to receive voltages of magnitudes different from each other, such is incorporation of a known technique into a known device to yield predictable result, the result would have been predictable and would allow display device to control emission state of pixel light emitting element in different frame period by adjusting base voltage wherein light emitting element is connected to.
Claims 8, 9, 10 11, 15, 16, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Park, as in claim 1 above, and in further view of Senda US 20140306946 A1 (hereinafter “Senda”).
Regarding claim 8, Park discloses the display device of claim 1, wherein: the first subpixel is electrically connected to the first gate line, the second subpixel is electrically connected to the second gate line (Park, fig. 3, see annotated figure below)
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Park does not disclose in particular: in operation, gate signals are supplied to the first gate line and the second gate line at a same time point.
In similar field of endeavor, Senda disclose display device wherein a first subpixel is electrically connected to a first gate line, the second subpixel is electrically connected to a second gate line (fig. 1, first and second pixel 140 connected to first and second gate line S1 and S2 respectively), and in operation, gate signals are supplied to the first gate line and the second gate line at a same time point (fig. 6, paragraph 69, initialization and stabilization stage wherein all scan line are activate simultaneously for a period at beginning of frame period).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of activating gate line simultaneously during a frame period to initialize pixel circuit, such as disclosed by Senda, into the display device of Park, to constitute in operation, gate signals are supplied to the first gate line and the second gate line at a same time point, such is incorporation of a known technique into a known device to yield predictable result, the result would have been predictable and would allow pixel circuit to be initialized at beginning of a frame period.
Regarding claim 9, Park in view of Senda discloses the display device of claim 8, further comprising: a third subpixel electrically connected to the first gate line and a second data line; and a fourth subpixel electrically connected to the second gate line and the second data line (Park, fig. 3, see annotated figure below).
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Regarding claim 10, Park in view of Senda discloses the display device of claim 9, wherein: the third subpixel is electrically connected to the first reference voltage line, and the fourth subpixel is electrically connected to the second reference voltage line (see Park, fig. 4, each pixel of display device is connected to the first reference line IVL1 and second reference line IVL2, including the third and fourth subpixels).
Regarding claim 11, Park in view of Senda discloses the display device of claim 9, wherein the third subpixel is electrically connected to the second reference voltage line, and the fourth subpixel is electrically connected to the first reference voltage line (see Park, fig. 4, each pixel of display device is connected to the first reference line IVL1 and second reference line IVL2, including the third and fourth subpixels).
Regarding claim 15, this is a method claim counterpart of device claim 8, with all claimed elements in claim 15 already addressed in rejection of claim 8 above. Accordingly, claim 15 is rejected for the same reasons as claim 8.
Regarding claim 16, this is a method claim counterpart of device claim 9, with all claimed elements in claim 16 already addressed in rejection of claims 9 and 1 above (claim 9 depends on claims 1 and 8). Accordingly, claim 16 is rejected for the same reasons as claim 9.
Regarding claim 17, this is a method claim counterpart of device claim 10, with all claimed elements in claim 17 already addressed in rejection of claim 10 above. Accordingly, claim 17 is rejected for the same reasons as claim 10.
Regarding claim 19, this is a method claim counterpart of device claim 11, with all claimed elements in claim 18 already addressed in rejection of claim 11 above. Accordingly, claim 19 is rejected for the same reasons as claim 11.
Conclusion
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/PEIJIE SHEN/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622