DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/24/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US 2023/0069326) in view of Nathan et al. (US 2007/0195020), further in view of LV et al. (US 2021/0091281).
As to Claim 1, Baek et al. discloses A display panel, comprising: a substrate (fig.1, substrate SUB; para.0052); a plurality of light-emitting diodes disposed on the substrate, wherein each of the plurality of light-emitting diodes comprises a first electrode and a second electrode (fig.1-3; para.0061; light emitting element LD, including first electrode ET1 and second electrode ET2);
a first electrode wiring (fig.1-3, power source wiring Vss) disposed on the substrate and electrically connected to second electrodes of the plurality of light-emitting diodes (fig.1,3; first electrode wiring power source VSS connected to electrodes ET2 of the light emitting element LD; para.0090,0097);
a plurality of pixel driving circuits disposed on the substrate, wherein each of the plurality of pixel driving circuits comprises a driving sub-circuit (fig.3, fig.3, transistors M1, M2, capacitor Cst, collectively read as driving sub-circuit) and a detection sub-circuit (fig.3, transistor M3 (read as detection sub-circuit) is turned on during the light emitting inspection period to detect pixel defects caused by the light emitting elements LD; para.0121-0123);
the driving sub- circuit is at least coupled to the first electrode of a corresponding one of the plurality of light- emitting diodes (fig.3, driving transistor M1, capacitor Cst are connected to electrode ET1 of the light emitting element LD; para.0104-0105);
wherein the driving sub-circuit comprises a driving transistor, a switching transistor, a storage capacitor (fig.3, driving transistor M1, switching transistor M2 and capacitor Cst; para.0105, 0109, 0111), and a monitoring transistor, wherein an output terminal of the monitoring transistor is electrically connected to the first electrode of the corresponding one of the plurality of light-emitting diodes, the output terminal of the driving transistor and a capacitor electrode plate of the storage capacitor;
the detection sub-circuit comprises a detection input terminal (fig.3, terminal transistor M3 connected to power line INL) and a detection output terminal (fig.3-terminal of transistor M3 connected to ET1- node N2); and the detection sub-circuit is coupled to the first electrode of the corresponding one of the plurality of light-emitting diodes through the detection output terminal (fig.3-terminal of transistor M3 connected to ET1- node N2; para.0118, 0121);
wherein the detection sub-circuit comprises a detection transistor, wherein a source electrode and a drain electrode of the detection transistor are the detection input terminal and the detection output terminal, respectively (fig.3, source and drain of transistor M3, respectively); and
a detection pad portion (fig.1-3, pad area PA1 and PA2), wherein the detection pad portion comprises a first detection pad and a second detection pad (fig.1-3, pads P1 and P2 respectively), the first detection pad is electrically connected to detection input terminals of detection sub-circuits of the plurality of pixel driving circuits (fig.1-3, pad P1 connected to power source VDD, data DS which are connected to driving transistor M1 and switching transistor M2; para.0082,0087,0095), and the second detection pad is electrically connected to the first electrode wiring (fig.1-3; pads P2 are connected to first electrode wiring VSS; para.0090,0097);
wherein the display panel further comprises a display area and a non-display area surrounding the display area (fig.1-2, display area DA and non-display area NA; para.0052),
wherein the detection pad portion is disposed in the display area, and wherein the detection pad portion is disposed at a non-edge portion of the substrate;
wherein during a detecting period of the display panel, the driving sub-circuit is configured not to work or drive the corresponding one of the plurality of light-emitting diodes (para.0122, during light emitting inspection period a gate-off Voff may be applied to driving transistor M1); and
the first detection pad is configured to be applied a first electrical signal (para.0121, during light emitting element inspection period, power source VDD applied to pad P1), the second detection pad is configured to be applied a second electrical signal (para.0121, during light emitting element inspection period, power VSS is applied to pad P2),
wherein the first electrical signal is output to the detection input terminals of the detection sub-circuits and is further output to first electrodes of the plurality of light-emitting diodes through detection output terminals of the detection sub- circuits (fig.3, para.0118, 0121, during light emitting element inspection period, transistor M3 is turned on, and VDD is applied to input terminal of transistor M3 and transmitted to first electrode ET1 of the light emitting element), and the second electrical signal is output to the second electrodes of the plurality of light- emitting diodes through the first electrode wiring (para.0121-0122, during light emitting element inspection period VSS is applied to electrode ET2 of light emitting element LD), to detect whether all of the plurality of light- emitting diodes are normally lighted (para.0121-0123; defects caused by the light emitting elements provided to the pixels are individually detected); [or
when the display panel works normally, the driving sub-circuit is configured to drive the corresponding one of the plurality of light-emitting diodes to emit lights, and the detection sub- circuit is configured not to work or drive the corresponding one of the plurality of light-emitting diodes.]
Baek et al does not expressly disclose wherein the driving sub-circuit comprises a monitoring transistor, wherein an output terminal of the monitoring transistor is electrically connected to the first electrode of the corresponding one of the plurality of light-emitting diodes, the output terminal of the driving transistor and a capacitor electrode plate of the storage capacitor; and wherein the detection pad portion is disposed in the display area, and wherein the detection pad portion is disposed at a non-edge portion of the substrate;
Nathan et al. et al. discloses a pixel circuit comprising a monitoring transistor (fig.7,22, sensing transistor 220 used to monitor the voltage of the output line Vout and extract the aging factor of the OLED; para.0078,0080. 0117-0122), wherein an output terminal of the monitoring transistor is electrically connected to the first electrode of the corresponding one of the plurality of light-emitting diodes , the output terminal of the driving transistor and a capacitor electrode plate of the storage capacitor (fig.7,22, output terminal of transistor 220 connected to terminal of capacitor 214, the source of driving transistor 218, and first electrode of OLED).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Beak et al. with the teachings of Nathan et al., the motivation being monitor the voltage of an output line (or data line), and extract the aging the of pixel and use it for more accurate calibration of the luminance data.
Baek et al in view of Nathan et al do not expressly disclose wherein the detection pad portion is disposed in the display area, and wherein the detection pad portion is disposed at a non-edge portion of the substrate.
LV et al. discloses wherein the detection pad portion (fig.8,12; pad 52) is disposed in the display area (fig.8,12; pads 52 disposed in the detection substrate 200, same area as the mico LEDs to be detected; para.0064), and wherein the detection pad portion is disposed at a non-edge portion of the substrate (fig.8,12; pads are disposed on detection substrate 200 non-edge of the carrier substrate 100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Baek et al. in view of Nathan et al., with the teachings of LV et al., such that the substrate (of Baek) may be placed on a carrier substrate (as disclosed by LV). The motivation being to provide mass detection of lighting up of light emitting elements, and the detection efficiency and transfer efficiency of the light emitting elements are improved.
As to Claim 3, Baek et al. in view of Nathan et al., as modified by LV et al., disclose wherein the detection sub-circuit further comprises a detection driving terminal (Baek-fig.3, gate of transistor M3); and the detection pad portion further comprises a third detection pad, and the third detection pad is electrically connected to detection driving terminals of detection sub-circuits of the plurality of pixel driving circuits (Baek-fig.3, para.0089, signal pads SP transmit gate signals).
As to Claim 5, Baek et al. in view of Nathan et al., as modified by LV et al., disclose wherein a gate electrode of the detection transistor is the detection driving terminal (Baek-fig.3, gate of transistor M3).
As to Claim 20, Baek et al. in view of Nathan et al., as modified by LV et al., disclose wherein the third paction pad is disposed in the display area (Baek-fig.1-3, signal pads SP is substrate; LV-fig.8,12; pads disposed in the detection substrate 200).
Claim(s) 2,4,6,8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US 2023/0069326) in view of Nathan et al. (US 2007/0195020), further in view of LV et al. (US 2021/0091281), and further in view of of Zhu et al. (US 2017/0263187).
As to Claim 2, Baek et al. in in view of Nathan et al., as modified by LV et al., disclose wherein the detection sub-circuit further comprises a detection driving terminal (Baek-fig.3, gate of transistor M3). Baek et al. in view of Nathan et al., as modified by LV et al., do not expressly disclose the detection driving terminal of the detection sub-circuit is electrically connected to the detection input terminal.
Zhu et al. discloses a transistor having a driving terminal electrically connected to the input terminal (fig.2, gate electrode and first electrode of transistor T1 connected scan signal S1; para.0036,0039).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Baek et al. in view of Nathan et al., as modified by LV et al., with the teachings of Zhu et al., such that the driving terminal of detection transistor (M3) is electrically connected to the input terminal (as disclosed by Zhu et al). The motivation being so that input voltage signal may not only act to turn the transistor, but further act as an initiation voltage to initiate the driving transistor and the light emitting element. Thus, the layout area of the pixel driving circuit may be reduced.
As to Claim 4, Baek et al. in view of Nathan et al., as modified by LV et al. and Zhu et al., disclose wherein a gate electrode of the detection transistor is the detection driving terminal (Baek-fig.3, gate of transistor M3).
As to Claim 6, Baek et al. in view of Nathan et al., as modified by LV et al. and Zhu et al., disclose comprising a plurality of first detection wirings (Baek-fig.13; Vdd and Vint), and the plurality of first detection wirings are configured to electrically connect first electrodes of the plurality of light-emitting diodes to the first detection pad (Baek-fig.1-3; Vdd and Vint lines connect pad P1 to electrode ET1).
As to Claim 8 Baek et al. in view of Nathan et al., as modified by LV et al. and Zhu et al., disclose wherein an output terminal of the switching transistor is electrically connected to a driving terminal of the driving transistor and a first capacitor electrode plate of the storage capacitor (Baek-fig.3, terminal of transistor M2 connected to gate of driving transistor M1 and capacitor Cst), and an output terminal of the driving transistor is electrically connected to the first electrode of the corresponding one of the plurality of light-emitting diodes and the capacitor electrode plate of the storage capacitor (Baek-fig.3, terminal of driving transistor M1 connected to electrode ET1 of light emitting element LD and capacitor Cst).
Claim(s) 10-11, 13, 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US 2023/0069326) in view of Nathan et al. (US 2007/0195020), further in view of LV et al. (US 2021/0091281), and further in view of Jiang et al. (US 2021/0183282).
As to Claim 10, Baek et al. in view of Nathan et al., as modified by LV et al. a disclose display panel of Claim 1 (see above), providing a motherboard to be tested, wherein the motherboard to be tested comprises a plurality of display panels of claim 1; providing a detection power supply, wherein the detection power supply comprises a plurality of electric signal output terminals (Baek-fig.1-3, power source Vdd, Vint, Vss); electrically connecting the plurality of electrical signal output terminals of the detection power supply to corresponding detection pads of the detection pad portion (Baek-fig.1-3; para.0087,0090,0085,0097, 0118-0122; power source Vdd, Vint via pad P1, and Vss via pad P2 ); turning on the detection power supply, and lighting the plurality of light-emitting diodes in the display panel, to detect whether all of the plurality of light-emitting diodes in the display panel are normally lighted (Baek- para.0118-0123; LV-para.0064, 0076-079); and cutting the motherboard to be tested to form the plurality of display panels, wherein the detection pad portion is disposed at the non-edge portion of the substrate (Baek-fig.1-2; pads PA1-PA2; LV-fig.8,12-pads 52).
Baek et al. in view of Nathan et al., as modified by LV et al. do not expressly disclose providing a motherboard to be tested, wherein the motherboard to be tested comprises a plurality of display panels; cutting the motherboard to be tested to form the plurality of display panels.
Jiang et al. discloses providing a motherboard to be tested, wherein the motherboard to be tested comprises a plurality of display panels (para.0047); and cutting the motherboard to be tested to form the plurality of display panels (para.0047-0049).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Baek et al. in view of Nathan et al., as modified by LV et al. al, with the teachings of Jiang et al., the motivation being to test the display motherboard, thereby preventing the display device from poor display.
As to Claim 11, Baek et al. in view of Nathan et al., as modified by LV et al. and Jiang al., disclose wherein the detect whether all of the plurality of light-emitting diodes in the display panel are normally lighted comprises: in response to determine a light-emitting diode being damaged, repairing the damaged light-emitting diode (Baek-para.0123).
As to Claim 13, Baek et al. in view of Nathan et al., as modified by LV et al. and Jiang al., disclose wherein the detection sub-circuit further comprises a detection driving terminal (Baek-fig.3, transistor M3); and the detection pad portion further comprises a third detection pad, and the third detection pad is electrically connected to detection driving terminals of detection sub-circuits of the plurality of pixel driving circuits (Baek-fig.3, para.0089, signal pad SP transmit gate signals).
As to Claim 15, Baek et al. in view of Wu et al., as modified by Jiang et al., disclose a gate electrode of the detection transistor is the detection driving terminal (Baek-fig.3, gate of transistor M3).
Claim(s) 12, 14, 16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US 2023/0069326) in view of Nathan et al. (US 2007/0195020), further in view of LV et al. (US 2021/0091281), further in view of Jiang et al. (US 2021/0183282), and further in view of Zhu et al. (US 2017/0263187).
As to Claim 12, Baek et al. in view of Nathan et al., as modified by LV et al. and Jiang et al., disclose wherein the detection sub-circuit further comprises a detection driving terminal (Baek-fig.3, gate of transistor M3). Baek et al. in in view of Nathan et al., as modified by LV et al. and Jiang et al., do not expressly disclose the detection driving terminal of the detection sub-circuit is electrically connected to the detection input terminal.
Zhu et al. discloses a transistor having a driving terminal electrically connected to the input terminal (fig.2, gate electrode and first electrode of transistor T1 connected scan signal S1; para.0036,0039).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Baek et al. in in view of Nathan et al., as modified by LV et al. and Jiang et al., with the teachings of Zhu et al., such that the driving terminal of detection transistor (M3) is electrically connected to the input terminal (as disclosed by Zhu et al). The motivation being so that input voltage signal may not only act to turn the transistor, but further act as an initiation voltage to initiate the driving transistor and the light emitting element. Thus, the layout area of the pixel driving circuit may be reduced.
As to Claim 14, Baek et al. in in view of Nathan et al., as modified by LV et al., Jiang et al., and Zhu et al., disclose wherein a gate electrode of the detection transistor is the detection driving terminal (Baek-fig.3, gate of transistor M3).
As to Claim 16, Baek et al. in in view of Nathan et al., as modified by LV et al., Jiang et al., and Zhu et al., disclose a plurality of first detection wirings (Baek-fig.13; Vdd and Vint), and the plurality of first detection wirings are configured to electrically connect first electrodes of the plurality of light-emitting diodes to the first detection pad (Baek-fig.1-3; Vdd and Vint lines connect pad P1 to electrode ET1).
As to Claim 18, Baek et al. in in view of Nathan et al., as modified by LV et al., Jiang et al., and Zhu et al., disclose wherein an output terminal of the switching transistor is electrically connected to a driving terminal of the driving transistor and a first capacitor electrode plate of the storage capacitor (Baek-fig.3, terminal of transistor M2 connected to gate of driving transistor M1 and capacitor Cst), and an output terminal of the driving transistor is electrically connected to the first electrode of the corresponding one of the plurality of light-emitting diodes and the capacitor electrode plate of the storage capacitor (Baek-fig.3, terminal of driving transistor M1 connected to electrode ET1 of light emitting element LD and capacitor Cst).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection applied as necessitated by amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 fomr.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
