DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 13 and 14.
Pending: 1-14.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 5/29/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: PACKAGE STRUCTURE WITH LIMITING CONNECTORS BETWEEN PACKAGES AND REDISTRIBUTION CIRCUIT STRUCTURE.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 and 11-14 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Jeng et al., US PG pub. 20180068978 A1.
Re: Independent Claim 1, Jeng discloses a first redistribution circuit structure (20, fig. 10); at least one third chip (30, fig. 10) disposed on the first redistribution circuit structure (20, fig. 10); a third encapsulant (40, fig. 10) disposed on the first redistribution circuit structure (20, fig. 10) and covering the third chip (30, fig. 10); a second redistribution circuit structure (70, fig. 10) disposed on the third encapsulant (40, fig. 10) and electrically connected to the third chip (30, fig. 10); a conductive connector (84, fig. 10) penetrating through the third encapsulant (40, fig. 10) so that the first redistribution circuit structure (20, fig. 10) and the second redistribution circuit structure (70, fig. 10) are electrically connected; a first package (left 50, fig. 10) disposed on the second redistribution circuit structure (70, fig. 10) and comprising a first chip (left 50, fig. 10) and a first encapsulant (58, fig. 10) covering the first chip (left 50, fig. 10); a second package (right 50, fig. 10) disposed on the second redistribution circuit structure (70, fig. 10) and comprising a second chip (right 50, fig. 10) and a second encapsulant (59, fig. 10) covering the second chip (right 50, fig. 10); and a plurality of limiting connectors (76, fig. 8E) disposed between the first package (left 50, fig. 10) and the second redistribution circuit structure (70, fig. 10) and between the second package (right 50, fig. 10) and the second redistribution circuit structure (70, fig. 10).
Re: Claim 2, Jeng disclose(s) all the limitations of claim 1 on which this claim depends. Jeng further discloses: wherein each of the first chip (left 50, fig. 10) and the second chip (right 50, fig. 10) comprise a corresponding photoelectric conversion chip (¶0036), and a top surface of the first package (left 50, fig. 10) a top surface of the second package (right 50, fig. 10) are coplanar.
Re: Claim 3, Jeng disclose(s) all the limitations of claim 1 on which this claim depends. Jeng further discloses: wherein the limiting connectors (76, fig. 8E) are at least partially overlapped (covered with 58 or 59, fig. 10) with the first encapsulant (58, fig. 10) or the second encapsulant (59, fig. 10).
Re: Claim 4, Jeng disclose(s) all the limitations of claim 1 on which this claim depends. Jeng further discloses: wherein the limiting connectors (76, fig. 8E) are not in contact with any of the first chip (left 50, fig. 10) and the second chip (right 50, fig. 10).
Re: Claim 5, Jeng disclose(s) all the limitations of claim 1 on which this claim depends. Jeng further discloses: the first package (left 50, fig. 10) further comprises a first circuit structure (51, fig. 10) disposed on the first chip (left 50, fig. 10), the first circuit structure (51, fig. 10) is electrically connected to the first chip (left 50, fig. 10), and the limiting connectors (76, fig. 8E) are not directly electrically connected to the first chip (left 50, fig. 10) via the first circuit structure (51, fig. 10); or the second package (right 50, fig. 10) further comprises a second circuit structure (middle 50, fig. 10) disposed on the second chip (right 50, fig. 10), the second circuit structure (middle 50, fig. 10) is electrically connected to the second chip (right 50, fig. 10), and the limiting connectors (76, fig. 8E) are not directly electrically connected to the second chip (right 50, fig. 10) via the second circuit structure (middle 50, fig. 10).
Re: Claim 6, Jeng disclose(s) all the limitations of claim 1 on which this claim depends. Jeng further discloses: wherein at least one of the first package (left 50, fig. 10) and the second package (right 50, fig. 10) corresponds to at least four of the limiting connectors (76, fig. 8E), and the four limiting connectors (76, fig. 8E) respectively correspond to four sides or four corners of at least one in the first package (left 50, fig. 10) and the second package (right 50, fig. 10).
Re: Claim 11, Jeng disclose(s) all the limitations of claim 1 on which this claim depends. Jeng further discloses: wherein the limiting connectors (76, fig. 8E) are not structures made entirely of solder (not made of solder).
Re: Claim 12, Jeng disclose(s) all the limitations of claim 1 on which this claim depends. Jeng further discloses: a plurality of connecting terminals (connecting pads between 50 and 70, fig. 10; overall connecting structure include material conductive and non-conductive) disposed between the first package (left 50, fig. 10) and the second redistribution circuit structure (70, fig. 10) and between the second package (right 50, fig. 10) and the second redistribution circuit structure (70, fig. 10), wherein: an overall structure of the connecting terminals is different from an overall structure of the limiting connectors (76, fig. 8E); an overall material of the connecting terminals is different from an overall material of the limiting connectors (76, fig. 8E); or an overall conductivity of the connecting terminals is different from an overall conductivity of the limiting connectors (76, fig. 8E).
Re: Independent Claim 13, Jeng discloses a first redistribution circuit structure (20, fig. 10); a chip (30, fig. 10) disposed on the first redistribution circuit structure (20, fig. 10); a second redistribution circuit structure (70, fig. 10) disposed on the chip; a plurality of packages (50, fig. 10) disposed on the second redistribution circuit structure (70, fig. 10), and each of the packages comprises an encapsulant (58 and 59, fig. 10); and a plurality of limiting connectors (76, fig. 8E) disposed between each of the packages and the second redistribution circuit structure (70, fig. 10), and the limiting connectors (76, fig. 8E) are not structures made entirely of solder.
Re: Independent Claim 14, Jeng discloses disposing at least one third chip (30, fig. 10) on a first redistribution circuit structure (20, fig. 10); forming a conductive connector (84, fig. 10) on the first redistribution circuit structure (20, fig. 10); forming a third encapsulant (40, fig. 10) on the first redistribution circuit structure (20, fig. 10), wherein the third encapsulant (40, fig. 10) covers the third chip (30, fig. 10); after the conductive connector (84, fig. 10) and the third encapsulant (40, fig. 10) are formed, the conductive connector (84, fig. 10) penetrates through the third encapsulant (40, fig. 10); forming a second redistribution circuit structure (70, fig. 10) on the third encapsulant (40, fig. 10), wherein the second redistribution circuit structure (70, fig. 10) is electrically connected to the third chip (30, fig. 10), and the first redistribution circuit structure (20, fig. 10) and the second redistribution circuit structure (70, fig. 10) are electrically connected by the conductive connector (84, fig. 10); and disposing a first package (left 50, fig. 10) and a second package (right 50, fig. 10) on the second redistribution circuit structure (70, fig. 10), and there are a plurality of limiting connectors (76, fig. 8E) between the first package (left 50, fig. 10) and the second redistribution circuit structure (70, fig. 10) and between the second package (right 50, fig. 10) and the second redistribution circuit structure (70, fig. 10), wherein the first package (left 50, fig. 10) comprises a first chip (left 50, fig. 10) and a first encapsulant (58, fig. 10) covering the first chip (left 50, fig. 10), and the second package (right 50, fig. 10) comprises a second chip (right 50, fig. 10) and a second encapsulant (59, fig. 10) covering the second chip (right 50, fig. 10).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jeng et al., US PG pub. 20180068978 A1; in view of Yeh et al., US PG pub. 20180108602 A1.
Re: Claim 7, Jeng discloses all the limitations of claim 1 on which this claim depends. Jeng is silent regarding wherein the limiting connectors (76, fig. 8E) comprise a core and a connecting layer covering the core.
Yeh teaches an outer shell core connecting layer (42, fig. 4) comprise a core (420, fig. 4) and a connecting layer (11, fig. 4) covering the core.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include outer shell conductive layer since an outer shell connecting layer can enhanced electrical and thermal performance.
Re: Claim 8, Jeng and Yeh discloses all the limitations of claim 7 on which this claim depends. Jeng is silent regarding the connecting layer comprises an outer shell layer;
a material of the core is polymer; and
a material of the outer shell layer comprises a metal.
Yeh teaches a outer shell layer connecting layer (42, fig. 4) with an outer shell layer (421-423, fig. 4) made of metal, a core that is made of polymer (¶0051), that can form on the outer corner of the device.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include outer shell conductive layer since an outer shell connecting layer can enhanced electrical and thermal performance.
Re: Claim 9, Jeng and Yeh discloses all the limitations of claim 8 on which this claim depends. Jeng is silent regarding the connecting layer further comprises an inner shell layer;
the inner shell is disposed between the outer shell layer and the core;
a material of the inner shell layer comprises a metal; and
a melting point of the outer shell layer is lower than a melting point of the inner shell layer.
Yeh teaches a outer shell layer connecting layer (42, fig. 4) with an outer shell layer (421, fig. 4) made of metal , a core that is made of polymer (¶0051), that can form on the outer corner of the device.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include outer shell conductive layer since an outer shell connecting layer can enhanced electrical and thermal performance.
Re: Claim 10, Jeng and Yeh discloses all the limitations of claim 7 on which this claim depends. Jeng is silent regarding wherein a material of the core is a high-melting point metal or a hard metal (421, fig. 4; ¶0051).
Yeh teach wherein a material of the core is a high-melting point metal or a hard metal (421, fig. 4; ¶0051).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include outer shell conductive layer that made out of high melting point metal since an outer shell connecting layer with a high melting point metal can enhanced electrical and thermal performance.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Yu et al., US PG pub. 20220352082 A1”) Discloses a semiconductor device includes a first plurality of dies on a wafer, a first redistribution structure over the first plurality of dies, and a second plurality of dies on the first redistribution structure opposite the first plurality of dies. The first redistribution structure includes a first plurality of conductive features. Each die of the first plurality of dies are bonded to respective conductive features of the first plurality of conductive features by metal-metal bonds on a bottom side of the first redistribution structure. Each die of the second plurality of dies are bonded to respective conductive features of the first plurality of conductive features in the first redistribution structure by metal-metal bonds on a top side of the first redistribution structure.
* (“Chen et al., US Patent 9666502 B2”) discloses a package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898