DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5 and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choe et al. (USPN 5,629,614).
With respect to claim 1, Choe et al. discloses, in Fig. 4,a reference signal generation circuit (Fig. 4), comprising:
a voltage-to-current (V21) converter (10 with 31) having a terminal (drain of M1) and configured to generate a current (drain current) that increases as an input voltage increases (as VIN increases the current produced by M1 increases);
a first current mirror (M2 with M7) having a first terminal (gate/drain terminal of M2) and a second terminal (drain terminal of M7), the first terminal coupled to the terminal of the V21 converter (connected as claimed at node d);
a second current mirror (M9 with M10) having a first terminal (source terminal of M9), a second terminal (source terminal of M10), and a third terminal (gate/drain terminal of M10), the first terminal of the second current mirror coupled to the second terminal of the first current mirror (drain of M7 directly connected to the source of M9); and
a third current mirror (M11 with M12) having a first terminal (drain/gate terminal of M11) coupled to the second terminal of the first current mirror (via the source to drain conduction path of M9), and the third current mirror coupled to the third terminal of the second current mirror (drain of M12 connected to the drain/gate of M10 at node e).
With respect to claim 2, the reference signal generation circuit of claim 1, wherein the third current mirror has a second terminal (source terminals of M11 and M12), and the reference signal generation circuit further comprises a fourth current mirror (M5 with M6) having a first terminal coupled to the second terminal of the third current mirror (sources of M5 and M6 coupled to the sources of M11 and M12 at the VSS node).
With respect to claim 3, the reference signal generation circuit of claim 2, wherein the third current mirror has a first field effect transistor (FET) (M11) and a second FET (M12), the first FET has a source terminal (source), the second FET has a source terminal (source), and the source terminals of the first and second FETs are coupled together (sources of M11 and M12 are coupled together) and to the third terminal of the second current mirror (via the source to drain conduction path of M10 and the drain to source conduction path of M12, i.e., source of M10 is connected to the drain of M12, the drain of M12 is connected to M12 via the drain to source conduction path of M12, and the source of M12 is connected to M11 at the VSS terminal).
With respect to claim 5, the reference signal generation circuit of claim 1, further comprising a current source circuit (M8, M8 produces a current that is provide to the source, i.e., first terminal, of M10. Thus, M8 is interpreted as a “current source circuit”) having terminal coupled to the first terminal of the second current mirror (gate/drain of M8 connected to the source of M10).
With respect to claim 6, the reference signal generation circuit of claim 5, wherein the third current mirror has a second terminal (source terminals of M11 and M12), and the reference signal generation circuit further comprises a fourth current mirror (M5 with M6) having a first terminal coupled to the second terminal of the third current mirror (sources of M5 and M6 coupled to the sources of M11 and M12 at the VSS node).
Claim(s) 1, 5-7 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (USPN 7,391,169).
With respect to claim 1, Huang et al. discloses, in Fig. 7, a reference signal generation circuit (Fig. 7), comprising:
a voltage-to-current (V2I) converter (720 with 701) having a terminal (drain of 701) and configured to generate a current (drain current of 701) that increases as an input voltage increases (as VIN increases the current produced by 701 increases, see equation 12 of Col. 12);
a first current mirror (702 with 708) having a first terminal (source of 702) and a second terminal (drain terminal of 708), the first terminal coupled to the terminal of the V21 converter (connected as claimed at drain of 701 and source of 702);
a second current mirror (704 with 706) having a first terminal (drain of 706), a second terminal (gate/drain of 704), and a third terminal (source of 704), the first terminal of the second current mirror coupled to the second terminal of the first current mirror (drain of 706 directly connected to the drain of 708); and
a third current mirror (703 with 705) having a first terminal (drain of 705) coupled to the second terminal of the first current mirror (to drain of 708 via the source to drain conduction path of 706), and the third current mirror coupled to the third terminal of the second current mirror (drain/gate of 703 connected to the source of 704).
With respect to claim 5, the reference signal generation circuit of claim 1, further comprising a current source circuit (e.g., 708) having terminal coupled to the first terminal of the second current mirror ( drain connection of 708 to drain connection of 706. Note the “first terminal” of the “second current mirror” that is connected to “the second terminal” of the “first current mirror”, as required by claim 1, is 642 of Applicant’s Fig. 6 and Fig. 7 of Applicant’s instant drawings. It can be seen that the only “current source” that is connected to 642 is current mirror 620/transistor 6526 of Figs. 6 and 7. Thus, Applicant double includes the transistor that is connected to the second terminal of the first current mirror as the current source. Therefore, Examiner reads the transistor, i.e., 708, that is connected to the second output of the first current mirror, i.e., 702 with 708, as the “current source” as is consistent with Applicant’s “current source”).
With respect to claim 6, the reference signal generation circuit of claim 5, wherein the third current mirror has a second terminal (source terminals of 703 and 705), and the reference signal generation circuit further comprises a fourth current mirror (707, which is interpreted as a “current mirror” since 707 copies/mirrors the current output from 701) having a first terminal coupled to the second terminal of the third current mirror (sources of 703 and 705 coupled to the source of 707)
With respect to claim 7, the reference signal generation circuit of claim 6, wherein the terminal of the fourth current mirror is a first terminal (source terminal of 707 is a first terminal), the fourth current mirror has a second terminal (drain terminal of 707), and the reference signal generation circuit includes a resistor coupled to the second terminal of the fourth current mirror (resistor 734 connected to the drain of 707 via the source to drain conduction path of 708).
With respect to claim 21, the reference signal generation circuit of claim 1, having an output terminal (Vout), wherein a voltage on the output terminal increases as a function of the input voltage over a first input voltage range (from Voffset to maximum Vin of Fig. 1), and the voltage on the output terminal is approximately constant within a second input voltage range above the first input voltage range (once Vin hits a maximum voltage and stays at the maximum value the circuit will operate as claimed and provide the functional claim limitations).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (USPN 7,391,169).
With respect to claim 4, Huang et al. discloses, the reference signal generation circuit of claim 1, wherein the second current mirror has a current mirror ratio of 1:n between the first terminal of the second current mirror and the third terminal of the second current mirror (the current inherent mirror ratio of 704 and 706 is set according to the sizing of 704 and 706);
the third current mirror has a second terminal (source terminal of 703 having a current equal to the drain current, i.e., the drain to source current) and a current mirror ratio of 1:m between the first terminal of the third current mirror and the second terminal of the third current mirror (the inherent current mirror ration of 703 and 705 set according to the sizing of 703 and 705).
Huang et al. fails to disclose the specific sizing between 703 and 705. Thus, Huang et al. fails to disclose “wherein m is different than n”.
However, it is noted that the value of Iout is set, at least in part, according to the current mirror ratio of 703 and 705 (see Col. 12 lines 28-47).
Thus it would have been obvious to set the current mirror ratio of “m” to any desired value including one wherein m is different from n, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to set Iout to a desired value as suggested by Huang et al.
Allowable Subject Matter
Claims 8-11 and 13-20 are allowed.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THOMAS J. HILTUNEN/ Primary Examiner, Art Unit 2836
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