DETAILED ACTION
This Office action is in response to the application/amendment filed on .
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Response to Arguments
Applicant's arguments filed 13 January 2026 with respect to claim 1 have been fully considered but they are not persuasive.
Applicant merely argues that claim 1 has been amended to include the allowable subject matter of claim 5 (Remarks at p. 12). However, it is respectfully asserted that this is not the case, as claim 5 was indicated to contain allowable subject matter encompassing the claim as a whole. Claim 5 as originally filed includes eight, ninth, tenth and eleventh transistors and a diode, all having particular terminals with particular coupling interrelationships with each other and with the remaining claimed circuitry. Moreover, claim 5 depends from claim 4, which depended from claim 3, which depended from claim 2, which depended from claim 1. Thus the indication of allowable subject matter was predicated not only on the language of claim 5 itself, but also the combination of such with all of the subject matter included in the chain of dependency of the claim.
Applicant has merely taken the eight transistor from claim 5 by itself and moved it to the independent claim. Examiner respectfully asserts that the applied prior art in Tai (US 2022/0171416) clearly discloses additional transistors to those cited in correspondence to claim 1 (Tai at Fig. 9). The rejections of claims 1-4 as being anticipated by Tai have been maintained.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tai (US 2022/0171416).
Examiner’s note: the claimed term, “coupled” has been broadly interpreted in light of the specification to include any manner of coupling (direct, indirect, physical, electrical, etc.) that does not preclude the components from operating substantially in the manner as described by Applicant). If two components, or two terminals of components, are included within the same circuit structure of an apparatus that has a substantially similar functionality as Applicant’s claimed invention, they will be considered to be coupled.
In re claim 1, Tai discloses a circuit (Fig. 3) comprising: a first transistor having a first terminal, a second terminal, and a control terminal (transistor M1 with terminals SN, DN, GN);
a second transistor having a first terminal, a second terminal, and a control terminal (within circuit 320: see detail in e.g., Fig. 9: transistor M2 with drain, source, and gate terminals), the first terminal of the second transistor coupled to the control terminal of the first transistor (Fig. 9: at node SDN1, via M4), the second terminal of the second transistor coupled to the second terminal of the first transistor (Fig. 9: at nodes SDN2/VPRN: see [0021]);
a third transistor having a first terminal, a second terminal, and a control terminal (Fig. 9: IM1 having source, drain, and gate), the first terminal of the third transistor coupled to a voltage supply terminal (at VN1), the second terminal of the third transistor coupled to the control terminal of the second transistor (at LN41);
a fourth transistor having a first terminal, a second terminal, and a control terminal (Fig. 9: IM2 having drain, source and gate), the first terminal of the fourth transistor coupled to the control terminal of the second transistor (at LN41), the second terminal of the fourth transistor coupled to the second terminal of the second transistor (at SDN2); and
a fifth transistor having a first terminal, a second terminal, and a control terminal (Fig. 9: M3 having source, drain, and gate), the first terminal of the fifth transistor coupled to the first terminal of the first transistor (M3 coupled to M1 at V1 through M3 and R1, or through SDN2 and M1), the second terminal of the fifth transistor coupled to the control terminal of the fourth transistor (M3 coupled to IM2 at LN3 through M3 or through IM2); and
an eighth transistor having a first terminal, a second terminal, and a control terminal (Fig. 9: M4 having drain, source, gate terminals), the second terminal of the eighth transistor coupled to the first terminal of the first transistor (Fig. 9: M4 coupled to source of M1 via the gate of M1, for example).
In re claim 2, Tai discloses first control circuitry having a first terminal and a second terminal (Fig. 4: 422-1 having terminals at KN1, VGN3, KN2, and KN3), the first terminal of the first control circuitry coupled to the control terminal of the third transistor (422-1 coupled to IM1 at KN3); and
second control circuitry having a first terminal and a second terminal (426 having terminals at VGN1, VGN2, VGN3), the first terminal of the second control circuitry coupled to the control terminal of the fifth transistor (426 coupled to M3 at VGN3), the second terminal of the second control circuitry coupled to the second terminal of the first control circuitry (426 coupled to 422-1 at VGN1/KN1).
In re claim 3, Tai discloses a first resistor coupled between the first terminal of the first transistor and the first terminal of the fifth transistor (Fig. 4: R1 coupled between source of M1 at node VN1 and drain of M3 at KN3); and
a second resistor having a first terminal and a second terminal (see detail of circuit 426 shown in Fig. 5(a): R2 or R3), the first terminal of the second resistor coupled to the second terminal of the fifth transistor (Figs. 4 and 5: e.g., resistor R3 coupled to drain or source of M3 through VGN3 and M3), the second terminal of the second resistor coupled to the second terminal of the first transistor (Figs. 3, 4 and 5: R3 coupled to drain of M1 through reference node VN2 and implied load connected between VN2 and Vout: see [0017]).
In re claim 4, Tai discloses (see alternative circuitry of Fig. 9, including all of the circuit components from Fig. 4 cited above and further including …) a sixth transistor having a first terminal, a second terminal, and a control terminal (IM3 having source, drain, and gate), the first terminal of the sixth transistor coupled to the voltage supply terminal (VN1), the second terminal of the sixth transistor coupled to the control terminal of the first transistor (Fig. 9: IM3 coupled to gate of M1 through M4); and
a seventh transistor having a first terminal, a second terminal, and a control terminal (IM4 having drain, source, and gate), the first terminal of the seventh transistor coupled to the control terminal of the first transistor (IM4 coupled to gate of M1 through M4), the second terminal of the seventh transistor coupled to the second terminal of the first transistor IM4 coupled to drain of M1 at SDN2/Vout: see [0021]), the control terminal of the seventh transistor coupled to the control terminal of the sixth transistor and the second terminal of the second control circuitry (gate of IM4 coupled to gate of IM3 and coupled to circuit 426 through IM1/IM2/M3).
Allowable Subject Matter
Claims 9-12 and 14-21 are allowed.
Claims 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The statements of reasons for indicating allowability in the above-mentioned claims may be found in the non-final Office action dated 11 August 2025.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838