DETAILED ACTION
The Examiner acknowledges the applicant's submission of the amendment dated 2/18/2026.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7, 8, 10-13, 15, 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al (US 2024/0281146) in view of Bose et al (US 8,949,101).
Regarding Claim 1, Zhang teaches a method for memory pool management, the method comprising:
receiving, by a memory-pool manager (processor 10 of Fig. 1), a memory request from an application (step 201 of Fig. 2, an allocation [memory] request from a program [application] is received), the memory-pool manager being communicatively coupled to a memory pool (memory pool corresponding to storage system 20 of Fig. 1) comprising a first memory module, of a first type (storage space 21 of Fig. 1, which uses a first type of fault tolerance, Paragraph 0086), and a second memory module, of a second type (storage space 21 of Fig. 1, which uses a second type of fault tolerance, Paragraph 0086), the first type being different from the second type;
determining, by the memory-pool manager, based the memory request, an error tolerance associated with the application (step 203 of Fig. 2, Paragraph 0056, and this is based on a reliability corresponding to the size of the storage space of the request, “size of the storage space corresponding to the allocation request,” Paragraph 0055); and
allocating a memory space from the first memory module or from the second memory module to the application based on the error tolerance (step 204 of Fig. 2, Paragraph 0067).
However, the cited prior art does not explicitly teach an error tolerance associated with the application based on a statistical fault injection (SFI).
Bose teaches an error tolerance associated with an application based on a statistical fault injection (“an application fault injector that is used to inject faults” to determine an error tolerance/mean time to failure, C6 L14-39).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the error tolerance of application (as taught by Bose) in order to add “additional error detection and recovery features into the design” if necessary (C6 L40-55).
Regarding Claim 2, the cited prior art teaches the method of claim 1, wherein the first memory module comprises a first memory having a higher reliability than a second memory of the second memory module (Paragraph 0086).
Regarding Claim 3, the cited prior art teaches the method of claim 2, wherein the first memory module stores a recovery code (all fault tolerance levels may use a recovery code/ECC, Paragraph 0086).
Regarding Claim 4, the cited prior art teaches the method of claim 1, further comprising:
receiving, by the memory-pool manager, a second memory request from a second application (step 201 of Fig. 2, an allocation [memory] request from a program [application] is received);
wherein the memory pool manager determines a second error tolerance based on a reliability parameter indicating opportunistic reliability (using the definition of opportunistic reliability given on Paragraph 0052 of applicant’s specification, the application takes advantage of memory availability of the given error tolerance according to the process of Fig. 2, and therefore the reliability indicator indicates an opportunistic reliability).
Regarding Claim 7, the cited prior art teaches the method of claim 1, further comprising:
receiving, by the memory-pool manager, a second memory request from a second application (such as a second request received at step 201 of Fig. 2),
wherein the memory-pool manager determines the error tolerance based on a probability of an incorrect output (an MVF/memory vulnerability factor is calculated, and a higher MVF indicates a higher probability of an incorrect output, and this is used to determine error tolerance, Paragraph 0088).
Regarding Claim 8, the cited prior art teaches the method of claim 7, wherein the memory-pool manager calculates the probability of the incorrect output based on a processing circuit associated with the memory pool (processing circuit corresponding to hardware simulator 41 of Fig. 4, Paragraph 0088).
Claim 10 is the system corresponding the method of claim 1, and is rejected under similar rationale.
Claim 11 is the system corresponding the method of claim 2, and is rejected under similar rationale.
Claim 12 is the system corresponding the method of claim 3, and is rejected under similar rationale.
Claim 13 is the system corresponding the method of claim 4, and is rejected under similar rationale.
Claim 15 is the system corresponding the method of claim 7, and is rejected under similar rationale.
Claim 17 is the device corresponding the method of claim 1, and is rejected under similar rationale.
Regarding Claim 18, the cited prior art teaches the device of claim 17, wherein: the computer-readable medium is distinct from the first memory module and the second memory module (the instructions may be on a ROM, distinct from the RAM, Paragraph 0109); and the first memory module comprises a first memory having a higher reliability than a second memory of the second memory module (Paragraph 0086).
Claim 20 is the device corresponding the method of claim 7, and is rejected under similar rationale.
Claims 5, 6, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Bose et al (US 8,949,101) and Keeton et al (US 2007/0050686).
Regarding Claim 5, the cited prior art teaches the method of claim 1, further comprising:
receiving, by the memory-pool manager, a second memory request from a second application (such as a second request received at step 201 of Fig. 2), but does not explicitly teach wherein the memory-pool manager determines a second error tolerance based on inputting a fault into the second application.
Keeton teaches to determine an error tolerance based on inputting a fault into the application (Paragraph 0003).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the determining of Keeton in the cited prior in order to determine the best place to allocate memory.
Regarding Claim 6, the cited prior art teaches the method of claim 5, wherein the memory-pool manager determines the error tolerance based on analyzing an output associated with inputting the fault into the application (Paragraph 0003 of Keeton).
Claim 14 is the system corresponding the method of claim 5, and is rejected under similar rationale.
Claim 19 is the device corresponding the method of claim 5, and is rejected under similar rationale.
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Bose et al (US 8,949,101) and Chen et al (US 2024/0231653).
Regarding Claim 9, the cited prior art teaches the method of claim 1, but does not explicitly teach wherein the memory-pool manager is in communication with the memory pool via a cache-coherent protocol.
Chen teaches wherein a memory-pool manager (processor 210 of Fig. 2) is in communication with a memory pool (first and second memory medium of Fig. 2) via a cache-coherent protocol (CCIX protocol, Paragraph 0037).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the cache-coherent protocol of Chen in the cited prior art in order to synchronize a cache with memory.
Regarding Claim 16, the cited prior art teaches the system of claim 10, wherein: the computer-readable medium is distinct from the first memory module and the second memory module (the instructions may be on a ROM, distinct from the RAM, Paragraph 0109), but does not explicitly teach the processing circuit is in communication with the memory pool via a cache-coherent protocol.
Chen teaches wherein a memory-pool manager (processor 210 of Fig. 2) is in communication with a memory pool (first and second memory medium of Fig. 2) via a cache-coherent protocol (CCIX protocol, Paragraph 0037).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the cache-coherent protocol of Chen in the cited prior art in order to synchronize a cache with memory.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's argument that the cited prior art fails to teach the claims as amended has been considered and is persuasive. Thus, the prior rejections have been withdrawn. However, a new rejection has been made as noted above.
CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have been rejected in the application.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:00- 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135