Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are presented for examination. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 19-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims recite “ partitioning elements of the vector into a first subset of elements with even indices and a second subset of elements with odd indices; and applying a reduction operation to combine elements from the second subset of elements with corresponding elements from the first subset of elements to obtain a first set of reduced elements ” (claim 19) and “ determining whether the vector has an odd number of elements; and in response to the vector having an odd number of elements, applying the reduction operation to an unmatched member of the first subset of elements and an identity value of the reduction operation ” (claim 20) . The partitioning, applying, and determining limitations are process es that, under their broadest reasonable interpretation, cover performance of the limitation s in the mind but for the recitation of generic computer components . That is, other than “ reading a vector from a physical register of a vector register file or from bypass circuitry ”, nothing in the claim elements precludes the steps from practically being performed in the mind. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. This judicial exception is not integrated into a practical application. In particular, the claim only recites one additional element – reading a vector from a physical register of a vector register file or from bypass circuitry . The element is recited at a high-level of generality (i.e., as a generic register performing a generic storage of vector data, or generic bypass circuitry providing data ) such that it amounts to no more than mere ly apply ing the exception using a generic computer component. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Retrieving data is an insignificant-extra solution activity. The claim is directed to an abstract idea. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception . As discussed above with respect to integration of the abstract idea into a practical application, the additional element of retrieving data amounts to no more than mere ly apply ing the exception using a generic computer component. Mere apply ing an exception using a generic computer component cannot provide an inventive concept. Retrieving data from registers or circuitry is well-understood, routine, conventional activity. The claim is not patent eligible. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Willcock, US Patent Application Publication 2016/0098208 (hereinafter Willcock) in view of Kunzman et al., US Patent Application Publication 2016/0179537 (hereinafter Kunzman ). Regarding claim 1, Willcock teaches: An integrated circuit comprising: an execution circuitry configured to, responsive to a folding micro-op (see e.g. para. [0030], [0063], sensing circuitry performing/executing logical operations/instructions such as a reduction operation) : read a vector from memory cells (see e.g. para. [0050]) ; partition elements of the vector into a first subset of elements with even indices and a second subset of elements with odd indices (see e.g. para. [0050], vector data is split into even and odd indexed elements) ; and apply a reduction operation to combine elements from the second subset of elements with corresponding elements from the first subset of elements to obtain a first set of reduced elements (see e.g. para. [0050-2] , [0063-4], a reduction operation is performed on even indexed elements and odd indexed elements ) . Willcock fails to explicitly teach wherein the memory cells are a vector register file configured to store register values of an instruction set architecture in physical registers . Kunzman teaches a vector register file configured to store register values of an instruction set architecture in physical registers (see e.g. para. [0036], [0097], [0108]) . Willcock recognizes the logical equivalence and interchangeability of performing operations on data in memory or performing operations on data in registers (see e.g. para. [0028-30]), each with their advantages. Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Willcock and Kunzman such that the vector data are read from a vector register file configured to store register values of an instruction set architecture in physical registers . This would have provided the clearly predictable result of performing the same operation on data simply sourced from a different location. This would have also provided increased flexibility in sourcing data for the reduction operation using fast and well-known storage such as registers. Regarding claim 2, Willcock in view of Kunzman teaches or suggests: The integrated circuit of claim 1, wherein the execution circuitry is configured to, where the vector has an odd number of elements, apply the reduction operation to an unmatched member of the first subset of elements and an identity value of the reduction operation (see e.g. Willcock para. [0056], an empty/unmatched element can have an identity value applied) . Regarding claim 3, Willcock in view of Kunzman teaches or suggests: The integrated circuit of claim 1, wherein the reduction operation is one of integer addition or floating-point addition (see e.g. Willcock para. [0052], Kunzman para. [0098], [0108]) . Regarding claim 4, Willcock in view of Kunzman teaches or suggests: The integrated circuit of claim 1, wherein the reduction operation is an operation from a set of operations that includes integer addition, integer minimum, integer maximum, floating-point addition, floating-point minimum, floating-point maximum, logical AND, logical OR, and logical XOR (see e.g. Willcock para. [0052], Kunzman para. [0108]) . Regarding claim 5, Willcock in view of Kunzman teaches or suggests: The integrated circuit of claim 1, wherein the execution circuitry comprises one or more pipelined execution units (see e.g. Kunzman para. [0104]) . Regarding claim 6, Willcock in view of Kunzman teaches or suggests: The integrated circuit of claim 1, wherein the execution circuitry is configured to, in an early phase of a reduction operation applied to a large vector with elements stored in multiple physical registers of the vector register file: read a third subset of the elements of the large vector from a first physical register of the vector register file or from bypass circuitry; read a fourth subset of the elements of the large vector from a second physical register of the vector register file or from bypass circuitry; and apply the reduction operation to combine elements from the fourth subset of elements with corresponding elements from the third subset of elements to obtain a second set of reduced elements (see e.g. Kunzman para. [0158]) . Regarding claim 7, Willcock in view of Kunzman teaches or suggests: The integrated circuit of claim 6, wherein the execution circuitry is configured to, where the large vector has an odd number of elements, apply the reduction operation to an unmatched member of the third subset of elements and an identity value of the reduction operation (see e.g. Willcock para. [0056]) . Regarding claim 8, Willcock in view of Kunzman teaches or suggests: The integrated circuit of claim 1, comprising a second execution circuitry that is configured to, in an early phase of a reduction operation applied to a large vector with elements stored in multiple physical registers of the vector register file: read a third subset of the elements of the large vector from a first physical register of the vector register file or from bypass circuitry; read a fourth subset of the elements of the large vector from a second physical register of the vector register file or from bypass circuitry; and apply the reduction operation to combine elements from the fourth subset of elements with corresponding elements from the third subset of elements obtain a second set of reduced elements (see e.g. Kunzman para. [0158]) . Regarding claim 9, Willcock in view of Kunzman teaches or suggests: The integrated circuit of claim 8, wherein the second execution circuitry is configured to, where the large vector has an odd number of elements, apply the reduction operation to an unmatched member of the third subset of elements and an identity value of the reduction operation (see e.g. Willcock para. [0056]) . Regarding claim 10, Willcock in view of Kunzman teaches or suggests: The integrated circuit of claim 8, wherein the second execution circuitry comprises one or more pipelined execution units (see e.g. Kunzman para. [0104]) . Claims 11-18 are rejected for reasons corresponding to those given above for claims 1-8. Claims 19-20 are rejected for reasons corresponding to those given above for claims 1-2. Pertinent Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Song et al., US Patent 5,991,531, teaches adding even and odd elements of a vector together. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT JOHN M LINDLOF whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1024 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Mon-Tue 8:30-5:00 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Jyoti Mehta can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 5712703995 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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