DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 08/16/2025 have been fully considered but they are not persuasive.
Applicant argues that Bhutta [US 2023/0082359 A1] does not teach or discloses “A match network comprising: a variable capacitance; one or more solid-state capacitances switchably in parallel with the variable capacitance; and a controller configured to: control the variable capacitance to impedance match to a first impedance state of a plasma load; and switch at least one solid-state capacitance into or out of parallel arrangement with the variable capacitance to impedance match to a second state of the plasma load.” (see page 8-10)
Examiner disagrees:
In response to applicant's arguments against the references individually Bhutta [US 2023/0082359 A1], one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
As broadly as claimed, Bhutta discloses a match network (Fig. 1-2, 11) comprising:
a variable capacitance (Fig. 1-2, 31 & Paragraph [0058]);
Bhutta does not specify one or more solid-state capacitances switchably in parallel with the variable capacitance; and a controller configured to: control the variable capacitance to impedance match to a first impedance state of a plasma load; and switch at least one solid-state capacitance into or out of parallel arrangement with the variable capacitance to impedance match to a second state of the plasma load.
Bhutta discloses in Fig. 3-7, one or more solid-state capacitances (Fig. 3, 33a and Fig. 5, 653) switchably in parallel (Fig. 3-7, Paragraph [0082-83 & 0089]) with the variable capacitance (Fig. 3, 31a); and a controller (Fig. 3, 45) configured to: control the variable capacitance (Fig. 3-7, 31) to impedance match (Paragraph [0100-116]) to a first impedance state of a plasma load (Fig. 3, 19); and switch at least one solid-state capacitance (Fig. 3, 33 and Fig. 7, 653) into or out of parallel arrangement with the variable capacitance (Fig. 3-7, 31a) to impedance match to a second state (Paragraph [0089-90 & 0102 & 0229 & 0240]) of the plasma load (Fig. 3, 19).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention was made to modify Bhutta with one or more solid-state capacitances switchably in parallel with the variable capacitance; and a controller configured to: control the variable capacitance to impedance match to a first impedance state of a plasma load; and switch at least one solid-state capacitance into or out of parallel arrangement with the variable capacitance to impedance match to a second state of the plasma load for purpose of improvement in matching network tune speed and determine a parameter related to the matching network or the plasma chamber; based on the determined parameter, determine from the different positions of the VRE a new position for the VRE to reduce a reflected power at the RF input of the matching network; wherein the power control scheme is configured to be altered; and wherein, while the power control scheme is altered, the matching network alters the VRE to the new position as disclosed by Bhutta (Paragraph [0098 & 0009]).
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Bhutta [US 2023/0082359 A1] is analogues prior art of record and its same field of endeavor as the applicant invention.
Bhutta Figure 6
Applicant Invention
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention was made to modify Bhutta with one or more solid-state capacitances switchably in parallel with the variable capacitance; and a controller configured to: control the variable capacitance to impedance match to a first impedance state of a plasma load; and switch at least one solid-state capacitance into or out of parallel arrangement with the variable capacitance to impedance match to a second state of the plasma load for purpose of improvement in matching network tune speed and determine a parameter related to the matching network or the plasma chamber; based on the determined parameter, determine from the different positions of the VRE a new position for the VRE to reduce a reflected power at the RF input of the matching network; wherein the power control scheme is configured to be altered; and wherein, while the power control scheme is altered, the matching network alters the VRE to the new position as disclosed by Bhutta (Paragraph [0098 & 0009]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bhutta [US 2023/0082359 A1].
In regards to claim 1. Bhutta discloses a match network (Fig. 1-2, 11) comprising:
a variable capacitance (Fig. 1-2, 31 & Paragraph [0058]);
Bhutta does not specify one or more solid-state capacitances switchably in parallel with the variable capacitance; and a controller configured to: control the variable capacitance to impedance match to a first impedance state of a plasma load; and switch at least one solid-state capacitance into or out of parallel arrangement with the variable capacitance to impedance match to a second state of the plasma load.
Bhutta discloses in Fig. 3-7, one or more solid-state capacitances (Fig. 3, 33a and Fig. 5, 653) switchably in parallel (Fig. 3-7, Paragraph [0082-83 & 0089]) with the variable capacitance (Fig. 3, 31a); and a controller (Fig. 3, 45) configured to: control the variable capacitance (Fig. 3-7, 31) to impedance match (Paragraph [0100-116]) to a first impedance state of a plasma load (Fig. 3, 19); and switch at least one solid-state capacitance (Fig. 3, 33 and Fig. 7, 653) into or out of parallel arrangement with the variable capacitance (Fig. 3-7, 31a) to impedance match to a second state (Paragraph [0089-90 & 0102 & 0229 & 0240]) of the plasma load (Fig. 3, 19).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention was made to modify Bhutta with one or more solid-state capacitances switchably in parallel with the variable capacitance; and a controller configured to: control the variable capacitance to impedance match to a first impedance state of a plasma load; and switch at least one solid-state capacitance into or out of parallel arrangement with the variable capacitance to impedance match to a second state of the plasma load for purpose of improvement in matching network tune speed and determine a parameter related to the matching network or the plasma chamber; based on the determined parameter, determine from the different positions of the VRE a new position for the VRE to reduce a reflected power at the RF input of the matching network; wherein the power control scheme is configured to be altered; and wherein, while the power control scheme is altered, the matching network alters the VRE to the new position as disclosed by Bhutta (Paragraph [0098 & 0009]).
In regards to claim 2. Bhutta discloses the match network of claim 1, wherein the controller (Fig. 1-7, 45 and 645) is configured to: tune the variable capacitance (Fig. 1-7, 31) to impedance match to the first impedance state (match configurations via lookup table) based on a first power pulse (Fig. 15, 333) applied (Fig. 14, 15, para. [0181]-[0183], [0187]-[0189]: FIG. 14 provides a flow chart of the exemplified process 300 for impedance matching when the RF input signal has multi-level power setpoints. FIG. 15 provides a graph 330 of RF signal 332 having a first pulse level L1 and second pulse level L2, as well as the times 338, 339 for determining the parameter-related value...Control circuit of the matching network detects whether the first pulse level is being provided (operation 302)...While the first pulse level is being detected (operation 302), the second pulse level is not being detected (operation 312). During this first pulse interval 333, while the first level process 301A is measuring the parameter to determine the parameter- related value and alter the EVCs accordingly, second level process 301B is determining a parameter- related value for the second pulse level (operation 320) without measuring the parameter...At second pulse interval 335, the first pulse level L1 is OFF and the second pulse level L2 is ON. When this occurs, the first pulse level L1 and the second pulse level L2 switch roles) to the plasma load (Fig. 3, 19); and switch (Fig. 5, 653) the at least one solid-state capacitance to impedance match to the second impedance state (match configurations via lookup table) based on a second power pulse (Fig. 15, 333) applied to the plasma load that is different than the first power pulse (Fig. 14, 15, para. [0181 ]-[0183], [0187]-[0189]: FIG. 14 provides a flow chart of the exemplified process 300 for impedance matching when the RF input signal has multi-level power setpoints. FIG. 15 provides a graph 330 of RF signal 332 having a first pulse level L1 and second pulse level L2, as well as the times 338, 339 for determining the parameter-related value...Control circuit of the matching network detects whether the first pulse level is being provided (operation 302)...While the first pulse level is being detected (operation 302), the second pulse level is not being detected (operation 312). During this first pulse interval 333, while the first level process 301A is measuring the parameter to determine the parameter-related value and alter the EVCs accordingly, second level process 301B is determining a parameter-related value for the second pulse level (operation 320) without measuring the parameter...At second pulse interval 335, the first pulse level L1 is OFF and the second pulse level L2 is ON. When this occurs, the first pulse level L1 and the second pulse level L2 switch roles).
In regards to claim 3. Bhutta discloses the match network of claim 2, wherein the controller (Fig. 3-4, 45 and 645) is configured to: determine a first switched configuration (Fig. 5, 661) of the one or more solid-state capacitances (Fig. 5, 653) to impedance match for the first power pulse (Fig. 14-15 and 19, Paragraph [0224-227]); determine a second switched configuration (Fig. 5, 661) of the one or more solid-state capacitances (Fig. 5, 653) to impedance match (Fig. 14-15 and 19 & Paragraph [0224-227]) for the second power pulse (Fig. 15, 335); and toggle between the first switched configuration (Fig. 5, 661) and the second switched configuration (Fig. 5, 661) for the first power pulse (Fig. 15, 335) and the second power pulse (Fig. 14-15 and 19, 335 & Paragraph [0224-227]), respectively.
In regards to claim 4. Bhutta discloses the match network of claim 1, wherein the controller (Fig. 3-5, 45 and 645) is configured to: tune the variable capacitance (Fig. 3, 31) to impedance match to the first impedance state (match configurations via lookup table) based on an average impedance value (Average parameter value) of a plasma load (Fig. 3, 19) over a period of time (Paragraph [0089 & 0103 & 0184 & 0188]); detect an impedance fluctuation of the plasma load (Fig. 3, 19) from the average impedance value (Fig. 6-7, 14-15 & Paragraph [0055 & 0089 & 0093 & 0103 & 0184 & 0188]); and switch the at least one solid-state capacitance (Fig. 5, 653) to impedance match to one or more second impedance states (match configurations via lookup table) based on the detected impedance fluctuation of the plasma load (Fig. 3, 19 & Fig. 6-7 & Paragraph [0102-103]).
In regards to claim 5. Bhutta discloses the match network of claim 4, wherein the controller (Fig. 3-5, 45 and 645) is configured to: tune the variable capacitance (Fig. 3-5, 31) based on an impedance value that is offset from the average impedance value (Average parameter value) (Fig. 6-7 & Paragraph [0124 & 0176 & 0177 & 0184]); switch the one or more solid-state capacitances (Fig. 3-7, 653 via 611) to a first switched configuration (array configuration capacitor switch positions via lookup table) to impedance match to the average impedance value (average parameter value) in conjunction with the variable capacitance (Fig. 3-7, 31 & Paragraph [0083 & 0103]); and switch the one or more solid-state capacitances (Fig. 3-7, 653 via 661) to a second switched configuration (array configuration capacitor switch positions via lookup table) to impedance match based on the detected impedance fluctuation of the plasma load (Fig. 1-7, 19 & Paragraph [0083 & 0102-103]).
In regards to claim 6. Bhutta discloses the match network of claim 1, wherein the controller (Fig. 3-7, 45/645) is configured to: monitor an impedance state of the plasma load (Fig. 5-7 & Paragraph [0089-90]); and in response to detecting an impedance change of the plasma load (Fig. 3-7, 19) from the first impedance state to the second impedance state (Match configuration via lookup table), switch the at least one solid-state capacitance (Fig. 3-7, 653 via 611 of 33) into or out of parallel arrangement with the variable capacitance (Fig. 3-7, 33) to impedance match to the second state of the plasma load (Fig. 5-7, 19 & Paragraph [0089-90]).
In regards to claim 7. Bhutta discloses the match network of claim 1, further comprising: a first array (Fig. 3-7, 651 of 653) including a first plurality of solid-state capacitances (Fig. 3-7, 653 of 33) and a first plurality of switches (Fig. 3-7, 661 of 33) corresponding with the first plurality of solid-state capacitances (Fig. 3-7, 653 of 33), wherein the first array (Fig. 3-7, 33) is in parallel with the variable capacitance (Fig. 3, 31) and is part of a shunt leg (Shunt leg) (Fig. 1-2, 5 & Paragraph [0058 & 0082-83]); and a second array (Fig. 3-7, 651 of 653 of 31) including a second plurality of solid-state capacitances (Fig. 3-7, 653 if 31) and a second plurality of switches (Fig. 3-7, 661 of 31) corresponding with the second plurality of solid-state capacitances (Fig. 3-7, 653 of 31), wherein the second array (Fig. 3-7, 31) is in parallel with a second variable capacitance (Fig. 3-7, 31) and is part of a series leg (series leg) (Fig. 1-2 & 5 & Paragraph [0058 & 0082-83]); wherein the controller (Fig. 3-7, 45 of 645) is configured to operate the first plurality of switches (Fig. 3-7, 661 of 33) and the second plurality of switches (Fig. 3-7, 661 of 31) to impedance match to the second state (Fig. 1-2, 5 & Paragraph [0061-71]).
In regards to claim 8. Bhutta discloses a method (Abstract) comprising:
a variable capacitance (Fig. 1-2, 31 & Paragraph [0058]);
Bhutta does not specify controlling a variable capacitance for impedance matching to a first impedance state of a plasma load; and switching one or more solid-state capacitances into or out of parallel arrangement with the variable capacitance for impedance matching to a second impedance state of the plasma load.
Bhutta discloses in Fig. 3-7 controlling (Fig. 3, 45) a variable capacitance (Fig. 3-7, 31) for impedance matching to a first impedance state of a plasma load (Fig. 3, 19); and switching one or more solid-state capacitances (Fig. 3, 33a and Fig. 5, 653) into or out of parallel arrangement with the variable capacitance (Fig. 3-7, 31) for impedance matching to a second impedance state (Paragraph [0082-83 & 0089 & 0102 & 0140]) of the plasma load (Fig. 3, 19).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention was made to modify Bhutta with controlling a variable capacitance for impedance matching to a first impedance state of a plasma load; and switching one or more solid-state capacitances into or out of parallel arrangement with the variable capacitance for impedance matching to a second impedance state of the plasma load for purpose of improvement in matching network tune speed and determine a parameter related to the matching network or the plasma chamber; based on the determined parameter, determine from the different positions of the VRE a new position for the VRE to reduce a reflected power at the RF input of the matching network; wherein the power control scheme is configured to be altered; and wherein, while the power control scheme is altered, the matching network alters the VRE to the new position as disclosed by Bhutta (Paragraph [0098 & 0009]).
In regards to claim 9. Bhutta discloses the method of claim 8, further comprising: providing power to the plasma load (Fig. 3, 19), the power including a first power pulse (Fig. 14-15, 333) and a second power pulse (Fig. 14-15, 335) that is different than the first power pulse (Fig. 14-15, 333); tuning the variable capacitance (Fig. 14-15, 31) for impedance matching to the first impedance state (match configurations via lookup table) based on the first power pulse (Fig. 14-15, 333) applied to the plasma load (Fig. 3, 19); and switching the one or more solid-state capacitances (Fig. 3-7, 653 of 33) for impedance matching to the second impedance state (Match configurations via lookup table) based on the second power pulse (Fig. 14-15, 335) applied to the plasma load (Fig. 3, 19 & Fig. 14-15, Paragraph [0181-183 & 0187 & 0189]).
In regards to claim 10. Bhutta discloses the method of claim 9, further comprising: determining a first switched configuration (Fig. 5, array of configuration of 661) of the one or more solid-state capacitances (Fig. 5, 653) to impedance match for the first power pulse (Fig. 14-15, 333 & Fig. 19 & Paragraph [0224-227]); determining a second switched configuration (Fig. 14-15, 661) of the one or more solid-state capacitances (Fig. 14-15 & 19 & Paragraph [0224-227]) to impedance match for the second power pulse (Fig. 14-15, 335 & 19 & Paragraph [0224-227]); and toggling between the first switched configuration (Fig. 5, array configuration of 661) and the second switched configuration (Fig. 5, array configuration of 661) for the first power pulse (Fig. 14-15, 333 & Fig. 19 & Paragraph [0224-227]) and the second power pulse (Fig. 14-15, 335 & 19 & Paragraph [0224-227]), respectively.
In regards to claim 11. Bhutta discloses the method of claim 8, further comprising: tuning the variable capacitance (Fig. 3-7, 31) for impedance matching to the first impedance state (match configurations via lookup table) based on an average impedance value (average parameter value) of the plasma load (Fig. 3, 19) over a period of time (Fig. 7, 14-15 & Paragraph [0089 & 0103 & 0184 & 0188]); detecting an impedance fluctuation of the plasma load (Fig. 3, 19) from the average impedance value (Fig. 6-7 & 14-15 & Paragraph [0055 & 0089 & 0093 & 0103 & 0184 & 0188]); and switching at least one solid-state capacitance (Fig. 3-7, 653) for impedance matching to the second impedance state (match configuration via lookup table) based on the detected impedance fluctuation of the plasma load (Fig. 3-7, 19) from the average impedance value (Average parameter value) (Fig. 6-7 & Paragraph [0102-103]).
In regards to claim 12. Bhutta discloses the method of claim 11, further comprising: tuning the variable capacitance (Fig. 3-7, 31) based on an impedance value that is offset from the average impedance value (Average parameter value) (Fig. 6-7 & Paragraph [0124 & 0176-177 & 0184]); switching the one or more solid-state capacitances (Fig. 5-7, 653) to a first switched configuration (array configuration capacitor switch positions via lookup table) to impedance match to the average impedance value (average parameter value) in conjunction with the variable capacitance (Fig. 3-7, 31); and switching the one or more solid-state capacitances (Fig. 3-7, 653) to a second switched configuration (array configuration capacitor switch positions via lookup table) to impedance match based on the detected impedance (Fig. 5-7 & Paragraph [0083 & 0102-103]) fluctuation of the plasma load (Fig. 3, 19).
In regards to claim 13. Bhutta discloses the method of claim 8, wherein: the variable capacitance is a variable vacuum capacitance (Fig. 3-7, 31 & Fig. 12 & Paragraph [0005 & 0163])
In regards to claim 14. Bhutta discloses a non-transitory processor-readable medium comprising instructions for execution by a processor (Fig. 1-2, 45) or for configuring a field programmable gate array (Paragraph [0042-44]), the instructions comprising instructions to:
Bhutta does not specify in Fig. 1-2, control a variable capacitance for impedance matching to a first impedance state of a plasma load; and switch one or more solid-state capacitances into or out of parallel arrangement with the variable capacitance for impedance matching to a second impedance state of the plasma load.
Bhutta discloses control a variable capacitance (Fig. 3, 31) for impedance matching to a first impedance state (array configuration capacitor switch positions via lookup table) of a plasma load (Fig. 3, 19 & Paragraph [0083 & 0089 & 0102 & 0140]); and switch one or more solid-state capacitances (Fig. 3-7, 653 of 33) into or out of parallel arrangement with the variable capacitance (Fig. 3-7, 31) for impedance matching to a second impedance state of the plasma load (Fig. 3, 19 & Paragraph [0089-90 & 0102 & 0140 & 0229]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention was made to modify Bhutta with control a variable capacitance for impedance matching to a first impedance state of a plasma load; and switch one or more solid-state capacitances into or out of parallel arrangement with the variable capacitance for impedance matching to a second impedance state of the plasma load for purpose of improvement in matching network tune speed and determine a parameter related to the matching network or the plasma chamber; based on the determined parameter, determine from the different positions of the VRE a new position for the VRE to reduce a reflected power at the RF input of the matching network; wherein the power control scheme is configured to be altered; and wherein, while the power control scheme is altered, the matching network alters the VRE to the new position as disclosed by Bhutta (Paragraph [0098 & 0009]).
In regards to claim 15. Bhutta discloses the non-transitory processor-readable medium of claim 14, wherein the instructions comprise instructions to: tune the variable capacitance for impedance matching to the first impedance state based on a first power pulse applied to the plasma load (Fig. 3-7, 31 and 19 & Fig. 14-15 & Paragraph [0181-183] & [0187-189]); and switch the one or more solid-state capacitances for impedance matching to the second impedance state based on a second power pulse applied to the plasma load that is different than the first power pulse (Fig. 3-7, 653 of 33 and 19 & Fig. 14-15, 333 and 335 & Paragraph [0181-183 & 0187-189]).
In regards to claim 16. Bhutta discloses the non-transitory processor-readable medium of claim 15, wherein the instructions comprise instructions to: determine a first switched configuration (Fig. 3-7, 661) of the one or more solid-state capacitances (Fig. 3-7, 653) to impedance match for the first power pulse (Fig. 14-15, 333 & Paragraph [0224-227]); determine a second switched configuration (Fig. 3-7, 661) of the one or more solid-state capacitances (Fig. 3-7, 653) to impedance match for the second power pulse (Fig. 14-15 & 19, 333 & Paragraph [0224-227]); and toggle between the first switched configuration and the second switched configuration for the first power pulse and the second power pulse, respectively (Fig. 3-7, 661 & Fig. 14-15, 333 and 335 & Paragraph [0224-227]).
In regards to claim 17. Bhutta discloses the non-transitory processor-readable medium of claim 14, wherein the instructions comprise instructions to: tune the variable capacitance for impedance matching to the first impedance state based on an average impedance value of the plasma load over a period of time (Fig. 3-7, 31 and 19 & Fig. 14-15 & Paragraph [0089 & 0103 & 0184 & 0188 & 0340]); detect an impedance fluctuation of the plasma load (Fig. 3-7, 19) from the average impedance value (average parameter value) (Fig. 6-7 & 14-15 & Paragraph [0055 & 0089 & 0093 & 0103 & 0184 & 0188); and switch at least one solid-state capacitance (Fig. 3-7, 653) for impedance matching to the second impedance state based on the detected impedance fluctuation of the plasma load from the average impedance value (Fig. 3-7, 19 & Paragraph [0102-103]).
In regards to claim 18. Bhutta discloses the non-transitory processor-readable medium of claim 17, the instructions comprise instructions to: tune the variable capacitance based on an impedance value that is offset from the average impedance value (Fig. 3-7, 31 & Paragraph [0124 & 0176-177 & 0184]); switch the one or more solid-state capacitances to a first switched configuration to impedance match to the average impedance value in conjunction with the variable capacitance (Fig. 3-7, 653 via 661 and 31 & Paragraph [0083 & 0103]); and switch the one or more solid-state capacitances (Fig. 3-7, 653 via 661) to a second switched configuration to impedance match based on the detected impedance fluctuation of the plasma load (Fig. 3-7, 19 & Paragraph [0083 & 0102 & 0103]).
In regards to claim 19. Bhutta discloses the non-transitory processor-readable medium of claim 14, wherein: the variable capacitance is a variable vacuum capacitance (Fig. 3-7, 31 &Fig. 12 & Paragraph [0005 & 0163]).
In regards to claim 20. Bhutta discloses the non-transitory processor-readable medium of claim 14, wherein the instructions comprise instructions to: control a first array (Fig. 3-7, 651 of 653 of 33) including a first plurality of solid-state capacitances (Fig. 3-7, 653 of 33) and a first plurality of switches (Fig. 3-7, 661 of 33) corresponding with the first plurality of solid-state capacitances (Fig. 3-7, 653 of 33), wherein the first array (Fig. 1-7, 33) is in parallel with the variable capacitance (Fig. 1-7, 31) and is part of a shunt leg of a match network (Fig. 1-2, 5 & Paragraph [0058 & 0082-83]); and control a second array (Fig. 1-7, 651 of 653 of 31) including a second plurality of solid-state capacitances (Fig. 1-7, 653 of 31) and a second plurality of switches (Fig. 1-7, 661 of 31) corresponding with the second plurality of solid-state capacitances (Fig. 1-7, 653 of 31),
wherein the second array (Fig. 1-7, 31) is in parallel with a second variable capacitance (Fig. 1-7, 31) and is part of a series leg of the match network (Fig. 1-2 & 5 & Paragraph [0058 & 0082-83]); wherein the control of the first array and the second array includes operating the first plurality of switches and the second plurality of switches to impedance match to the second state (Fig. 1-2 & 5 & Paragraph [0061-71]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WEI (VICTOR) CHAN whose telephone number is (571)272-5177. The examiner can normally be reached M-F 9:00am to 6:00pm.
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WEI (VICTOR) CHAN
Primary Examiner
Art Unit 2844
/WEI (VICTOR) Y CHAN/Primary Examiner, Art Unit 2844