DETAILED ACTION
1. This action is in response to the election filed on 10/24/25.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
3. Applicant's election with traverse of Species 2 in the reply filed on 10/24/25 is acknowledged. The traversal is on the ground(s) that “the scopes of the claims directed to Species 1 and 2 overlap with each other and belong to the same technical field, and thus the examination thereof does not incur significant extra burden to the Examiner.” This is found persuasive. Therefore, the restriction mailed on 08/27/25 has been withdrawn.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 10 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawasaki (US 20140070879).
Regarding claim 10: Kawasaki discloses an electronic device (i.e. figure 1A, 3A-3B, 4B), comprising:
a load circuit (i.e. 11) configured for performing a load function based on an output voltage (i.e. VDDMA) and a system clock signal (i.e. clk); and
a digital low-dropout regulator (DLDO) (i.e. 30) coupled to the load circuit (i.e. 11) and configured for regulating the output voltage (i.e. VDDMA) provided to the load circuit (i.e. 11) based on a reference clock signal (i.e. cka), to make the output voltage (i.e. VDDMA) approach a reference voltage (i.e. Vref), wherein the reference clock signal (i.e. cka) is triggered (i.e. function of PMU) when a level change in the system clock signal (i.e. clk) occurs, and a clock frequency of the reference clock signal is higher than a clock frequency of the system clock signal (i.e. function of PMU 12 that divided the clock signal clk to generate the operation clock and changes the clock clk. Therefore, a clock frequency of the reference clock signal cka is higher than a clock frequency of the system clock signal clk, ¶ 5).
Regarding claim 19: (i.e. figure 1A, 3A-3B, 4B) wherein the reference clock signal (i.e. cka) is asynchronous with the system clock signal (i.e. cka).
Regarding claim 20: Kawasaki discloses wherein the asynchronous clock generation circuit (i.e. 12) determines the clock frequency of the reference clock signal (i.e. see figure 3) based on a comparison completion signal (i.e. DVFS) (i.e. ¶ 19).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1-3, 6, 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kawasaki (US 20140070879) in view of Salem et al. (US 20180226981) and Lee et al. (US 20230288948).
Regarding claim 1: Kawasaki discloses (i.e. figure 1A, 3A-3B, 4B) a digital low-dropout regulator (DLDO) (i.e. 30) adapted for regulating an output voltage (i.e. VDDMA) provided to a load circuit (i.e. 11), comprising:
a voltage comparator circuit (i.e. 28) configured for comparing a reference voltage (i.e. Vref) with a voltage (i.e. MONA) to output a comparison result signal (i.e. output of 28);
a switch control circuit (i.e. 29) coupled to the voltage comparator circuit (i.e. 28) and configured for generating a switch control signal (i.e. output of 29) based on the comparison result signal (i.e. output of 28);
a power switch module (i.e. 21A-21C) configured to be controlled by the switch control signal (i.e. output of 29) to switch between an on state and an off state, thereby adjusting the output voltage (i.e. VDDMA); and
an asynchronous clock generation circuit (i.e. 12) coupled (i.e. electrically coupled) to the switch control circuit (i.e. 21A-21C) and the voltage comparator circuit (i.e. 28), and configured for generating a reference clock signal (i.e. cka) that is asynchronous with a system clock signal (i.e. clk), wherein the switch control circuit (i.e. 29) updates the output switch control signal (i.e. output of 29) based on the reference clock signal (i.e. cka), to make the output voltage (i.e. VDDMA) approach the reference voltage (i.e. Vref), wherein a clock frequency of the reference clock signal (i.e. cka) is higher than a clock frequency of the system clock signal (i.e. clk) (i.e. function of PMU 12 that divided the clock signal clk to generate the operation clock and changes the clock clk. Therefore, a clock frequency of the reference clock signal cka is higher than a clock frequency of the system clock signal clk, ¶ 5),
but does not specifically disclose a voltage comparator circuit configured for comparing a reference voltage with the output voltage to output a comparison result signal; wherein the system clock used in the load circuit.
Salem et al. disclose a voltage regulator (i.e. figure 2a) comprising a voltage comparator circuit (i.e. 16) configured for comparing a reference voltage (i.e. Vref) with the output voltage (i.e. Vout) to output a comparison result signal (i.e. from 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Kawasaki’s invention with the regulator as disclose by Salem et al. to stabilize the output voltage.
Lee et al. disclose a voltage regulator (i.e. figure 6) comprising wherein the system clock (i.e. CLK_DLDO) used in the load circuit (i.e. 200) (i.e. ¶ 63).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Kawasaki’s invention with the regulator as disclose by Lee et al. to minimizing the fluctuation of the output voltage.
Regarding claim 2: Kawasaki disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the asynchronous clock generation circuit triggers the generation of the reference clock signal in response to at least one of a rising edge and a falling edge of the system clock signal.
Lee et al. disclose a voltage regulator (i.e. figures 6-7) comprising the asynchronous clock generation circuit (i.e. 121) triggers the generation of the reference clock signal (i.e. CLK_COMP) in response to at least one of a rising edge and a falling edge of the system clock signal (i.e. CLK_DLDO) (i.e. figure 7: see clock signals).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Kawasaki and Salem et al.’s invention with the regulator as disclose by Lee et al. to minimizing the fluctuation of the output voltage.
Regarding claim 3: Kawasaki disclose the limitation of the claim(s) as discussed above, but does not specifically disclose when the system clock signal triggers the asynchronous clock generation circuit to generate the reference clock signal, the asynchronous clock generation circuit generates, within a triggering period, a pulse group as the reference clock signal.
Lee et al. disclose a voltage regulator (i.e. figures 6-7) comprising when the system clock signal triggers the asynchronous clock generation circuit (i.e. circuit of 200) to generate the reference clock signal (i.e. CLK_COMP), the asynchronous clock generation circuit (i.e. circuit of 200) generates, within a triggering period (i.e. period from t1-tb, tb-t2), a pulse group as the reference clock signal (i.e. CLK_COMP).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Kawasaki and Salem et al.’s invention with the regulator as disclose by Lee et al. to minimizing the fluctuation of the output voltage.
Regarding claim 6: Kawasaki disclose the limitation of the claim(s) as discussed above, but does not specifically disclose a length of the triggering period and a predetermined number of pulses are selected according to the asynchronous clock generation circuit.
Lee et al. disclose a voltage regulator (i.e. figures 6-7) comprising a length of the triggering period (i.e. length of the period from t1-tb, tb-t2) and a predetermined number of pulses (i.e. pulses of CLK_COMP) are selected according to the asynchronous clock generation circuit (i.e. circuit of 200).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Kawasaki and Salem et al.’s invention with the regulator as disclose by Lee et al. to minimizing the fluctuation of the output voltage.
Regarding claim 8: Kawasaki discloses (i.e. figure 1A, 3A-3B, 4B) wherein a number of bits of the switch control signal (i.e. output of 29) corresponds to a number of power switches (i.e. 21A-21C) comprised in the power switch module.
Regarding claim 9: Kawasaki discloses wherein the asynchronous clock generation circuit (i.e. 12) determines the clock frequency of the reference clock signal (i.e. see figure 3) based on a comparison completion signal (i.e. DVFS) (i.e. ¶ 19).
8. Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Kawasaki (US 20140070879) in view of Salem et al. (US 20180226981).
Regarding claim 11: Kawasaki discloses (i.e. figure 1A, 3A-3B, 4B) wherein the DLDO comprises: a voltage comparator circuit (i.e. 28), configured for comparing the reference voltage (i.e. Vref) with the voltage (i.e. MONA) to output a comparison result signal (i.e. output of 28);
a switch control circuit (i.e. 29), coupled to the voltage comparator circuit (i.e. 28) and configured for generating a switch control signal (i.e. output of 29) based on the comparison result signal (i.e. output of 28);
a power switch module (i.e. 21A-21C), configured to be controlled by the switch control signal (i.e. output of 29) to switch between an on state and an off state, thereby adjusting the output voltage (i.e. VDDMA); and
an asynchronous clock generation circuit (i.e. 12), coupled to the switch control circuit (i.e. 29) and the voltage comparator circuit (i.e. 28), and configured for generating the reference clock signal (i.e. cka) based on a level change in the system clock signal (i.e. clk),
but does not specifically disclose configured for comparing the reference voltage with the output voltage to output a comparison result signal.
Salem et al. disclose a voltage regulator (i.e. figure 2a) comprising configured for comparing the reference voltage (i.e. Vref) with the output voltage (i.e. Vout) to output a comparison result signal (i.e. from 16).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Kawasaki’s invention with the regulator as disclose by Salem et al. to stabilize the output voltage.
Regarding claim 12: Kawasaki discloses (i.e. figure 1A, 3A-3B, 4B) wherein the switch control circuit (i.e. 29) updates the output switch control signal (i.e. output of 29) based on the reference clock signal (i.e. cka).
Regarding claim 13: Kawasaki discloses (i.e. figure 1A, 3A-3B, 4B) a number of bits of the switch control signal (i.e. output of 29) corresponds to a number of power switches (i.e. 21A-21C) comprised in the power switch module.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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/Nguyen Tran/Primary Examiner, Art Unit 2838