Detail Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Status: Please all the replies and correspondence should be addressed to Examiner’s art unit 2629. Receipt is acknowledged of papers submitted on 12-29-2025 under amendments and request for reconsideration; which have been placed of record in the file. Claims 1-20 are pending.
Interview Summary
Examiner called Applicant’s representative on 02-10-2026. Examiner and Applicant’s representative discussed the independent claims in response to non-final office action mailed on 10-01-2025. Examiner pointed out paragraphs the prior art of Harris does teach applicant’s arguments. Applicant and Examiner discussed option and to move instant application forward. There was no mutual agreement was reached. Examiner mentioned to Applicant’s representative Examiner does have to issue an office action since there was no mutual agreement was reached as Examiner allocated time to respond to Applicant’s response of 12-29-2025 to non-final office action mailed on 10-01-2025 of is near expiring.
Further Examiner is available to discuss any issue to be resolve to move instant application forward and achieve compact prosecution at the phone number 571-272-7668.
Response to Amendment
The amendment filed 12-29-2025 does not introduce any new matter into the disclosure. The added material is supported by the original disclosure. Applicant has not amended any claims in response to non-final office action mailed on 10-01-2025.The response to non-final office action mailed on 10-01-2025 is mere request for reconsideration. Applicant has amended abstract per objection, therefore objection to abstract is withdrawn. Further Applicant has amended drawing to improve clarity of the figures.
Response to Arguments
Applicant's arguments filed 12-29-2025 have been fully considered but they are not persuasive.
Applicant argues Harris in view of Aaes et al. fails to disclose pilot or global common program instruction and main program instruction concurrently on different thread and track as well as determine completion of the processing of pilot or global common program instruction providing output that some of the main program processing depends from.
Examiner disagrees as prior art of Harris at figs. 5 & 6, paras. 191-203 discloses pilot or global common program instruction and main program instruction concurrently on different thread and track as well as determine completion of the processing of pilot or global common program instruction providing output that some of the main program processing depends from. Further paras. 59-64, disclosing the plural threads that start at different points in the shader program are in an embodiment executed in parallel, i.e. concurrently (at the same time). Further prior art of Harris at para. 108 discloses the execution of instructions at later points in the shader program is dependent upon the completion of earlier instructions in the shader program, then rather than waiting for a first thread to complete the shader program before beginning execution of the threads that are to start later in the shader program, the completion of particular instructions or sets of instructions in the shader program by (earlier) threads is tracked and monitored, and when a thread completes a relevant instruction or set of instructions in the shader program, then threads that are to begin the shader program at a later start point are released for execution. Please also see para.111. Please notice figs. 5-6, does main and common (or pilot program) runs on the same pass as some of the main program execution dependent on results of common program (or pilot program generated results. Further main program and global-common program runs on separate threads per Figs. 5-6. So the main program task and Global-common program are separately processed.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Harris Peter William (US-20170024848-A1) hereinafter referenced as Harris in view of Aaes Arne (US-20190340722-A1) hereinafter referenced as Aaes et al.
Regarding Claim 1, Harris discloses a method of operating a graphics processor ( paras. 24-26 disclosing graphics processing of shading stages described in details at paras.91-205) comprising a set of one or more processing cores (Please see abstract disclosing The sequence of instructions for a shader program 60 to be executed by a shader core of a graphics processor), the method comprising: when performing a processing pass including one or more initial processing jobs (please see abstract , para, 191, figs. 5-6, paras. 59-64, disclosing the plural threads that start at different points in the shader program are in an embodiment executed in parallel, i.e. concurrently), wherein an initial processing job executes a respective initial shader program that is to be executed in advance of a corresponding “main” shader program that will be executed for a separate “main” processing job within the same processing pass (please see abstract, Figs. 5-6, paras. 191-192, disclosing the shader program includes its main instruction sequence 63 that needs to be executed independently for each thread, for further detail paras. 191-205 disclosing figs. 5-6 detail operations of processing main job, wherein an initial processing job executes a respective initial shader program that is to be executed in advance of a corresponding “main” shader program that will be executed for a separate “main” processing job within the same processing pass), the “main” shader program thus having a dependency on the initial shader program for the initial processing job (please see abstract, paras. 191-192, for further detail please see figs. 5-6, paras. 191-205 disclosing figs. 5-6 operations, further disclosing the “main” shader program thus having a dependency on the initial shader program for the initial processing job), and wherein a “main” processing job comprises a respective set of one or more tasks to be processed for the “main” processing job, each task operable to execute a respective instance of the “main” shader program (abstract, para. 192, disclosing, the shader program includes its main instruction sequence 63 that needs to be executed independently for each thread (work item) tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores; and when a respective task to be processed as part of a “main” processing job is issued to a respective processing core for processing whilst the set of one or more processing cores is concurrently performing processing for at least one initial processing job (para. 191-192 disclosing operation of the main job with paras. 66-68, controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing) controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing, (paras. 191-205 disclosing processing of the main program paras. 66-68 combined with paras. 191-205 disclosing controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing, and paras 222-223, disclosing the execution of a job consisting of two work groups, each containing two work items (one work item mapping to one hardware thread) and the timing of execution of the threads for this job in a graphics processing unit that allows concurrent execution of dependent workloads, using a multithreaded execution unit ). Further prior art of Harris at figs. 5 & 6, paras. 191-203 discloses pilot or global common program instruction and main program instruction concurrently on different thread and track as well as determine completion of the processing of pilot or global common program instruction providing output that some of the main program processing depends from. Further paras. 59-64, disclosing the plural threads that start at different points in the shader program are in an embodiment executed in parallel, i.e. concurrently (at the same time). Further prior art of Harris at para. 108 discloses the execution of instructions at later points in the shader program is dependent upon the completion of earlier instructions in the shader program, then rather than waiting for a first thread to complete the shader program before beginning execution of the threads that are to start later in the shader program, the completion of particular instructions or sets of instructions in the shader program by (earlier) threads is tracked and monitored, and when a thread completes a relevant instruction or set of instructions in the shader program, then threads that are to begin the shader program at a later start point are released for execution. Please also see para.111. Please notice there are plurality of threads used to process plurality of workgroups.
However, prior art of Harris fails to recites a corresponding shader program that will be executed for a separate processing job within the same processing pass.
However, prior art of Aaes et al. recites a corresponding shader program that will be executed for a separate processing job within the same processing pass.
(at para. 82, a graphics processor, the processing to be performed is an interleaved rendering operation, i.e. in which plural rendering passes are each divided into many tasks, with the tasks then being interleaved across the (plural) rendering passes (e.g. to reduce the amount of cache that is needed to hold intermediate results).
Harris teaches the sequence of instructions for a shader program to be executed by a shader core of a graphics processor is divided into an initial set of instructions that perform "global" common expressions of the shader program, a set of instructions in the shader program that perform expressions that are common to a given work group within a set of work items that the shader program is to process, and a main instruction sequence that needs to be executed independently for each work item.
Harris teaches the shader program includes its main instruction sequence that needs to be executed independently for each thread.
Aaes et al. teaches a corresponding shader program that will be executed for a separate processing job within the same processing pass.
Harris does not teach a corresponding shader program that will be executed for a separate processing job within the same processing pass.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, Harris performs the same function as it does separately of
managing process operating, the shader program includes its main instruction sequence that needs to be executed independently for each thread
. Aaes et al. performs the same function as it does separately of a graphics processor processing shader task or job, the executing processing job within the same processing pass
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and resulted in modifying the invention of Harris to include a corresponding shader program that will be executed for a separate processing job within the same processing pass, as disclosed by Aaes et al. thereby reduce the amount of cache that is needed to hold intermediate results as Aaes et al. discusses at para. 82
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time the invention was made.
Regarding Claim 2, Harris discloses when issuing a task for a “main” processing job to a respective processing core for processing: determining, based on the tracking, whether any initial processing jobs on which the task has a potential dependency are currently being performed by the set of one or more processing cores; and when it is determined that at least one initial processing job on which the task has a potential dependency is currently being processed by the set of one or more processing cores at the point at which the task is issued to a respective processing core for processing: issuing the task to the respective processing core for processing concurrently with the at least one initial processing job that is being processed by the set of one or more processing cores; and performing at least some processing of the task up to but not including execution of the “main” shader program but waiting at least until the at least one initial processing job that was being performed by the set of one or more processing cores concurrently with the task for the “main” processing job has finished its processing before executing the “main” when it is determined that at least one initial processing shader program , (paras. 191-205 disclosing processing of the main program paras. 66-68 combined with paras. 191-205 disclosing controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing, and paras 222-223, disclosing the execution of a job consisting of two work groups, each containing two work items (one work item mapping to one hardware thread) and the timing of execution of the threads for this job in a graphics processing unit that allows concurrent execution of dependent workloads, using a multithreaded execution unit ).
Regarding Claim 3, Harris discloses when it is determined that at least one initial processing job on which the task has a potential dependency is currently being processed by the set of one or more processing cores at the point at which the task is issued to a respective processing core for processing, the method comprises indicating that execution of the “main” shader program for the task should be stalled pending the set of one or more processing cores completing processing the initial processing job or jobs on which the task has a potential dependency, the indicating causing the processing core to stall execution of the “main” shader program until a signal is received to indicate that the set of one or more processing cores has completed processing the initial processing job or jobs on which the task has a potential dependency , (paras. 191-205 disclosing processing of the main program paras. 66-68 combined with paras. 191-205 disclosing controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed (or stalled) in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing, and paras 222-223, disclosing the execution of a job consisting of two work groups, each containing two work items (one work item mapping to one hardware thread) and the timing of execution of the threads for this job in a graphics processing unit that allows concurrent execution of dependent workloads, using a multithreaded execution unit ).
Regarding Claim 4, Harris discloses the processing core subsequently receiving a signal to indicate that the set of one or more processing cores has completed processing the initial processing job or jobs on which the task has a potential dependency; and in response to such signal the processing core continuing processing the task including executing the “main” shader program (please see figs. 5-9 flow charts).
Regarding Claim 5, Harris discloses the tracking whether any initial processing jobs are currently being performed by the set of one or more processing cores comprises maintaining a reference counter indicative of how many initial processing jobs are currently being performed by the set of one or more processing cores.(please see paras 66-68, 102).
Please also see prior art of Aaes et al. paras. 106-110
Regarding Claim 6, Harris discloses the tracking whether any initial processing jobs are currently being performed by the set of one or more processing cores is performed by a task issuing circuit that controls issuing of tasks to the set of one or more processing cores (paras, 66-68, figs. 5-9).
Regarding Claim 7, Harris discloses the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores is performed on a per-processing pass basis, such that it is tracked for individual processing passes whether or not any initial processing jobs are currently being processed by the set of one or more processing cores for that processing pass, and wherein the controlling processing of the task for the “main” processing job comprises controlling processing of the task based on the tracking whether or not any initial processing jobs are currently being processed by the set of one or more processing cores for the same processing pass including the “main” processing job (please see paras. 66-68, 191-192, figs. 5-9).
Regarding Claim 8, Harris discloses the sequence of processing jobs includes a first processing pass including one or more initial processing jobs and one or more subsequent “main” processing jobs and a second processing pass including one or more initial processing jobs and one or more subsequent “main” processing jobs, and wherein a processing barrier is enforced between the first and second processing passes so that an initial processing job for the second processing pass is not issued for processing concurrently with any processing jobs for the first processing pass (please see abstract, paras. 66-68, 191-192, figs. 5-9).
Please also see prior art of Aaes et al. paras. 82, 86-87, 97-98.
Regarding Claim 9, Harris discloses a processing barrier is enforced in the sequence of processing jobs ahead of any initial processing job in the sequence of processing jobs such that initial processing jobs are not issued for processing concurrently with any earlier processing jobs in the sequence of processing jobs (please see figs. 5-9, paras. 189-192, 196-197, 201-204 disclosing basic processing of the jobs or workgroup in sequences obviously suggests and discloses initial processing jobs are not issued for processing concurrently with any earlier processing (or stalling) jobs in the sequence of processing jobs)
Regarding Claim 10, discloses the “main” processing jobs are fragment rendering jobs in which a fragment shader program is to be executed (please see abstract, paras. 189-192, 196-197, 201-204, disclosing the “main” processing jobs are fragment rendering jobs in which a fragment shader program is to be executed)
Regarding Claim 11, Harris discloses a graphics processor (please see fig. 1, item # 3) comprising: a set of one or more processing cores a task issuing circuit operable and configured to issue tasks to the set of one or more processing cores for processing (please see fig. 1-3); and a control circuit, wherein the control circuit (paras. 137, 178) is configured: method of operating a graphics processor ( paras. 24-26 disclosing graphics processing of shading stages described in details at paras.91-205) comprising a set of one or more processing cores (Please see abstract disclosing The sequence of instructions for a shader program 60 to be executed by a shader core of a graphics processor), the method comprising: when performing a processing pass including one or more initial processing jobs (please see abstract , para, 191, figs. 5-6, paras. 59-64, disclosing the plural threads that start at different points in the shader program are in an embodiment executed in parallel, i.e. concurrently), wherein an initial processing job executes a respective initial shader program that is to be executed in advance of a corresponding “main” shader program that will be executed for a separate “main” processing job within the same processing pass (please see abstract, Figs. 5-6, paras. 191-192, disclosing the shader program includes its main instruction sequence 63 that needs to be executed independently for each thread, for further detail paras. 191-205 disclosing figs. 5-6 detail operations of processing main job, wherein an initial processing job executes a respective initial shader program that is to be executed in advance of a corresponding “main” shader program that will be executed for a separate “main” processing job within the same processing pass), the “main” shader program thus having a dependency on the initial shader program for the initial processing job (please see abstract, paras. 191-192, for further detail please see figs. 5-6, paras. 191-205 disclosing figs. 5-6 operations, further disclosing the “main” shader program thus having a dependency on the initial shader program for the initial processing job), and wherein a “main” processing job comprises a respective set of one or more tasks to be processed for the “main” processing job, each task operable to execute a respective instance of the “main” shader program (abstract, para. 192, disclosing, the shader program includes its main instruction sequence 63 that needs to be executed independently for each thread (work item) tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores; and when a respective task to be processed as part of a “main” processing job is issued to a respective processing core for processing whilst the set of one or more processing cores is concurrently performing processing for at least one initial processing job (para. 191-192 disclosing operation of the main job with paras. 66-68, controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing) controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing, (paras. 191-205 disclosing processing of the main program paras. 66-68 combined with paras. 191-205 disclosing controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing, and paras 222-223, disclosing the execution of a job consisting of two work groups, each containing two work items (one work item mapping to one hardware thread) and the timing of execution of the threads for this job in a graphics processing unit that allows concurrent execution of dependent workloads, using a multithreaded execution unit ). Further prior art of Harris at figs. 5 & 6, paras. 191-203 discloses pilot or global common program instruction and main program instruction concurrently on different thread and track as well as determine completion of the processing of pilot or global common program instruction providing output that some of the main program processing depends from. Further paras. 59-64, disclosing the plural threads that start at different points in the shader program are in an embodiment executed in parallel, i.e. concurrently (at the same time). Further prior art of Harris at para. 108 discloses the execution of instructions at later points in the shader program is dependent upon the completion of earlier instructions in the shader program, then rather than waiting for a first thread to complete the shader program before beginning execution of the threads that are to start later in the shader program, the completion of particular instructions or sets of instructions in the shader program by (earlier) threads is tracked and monitored, and when a thread completes a relevant instruction or set of instructions in the shader program, then threads that are to begin the shader program at a later start point are released for execution. Please also see para.111. Please notice there are plurality of threads used to process plurality of workgroups.
However, prior art of Harris fails to recites a corresponding shader program that will be executed for a separate processing job within the same processing pass.
However, prior art of Aaes et al. recites a corresponding shader program that will be executed for a separate processing job within the same processing pass.
(at para. 82, a graphics processor, the processing to be performed is an interleaved rendering operation, i.e. in which plural rendering passes are each divided into many tasks, with the tasks then being interleaved across the (plural) rendering passes (e.g. to reduce the amount of cache that is needed to hold intermediate results).
Harris teaches the sequence of instructions for a shader program to be executed by a shader core of a graphics processor is divided into an initial set of instructions that perform "global" common expressions of the shader program, a set of instructions in the shader program that perform expressions that are common to a given work group within a set of work items that the shader program is to process, and a main instruction sequence that needs to be executed independently for each work item.
Harris teaches the shader program includes its main instruction sequence that needs to be executed independently for each thread.
Aaes et al. teaches a corresponding shader program that will be executed for a separate processing job within the same processing pass.
Harris does not teach a corresponding shader program that will be executed for a separate processing job within the same processing pass.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, Harris performs the same function as it does separately of
managing process operating, the shader program includes its main instruction sequence that needs to be executed independently for each thread
. Aaes et al. performs the same function as it does separately of a graphics processor processing shader task or job, the executing processing job within the same processing pass
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and resulted in modifying the invention of Harris to include a corresponding shader program that will be executed for a separate processing job within the same processing pass, as disclosed by Aaes et al. thereby reduce the amount of cache that is needed to hold intermediate results as Aaes et al. discusses at para. 82
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time the invention was made.
Regarding Claim 12, Harris discloses when issuing a task for a “main” processing job to a respective processing core for processing: determining, based on the tracking, whether any initial processing jobs on which the task has a potential dependency are currently being performed by the set of one or more processing cores; and when it is determined that at least one initial processing job on which the task has a potential dependency is currently being processed by the set of one or more processing cores at the point at which the task is issued to a respective processing core for processing: issuing the task to the respective processing core for processing concurrently with the at least one initial processing job that is being processed by the set of one or more processing cores; and performing at least some processing of the task up to but not including execution of the “main” shader program but waiting at least until the at least one initial processing job that was being performed by the set of one or more processing cores concurrently with the task for the “main” processing job has finished its processing before executing the “main” when it is determined that at least one initial processing shader program , (paras. 191-205 disclosing processing of the main program paras. 66-68 combined with paras. 191-205 disclosing controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing, and paras 222-223, disclosing the execution of a job consisting of two work groups, each containing two work items (one work item mapping to one hardware thread) and the timing of execution of the threads for this job in a graphics processing unit that allows concurrent execution of dependent workloads, using a multithreaded execution unit ).
Regarding Claim 13, Harris discloses when it is determined that at least one initial processing job on which the task has a potential dependency is currently being processed by the set of one or more processing cores at the point at which the task is issued to a respective processing core for processing, the method comprises indicating that execution of the “main” shader program for the task should be stalled pending the set of one or more processing cores completing processing the initial processing job or jobs on which the task has a potential dependency, the indicating causing the processing core to stall execution of the “main” shader program until a signal is received to indicate that the set of one or more processing cores has completed processing the initial processing job or jobs on which the task has a potential dependency , (paras. 191-205 disclosing processing of the main program paras. 66-68 combined with paras. 191-205 disclosing controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed (or stalled) in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing, and paras 222-223, disclosing the execution of a job consisting of two work groups, each containing two work items (one work item mapping to one hardware thread) and the timing of execution of the threads for this job in a graphics processing unit that allows concurrent execution of dependent workloads, using a multithreaded execution unit ).
Regarding Claim 14, Harris discloses the processing core subsequently receiving a signal to indicate that the set of one or more processing cores has completed processing the initial processing job or jobs on which the task has a potential dependency; and in response to such signal the processing core continuing processing the task including executing the “main” shader program (please see figs. 5-9 flow charts).
Regarding Claim 15, Harris discloses the tracking whether any initial processing jobs are currently being performed by the set of one or more processing cores comprises maintaining a reference counter indicative of how many initial processing jobs are currently being performed by the set of one or more processing cores.(please see paras 66-68, 102).
Please also see prior art of Aaes et al. paras. 106-110
Regarding Claim 16, Harris discloses the tracking whether any initial processing jobs are currently being performed by the set of one or more processing cores is performed by a task issuing circuit that controls issuing of tasks to the set of one or more processing cores (paras, 66-68, figs. 5-9).
Regarding Claim 17, Harris discloses the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores is performed on a per-processing pass basis, such that it is tracked for individual processing passes whether or not any initial processing jobs are currently being processed by the set of one or more processing cores for that processing pass, and wherein the controlling processing of the task for the “main” processing job comprises controlling processing of the task based on the tracking whether or not any initial processing jobs are currently being processed by the set of one or more processing cores for the same processing pass including the “main” processing job (please see paras. 66-68, 191-192, figs. 5-9).
Regarding Claim 18, Harris discloses the sequence of processing jobs includes a first processing pass including one or more initial processing jobs and one or more subsequent “main” processing jobs and a second processing pass including one or more initial processing jobs and one or more subsequent “main” processing jobs, and wherein a processing barrier is enforced between the first and second processing passes so that an initial processing job for the second processing pass is not issued for processing concurrently with any processing jobs for the first processing pass (please see abstract, paras. 66-68, 191-192, figs. 5-9).
Please also see prior art of Aaes et al. paras. 82, 86-87, 97-98.
Regarding Claim 19, Harris discloses a processing barrier is enforced in the sequence of processing jobs ahead of any initial processing job in the sequence of processing jobs such that initial processing jobs are not issued for processing concurrently with any earlier processing jobs in the sequence of processing jobs (please see figs. 5-9, paras. 189-192, 196-197, 201-204 disclosing basic processing of the jobs or workgroup in sequences obviously suggests and discloses initial processing jobs are not issued for processing concurrently with any earlier processing (or stalling) jobs in the sequence of processing jobs)
Regarding Claim 20, Harris discloses a non-transitory computer readable medium storing computer software code that when executed on one or more data processor will cause the data processor to perform a method of operating (para. 145) Harris discloses a graphics processor (please see fig. 1, item # 3) comprising: a set of one or more processing cores a task issuing circuit operable and configured to issue tasks to the set of one or more processing cores for processing (please see fig. 1-3); and a control circuit, wherein the control circuit (paras. 137, 178) is configured Harris discloses a method of operating a graphics processor ( paras. 24-26 disclosing graphics processing of shading stages described in details at paras.91-205) comprising a set of one or more processing cores (Please see abstract disclosing The sequence of instructions for a shader program 60 to be executed by a shader core of a graphics processor), the method comprising: when performing a processing pass including one or more initial processing jobs (please see abstract , para, 191, figs. 5-6, paras. 59-64, disclosing the plural threads that start at different points in the shader program are in an embodiment executed in parallel, i.e. concurrently), wherein an initial processing job executes a respective initial shader program that is to be executed in advance of a corresponding “main” shader program that will be executed for a separate “main” processing job within the same processing pass (please see abstract, Figs. 5-6, paras. 191-192, disclosing the shader program includes its main instruction sequence 63 that needs to be executed independently for each thread, for further detail paras. 191-205 disclosing figs. 5-6 detail operations of processing main job, wherein an initial processing job executes a respective initial shader program that is to be executed in advance of a corresponding “main” shader program that will be executed for a separate “main” processing job within the same processing pass), the “main” shader program thus having a dependency on the initial shader program for the initial processing job (please see abstract, paras. 191-192, for further detail please see figs. 5-6, paras. 191-205 disclosing figs. 5-6 operations, further disclosing the “main” shader program thus having a dependency on the initial shader program for the initial processing job), and wherein a “main” processing job comprises a respective set of one or more tasks to be processed for the “main” processing job, each task operable to execute a respective instance of the “main” shader program (abstract, para. 192, disclosing, the shader program includes its main instruction sequence 63 that needs to be executed independently for each thread (work item) tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores; and when a respective task to be processed as part of a “main” processing job is issued to a respective processing core for processing whilst the set of one or more processing cores is concurrently performing processing for at least one initial processing job (para. 191-192 disclosing operation of the main job with paras. 66-68, controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing) controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing, (paras. 191-205 disclosing processing of the main program paras. 66-68 combined with paras. 191-205 disclosing controlling processing of the task for the “main” processing job within the processing core based on the tracking whether any initial processing jobs are currently being processed by the set of one or more processing cores such that the “main” shader program for the “main” processing job is not executed in respect of the task at least until any initial processing jobs that were being concurrently processed with the task and on which the “main” shader program has a dependency have finished their processing, and paras 222-223, disclosing the execution of a job consisting of two work groups, each containing two work items (one work item mapping to one hardware thread) and the timing of execution of the threads for this job in a graphics processing unit that allows concurrent execution of dependent workloads, using a multithreaded execution unit ). Further prior art of Harris at figs. 5 & 6, paras. 191-203 discloses pilot or global common program instruction and main program instruction concurrently on different thread and track as well as determine completion of the processing of pilot or global common program instruction providing output that some of the main program processing depends from. Further paras. 59-64, disclosing the plural threads that start at different points in the shader program are in an embodiment executed in parallel, i.e. concurrently (at the same time). Further prior art of Harris at para. 108 discloses the execution of instructions at later points in the shader program is dependent upon the completion of earlier instructions in the shader program, then rather than waiting for a first thread to complete the shader program before beginning execution of the threads that are to start later in the shader program, the completion of particular instructions or sets of instructions in the shader program by (earlier) threads is tracked and monitored, and when a thread completes a relevant instruction or set of instructions in the shader program, then threads that are to begin the shader program at a later start point are released for execution. Please also see para.111. Please notice there are plurality of threads used to process plurality of workgroups.
However, prior art of Harris fails to recites a corresponding shader program that will be executed for a separate processing job within the same processing pass.
However, prior art of Aaes et al. recites a corresponding shader program that will be executed for a separate processing job within the same processing pass.
(at para. 82, a graphics processor, the processing to be performed is an interleaved rendering operation, i.e. in which plural rendering passes are each divided into many tasks, with the tasks then being interleaved across the (plural) rendering passes (e.g. to reduce the amount of cache that is needed to hold intermediate results).
Harris teaches the sequence of instructions for a shader program to be executed by a shader core of a graphics processor is divided into an initial set of instructions that perform "global" common expressions of the shader program, a set of instructions in the shader program that perform expressions that are common to a given work group within a set of work items that the shader program is to process, and a main instruction sequence that needs to be executed independently for each work item.
Harris teaches the shader program includes its main instruction sequence that needs to be executed independently for each thread.
Aaes et al. teaches a corresponding shader program that will be executed for a separate processing job within the same processing pass.
Harris does not teach a corresponding shader program that will be executed for a separate processing job within the same processing pass.
Hence the prior art includes each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
In combination, Harris performs the same function as it does separately of
managing process operating, the shader program includes its main instruction sequence that needs to be executed independently for each thread
. Aaes et al. performs the same function as it does separately of a graphics processor processing shader task or job, the executing processing job within the same processing pass
Therefore one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately.
The results of the combination would have been predictable and resulted in modifying the invention of Harris to include a corresponding shader program that will be executed for a separate processing job within the same processing pass, as disclosed by Aaes et al. thereby reduce the amount of cache that is needed to hold intermediate results as Aaes et al. discusses at para. 82
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time the invention was made.
Conclusion
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/Prabodh M Dharia/
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Art Unit 2629
02-24-2026