DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, page 2, filed 03/31/2026, with respect to Claims 24 and 27 have been fully considered and are persuasive. The objections for Claims 24 and 27 have been withdrawn.
Applicant's arguments filed 03/31/2026, with respect to Claims 22-29 have been fully considered but they are not persuasive.
Specifically, Applicant discusses how “Takahashi does not teach or suggest detecting that the phase error is monotonically increasing, much less responsive to detecting that the phase error is monotonically increasing: producing a phase error adjustment signal; and producing a loop filter adjustment signal.” Remarks 03/31/2026, p. 3.
Examiner respectfully disagrees. Takahashi teaches in Figure 5 PLL 100, which detects whether phase error is monotonically increasing using Phase Detector 101. The resulting output Phase Data/Clock may then be used through the Frequency Change Slop Detector 300, Jitter/Wander Detector 200, and PLL Feed Forward Real-time Actuator 400 to further adjust the phase error of Phase Detector 101 using Phase Detector Reset signal. Additionally, PLL Feed Forward Real-time Actuator 400 produces a loop filter adjustment signal using Amp1 Parameter, Amp2 Parameter, and Integrator Reset from 400.
Thus, all claimed limitations of Claims 22-29 are taught by the prior art presented.
Claims 1-8, 10-21, 30, and 31 remain allowed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 22-29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takahashi et al. (US 8,983,016 B2).
Regarding Claim 22, Takahashi et al. teaches in Figure 5 a method comprising:
receiving a phase error with respect to a reference clock and a feedback clock (101, which receives Reference Clock and Recovered Clock, as fed back through Divider 108) responsive to detecting that the phase error is monotonically increasing (based in part on the operation of the PLL 100 and the control system 200-500):
producing a phase error adjustment signal (using Phase Detector Reset from 400), and
producing a loop filter adjustment signal (using Amp1 Parameter, Amp2 Parameter, and Integrator Reset from 400).
Regarding Claim 23, Takahashi et al. further teaches wherein the phase error adjustment signal instructs a phase frequency detector to determine the phase error by limiting a measured phase error to a range (using at least Phase Threshold 303).
Regarding Claim 24, Takahashi et al. further teaches wherein the adjusted phase error is a lesser of the measured phase error minus a floor of the measured phase error or the measured phase error minus a ceiling of the measured phase error (based in part on the phase frequency reset signal).
Regarding Claim 25, Takahashi et al. further teaches wherein the loop filter adjustment signal instructs an integrator of a loop filter to a previous value of an output of the loop filter minus a function of the phase error (based in part on the Integrator Reset signal).
Regarding Claim 26, Takahashi et al. further teaches wherein the phase error adjustment signal instructs a phase frequency detector to set the phase error to a predetermined value (based in part on the phase frequency reset signal).
Regarding Claim 27, Takahashi et al. further teaches wherein the loop filter adjustment signal instructs an output of the integrator to a previous value of the clock control signal (based in part on the Integrator Reset signal).
Regarding Claim 28, Takahashi et al. further teaches the method further comprising:
selecting the response from among a set of responses (outputs of 400 are based in part on 200, 300, and 500); and
performing the response (using 400).
Regarding Claim 29, Takahashi et al. further teaches detecting that the phase error is monotonically increasing comprising detecting that the phase error exceeding a threshold for a given duration, the phase error monotonically increasing for a given duration, or detecting that the phase error monotonically increasing for a given duration then decreasing (based in part on what is detected by 101 and 302).
Allowable Subject Matter
Claims 1-8, 10-21, 30, and 31 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 1, the prior art does not disclose, teach or suggest a circuit comprising:
a controller coupled to the phase frequency detector and to the loop filter, the controller configurable to:
responsive to the behavior of the phase error:
instruct the phase frequency detector to adjust the phase error by selecting a first command, a second command, or a third command; and
instruct the loop filter to adjust the clock control signal;
in combination with all the other claimed limitations.
Claims 2-8, 10, and 30 are allowed for depending from Claim 1.
Regarding Claim 11, the circuit comprising:
a controller having a first input, a second input, a first output, and a second output, the first input coupled to the output of the multiplexer, the second input coupled to the output of the loop filter, the first output coupled to the second input of the loop filter, and the second output coupled to the fourth input of the multiplexer;
in combination with all the other claimed limitations.
Claims 12-21 and 31 are allowed for depending from Claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached on (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIANA J. CHENG/ Primary Examiner, Art Unit 2849