DETAILED ACTION
This action is responsive to the amendments filed August 4, 2026. Claims 1 – 20 are pending. Claims 1, 10, and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on August 4, 2026. This IDS has been considered.
Claim Rejections - 35 USC § 112 - Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4, 5, 13, and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 4 and 13 recite the limitation "determining whether the at least one first deck satisfies the criterion and the at least one second deck does not satisfy the criterion.". Claims 5 and 14 repeat “the criterion.” There is insufficient antecedent basis for this limitation in the claim.
Amended claim 1, from which claims 4 and 5 depend, and amended claim 10, from which claims 13 and 14 depend, no longer recite “a criterion.” Each recites “a first criterion pertaining to a functional deck” and “a second criterion pertaining to a defective deck.” It is unclear whether “the criterion” is the first criterion, the second criterion, or some other criterion. The metes and bounds of claims 4, 5, 13, and 14 are therefore indefinite.
For purposes of examination, “the criterion” in claims 4, 5, 13, and 14 will be treated as the criterion pertaining to a functionality of a deck described in the specification, under which a deck that satisfies the criterion is a functional deck and a deck that does not satisfy the criterion is a defective deck. Applicant is advised that this treatment is for purposes of applying prior art only and does not cure the indefiniteness. Correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-5, 8, 9, 10, 12-14, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Namala et al. (US 20220199189; “Namala” – of record), in view of Park et al. (US 20210027849; “Park” – of record).
Regarding independent claims 1, 10, and 17, Namala discloses a system / method / non-transitory computer-readable storage medium comprising:
a memory device (para. 2; “Embodiments pertain to memory devices”);
and a processing device (Fig. 1, processing circuitry 110),
operatively coupled with the memory device (Fig. 1 where it illustrates Memory Die Interface 125 which couples the processing circuitry and the memory die.), to perform operations comprising:
receiving a request to perform a program operation on a set of cells in a block of the memory device (para. 90; “At operation 930 the memory die may perform the requested operation on the second portion. …the memory die may read a value from the second portion, store a value in the second portion, erase the second portion, or the like.”),
the block comprising a plurality of decks (para 77; “Memory block 500 may include two distinct portions or “decks” 505 and 510.”);
determining whether at least one second deck of the plurality of decks is physically disposed below at least one first deck of the plurality of decks, wherein the at least one first deck satisfies a first criterion pertaining to a functional deck, and the at least one second deck of the plurality of decks satisfies a second criterion pertaining to a defective deck (Fig. 7. See also para 83; “FIG. 7 shows the top deck as defective and the bottom deck as free of defects, but in other examples the top deck may be free of defects (and thus salvageable), but the bottom deck may have one or more defects.”. See also para 82; “a salvageable deck in some examples is a deck whose memory cells do not have a defect from a first group of defect types, but is part of a block in which at least one other deck has a defect from a second group of defect types. In some examples, the second group of defect types may include a word line-to-word line short, a resistive word line, a slow to program cell, and defects where a raw bit error rate (RBER) metric exceeds a threshold.”);
and responsive to determining that the at least one second deck is physically disposed below the at least one first deck (Fig. 7 where it illustrates the second deck below the first deck),
Namala discloses the structure of the memory device and that the compensation is a word line bias. It is silent with respect to the first bitline voltage applied during a program verify phase and with that voltage being higher than a default program verify bitline voltage
However, Park teaches performing the program operation on the set of cells in the block using a first bitline voltage applied during a program verify phase, wherein the first bitline voltage is higher than a default program verify bitline voltage (Fig. 8 where it illustrates the bit line voltage applied during the program verify operation. See also para. 46; “when a corresponding page is programmed early, a bit line voltage may be set to be relatively high and when a corresponding page is programmed later, a bit line voltage may be set to be relatively low.” Further, see para 78; “A bit line voltage may be a voltage applied to the bit lines BL1 to BLm of the selected memory block BLK1 during a program verify operation.”).
Namala and Park are from the same field of endeavor as applicant's invention directed to operation of a non-volatile memory device. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply Park’s relatively high program-verify bit line voltage when Namala performs the store on a salvageable deck and the defective deck is the bottom deck. Namala already applies a compensation bias “so as to prevent the defects in the bad portion from interfering in the passing of electrical current to and from the memory cells associate to the word lines of the salvageable portion” (para. 89). Park changes the bit line voltage applied during the program verify operation for the same class of verify-current change and that the high voltage is used for that bottom-deck condition whereas the low voltage remains the default. The result is a predictable verify outcome using known techniques.
Regarding claims 3, 12, and 20, Namala and Park combined disclose the limitations of claims 1, 10, and 17 respectively.
As applied, Park further discloses wherein the processing device is to perform operations further comprising:
responsive to determining that the at least one second deck is not physically disposed below the at least one first deck, performing the program operation on the set of cells in the block using the default program verify bitline voltage (Fig. 8: BL Bias [V], see para. 46).
Regarding claims 4, and 13, notwithstanding the rejection for indefiniteness above, Namala and Park combined disclose the limitations of claims 1 and 10 respectively. Also as set forth above, the limitations are mapped as in claim 1/10. “The criterion” is examined as the functionality criterion: a deck that satisfies it is a functional deck, and a deck that does not satisfy it is a defective deck.
As applied, Namala further discloses wherein the processing device is to perform operations further comprising:
determining whether the at least one first deck satisfies the criterion and the at least one second deck does not satisfy the criterion (Fig. 9: 915. See also para 86; “At operation 915, the system may identify that a second portion of the block identified at operation 910 does not have a defect from a second identified list of defect types.”).
Regarding claims 5, and 14, Namala and Park combined disclose the limitations of claims 4 and 10 respectively.
As applied, Namala further discloses wherein the processing device is to perform operations further comprising:
responsive to determining that it is not that the at least one first deck satisfies the criterion and the at least one second deck does not satisfy the criterion (Fig. 8. See also para. 84; “FIG. 8 illustrates a diagram of a memory block 800 according to some examples of the present disclosure that show example defects in one portion, a top deck 810, that do not allow any other portion—in this case, the bottom deck 815, to be salvaged... Both decks in blocks with these defects will be marked as bad, even if the defect exists only in one deck.”),
Namala discloses the negative criterion determination but is silent with respect to the default program verify bitline voltage.
However, Park teaches performing the program operation on the set of cells in the block using the default program verify bitline voltage (Fig. 8: BL Bias [V], see para. 46).
Regarding claim 8, Namala and Park combined disclose the limitations of claim 1.
As applied, Namala further discloses wherein determining whether the at least one second deck is physically disposed below the at least one first deck further comprises:
determining whether the block is associated with an indicator according to a data structure (para. 87; “Responsive to identifying that there is a defect with a first portion at operation 910 and that a second portion does not have a defect at operation 915, the first portion may be marked defective by the memory device, and the second portion may be marked as salvageable. For example, the portions may be marked in a Logical-to-Physical (L2P) table in a controller, in the memory portion itself, in a table in a memory die that flags defective blocks and/or portions, a one-time programmable area, and the like.”)
Regarding claim 9, Namala and Park combined disclose the limitations of claim 1.
As applied, Namala further discloses wherein the processing device is to perform operations further comprising:
identifying the block based on an address of the set of cells (para. 24; “To address salvageable block portions when reading from or writing to the salvageable block portions, one or more additional address bits may be used to indicate the salvageable portion(s) of the block that are being addressed. For example, portions may comprise one of two decks in a block and the address bit may indicate an upper or lower deck.”).
Claims 6, 7, 15, 16, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Namala et al. (US 20220199189; “Namala” – of record), in view of Park et al. (US 20210027849; “Park” – of record) and further in view of Mokhlesi et al. (US 9911488; “Mokhlesi” – of record).
Regarding claims 6, 15, and 18, Namala and Park combined disclose the limitations of claims 1, 10, and 17 respectively.
As applied, Park further discloses wherein the first bitline voltage (Fig. 8: BL Bias [V]), but does not teach the “…bitline voltage is determined through a characterization measurement on the set of cells associated with the block”.
However, Mokhlesi teaches the first bitline voltage is determined through a characterization measurement (Fig. 11: showing multiple measured characterizations) on the set of cells (Note, Fig. 25, shows sets or groups of cells) associated with the block (Fig. 1A: BLK).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory device system of Namala in view of Park with Mokhlesi’s example of characterization measurement of the memory cells for the purpose of properly storing data in the memory.
Furthermore, the best representation of the applicant’s limitation is shown in figure 11.
Regarding claims 7, 16, and 19, Namala and Park combined disclose the limitations of claims 1, 10, and 17 respectively.
As applied, Park further discloses wherein the first bitline voltage (Fig. 8: BL Bias [V]), but does not disclose “the bitline voltage is determined according to a preset table, wherein the preset table comprises a plurality of records, wherein each record of the plurality of records comprises a value of the first bitline voltage corresponding to at least one of: a cell type, a level, or a numbered wordline”.
However, Mokhlesi teaches the first bitline voltage is determined according to a preset table (Fig. 11), wherein the preset table comprises a plurality of records (Fig. 11, showing a plurality of records), wherein each record of the plurality of records (Fig. 11, showing a plurality of records) comprises a value of the first bitline voltage (Fig. 11, shows the bit line voltage in the table) corresponding to at least one of:
a cell type, a level, or a numbered wordline (Fig. 11, shows the bitline voltages corresponding to the data states shown in figure 8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the memory device system of Namala in view of Park with Mokhlesi’s characterization measurement table for the purpose of properly storing data in the memory.
Claim 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Namala et al. (US 20220199189; “Namala” – of record), in view of Park et al. (US 20210027849; “Park” – of record), and further in view of Fastow et al. (US 20190043591; "Fastow").
Regarding claims 2 and 11, Namala and Park disclose the limitations of claims 1 and 10, respectively.
Namala in view of Park is silent to the specific provision of “performing a read operation on the set of cells in the block using a default read bitline voltage.”
However, Fastow teaches performing a read operation on the set of cells in the block using a default read bitline voltage (Fig. 8. See also para. 66; "FIG. 8 illustrates a flow and timing for a deck read and verify operation in accordance with various embodiments. It is here noted that, in embodiments, a block by deck read/verify operation may use the same flow and timing as used in a standard read/verify operation).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the program operation on the memory device of Namala in view of Park (with its PV bitline voltage adjustment) by performing the subsequent read using the standard/default read bitline voltage as taught by Fastow. Doing so would maintain compatibility with existing read schemes while avoiding complicating read-level optimization in multi-deck arrays where some decks may be erased.
Response to Arguments
Applicant's arguments filed have been fully considered.
The assertion on pg. 6 of Remarks that the obviousness rejection of claims 1, 3–5, 9, 10, 12–14, 17, and 20 under 35 U.S.C. 102(a)(1) as anticipated by Park is improper is persuasive as to that ground. Amended claims 1, 10, and 17 require a first criterion pertaining to a functional deck and a second criterion pertaining to a defective deck, and a determination that the deck satisfying the defective-deck criterion is physically disposed below the deck satisfying the functional-deck criterion. Park sets the program-verify bit line voltage according to whether a page is programmed early or late. Park (para. 46). An early or late program order is not a functional-deck criterion or a defective-deck criterion, and Park does not determine the relative physical position of a defective deck and a functional deck. The anticipation rejection is withdrawn.
The argument is not persuasive as to patentability. The same amendment necessitates the new rejection of claims 1, 10, and 17 under 35 U.S.C. 103 as unpatentable over Namala in view of Park, as set forth above. Namala discloses a salvageable deck free of the listed defects and another deck that has those defects, including the example in which the top deck is free of defects and the bottom deck has one or more defects (Namala para. 82, and 83). Park supplies the program-verify bit line voltage that is relatively high for an early page and relatively low for a later page. (Park para. 46, and 78).
Applicant’s arguments as to claims 3–5, 9, 12–14, and 20 are only that those claims depend from an independent claim that Park does not anticipate. No separate argument is made about the limitations those claims add. Those claims are rejected with the independent claims under the new ground.
The rejections of claims 6, 7, 15, 16, 18, and 19 over Park in view of Mokhlesi, of claim 8 over Park in view of Lee, and of claims 2 and 11 over Park in view of Fastow are withdrawn with the Park base. Applicant’s argument as to each of those rejections is only that the secondary reference does not cure Park. No separate argument is made about the characterization measurement, the preset table, the indicator, or the default read bitline voltage. Those claims are rejected under the new ground set forth above.
The amendment also introduces the indefiniteness of claims 4, 5, 13, and 14. Those claims still recite “the criterion.” Amended claims 1 and 10 recite a first criterion and a second criterion. That rejection is new and is set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
