The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This communication is responsive to Amendment filed 07/29/2026.
Claims 1-16, 18-19, and 21-22 have been examined.
Response to Amendment
In the instant amendment, claims 1, 4, 7-8, 13-14, 16 and 19 have been amended. Claims 21-22 are newly added.
The 35 USC §101 rejection over claims 1-16, 18-19, and 21-22 is withdrawn in view of Applicant’s amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0401444 to Hirota et al. (hereafter “Hirota”) in further view of US 2011/0041006 to Fowler and US 2012/0016432 to Westendorp et al. (hereafter “Westendorp”).
As per claim 1, Hirota discloses A device comprising:
processing elements configured in hardware using circuitry for executing a plurality of tasks (FIG. 1; paragraphs 0023 and 0055-0056: “the software application 126 includes, without limitation, a task graph 128. The task graph 128 specifies a workload via a graph (e.g., a directed graph) that is to be executed by at least one of the PPUs. Each node in the task graph is a task, and each edge in the task graph specifies a relationship between a producer task and a consumer task that is dependent on the producer task. A task is a set of program instructions that may be loaded into any type of memory of cache.”); and
a command processor configured in hardware using circuitry to:
schedule execution of the plurality of tasks by the processing elements (FIG. 1; paragraphs 0023 and 0055-0056: “The task management unit 234 receives tasks from the host interface unit 232, the work distribution unit 236, and/or the SMs 310 and schedules the tasks for execution by the SMs 310”), the plurality of tasks specified by a plurality of nodes in a task graph (FIG. 1; paragraphs 0023 and 0055-0056: “The task graph 128 specifies a workload as a directed graph. The nodes of the graph specify tasks, and the edges between the nodes specify dependency relationships between “producer tasks” and “consumer tasks.” Each dependency relationship may be a data dependency and/or an execution dependency (i.e., the producer task “happens before” the consumer task”);
track execution of the plurality of tasks using a counter (FIG. 4; paragraphs 0059, 0062 and 0067-0069: “Each of the task descriptors 430 is a data record that describes a different task that is to be performed by one or more threads executing on the SMs 310. Each of the task descriptors 430 includes, without limitation, a task configuration 450, consumer task descriptor pointers 470(1)-470(2), consumer flags 460(1)-460(2), a dependency count 442, a current count 444, and a self-reset flag 426.” [Wingdings font/0xE0]dependency count and current count), wherein a value of the counter is set based on a number of data dependencies identified for the plurality of tasks from the task graph (FIG. 4; paragraphs 0059, 0062 and 0067-0069: “The dependency count 442 specifies the number of dependencies that the task associated with the task descriptor 430 has on producer tasks. The dependency count 442 for a join task is therefore at least two. By contrast, if the dependency count 422 for a task is one, then the task is dependent upon one other task. The current count 444 specifies the number of dependencies of the task that have not yet been met. The self-reset flag 446 triggers the dependency/prefetch unit 410 to automatically copy the dependency count 442 to the current count 444 when the task-related activities for the task have completed” [Wingdings font/0xE0] both dependency count and current count are based on the number of dependencies that the task associated with the task descriptor has on producer task).
Hirota does not explicitly disclose initiate, based on the counter, a data transfer of aggregated data to a respective processing element of the processing elements, the aggregated data generated from the plurality of tasks.
Flower further discloses initiate, based on the counter (paragraph 0053: “incrementing the counter when a new processing thread is initiated for the transaction at the processing element; and decrementing the counter when a processing thread for the transaction completes; wherein processing result information collected for a plurality of threads associated with the transaction is preferably transmitted to the transaction manager when the counter is decremented to a value (e.g. zero) indicating that no threads remain executing for the transaction.”), a data transfer of aggregated data (paragraph 0053: “storing processing result information relating to processing performed in response to multiple received messages at the processing element, and transmitting the stored processing result information to the transaction manager as a group and/or in a single message.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Fowler into Hirota’s teaching because it would provide for the purpose of The multiple messages (and associated processing) preferably relate to the same distributed transaction. Thus, processing results for a particular transaction resulting from multiple calls to the processing element as part of that transaction may be grouped (Fowler, paragraph 0053).
Westendorp further disclose a data transfer of aggregated data to a respective processing element of the processing elements (FIGs. 7 and 10; paragraphs 0131-0132 and 0134: “Clinician device 250-1, which is associated with clinic 254-1, may send requests to data retrieval module 268 to retrieve both aggregate data 284 and clinic specific data 288-1” [Wingdings font/0xE0] sending a aggregated data to device 250-1 of a plural device 250-1 to 250-N), the aggregated data generated from the plurality of tasks (FIGs. 1, 7 and 10; paragraphs 0013-0014, 0033 and 0134: aggregated data collected from multiple IMD devices performing different tasks).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Westendorp into Hirota’s teaching and Flower’s teaching because it would provide for the purpose of the remote device may present results of its analysis of data from IMDs associated with a particular clinician or clinic in conjunction with results of its analysis of data from a broader subset of IMDs or from all IMDs (Westendorp, paragraph 0009).
As per claim 2, Hirota discloses wherein the plurality of nodes in the task graph are coupled using a plurality of edges that indicate the data dependencies between respective nodes of the plurality of nodes (paragraph 0023: “a task graph 128. The task graph 128 specifies a workload via a graph (e.g., a directed graph) that is to be executed by at least one of the PPUs. Each node in the task graph is a task, and each edge in the task graph specifies a relationship between a producer task and a consumer task that is dependent on the producer task. A task is a set of program instructions that may be loaded into any type of memory of cache. A consumer task may have an execution and/or data dependency on a related producer task. A task that is dependent on multiple producer tasks is referred to as a “join task,” while a task that has multiple, dependent consumer tasks is referred to as a “fork task.”).
As per claim 3, Hirota does not explicitly disclose wherein the command processor is configured to initiate the data transfer responsive to detecting that the counter indicates a respective task of the plurality of tasks does not include a further data dependency.
Fowler further discloses wherein the command processor is configured to initiate the data transfer responsive to detecting that the counter indicates a respective task of the plurality of tasks does not include a further data dependency (paragraph 0053: “decrementing the counter when a processing thread for the transaction completes; wherein processing result information collected for a plurality of threads associated with the transaction is preferably transmitted to the transaction manager when the counter is decremented to a value (e.g. zero) indicating that no threads remain executing for the transaction.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Fowler into Hirota’s teaching because it would provide for the purpose of The multiple messages (and associated processing) preferably relate to the same distributed transaction. Thus, processing results for a particular transaction resulting from multiple calls to the processing element as part of that transaction may be grouped (Fowler, paragraph 0053).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Hirota in view of Fowler and Westendorp, as applied to claim 1, and further in view of US 2022/0245009 to Vasiljevic et al. (hereafter “Vasiljevic”)
As per claim 4, Hirota does not explicitly disclose a data transfer aggregation buffer, associated with a respective processing element of the processing elements, configured to store the aggregated data.
Vasiljevic further discloses a data transfer aggregation buffer, associated with a respective processing element of the processing elements, configured to store the aggregated data (FIGs. 2 and 5; paragraphs 0052, 0054, 0059, 0061 and 0068: buffers/streams to store a combined data (aggregated data)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Vasiljevic into Hirota’s teaching, Fowler’s teaching, and Westendorp’s teaching because it would provide for the purpose of utilizing a network overlay layer and network overlay graph to efficiently execute an application data flow graph (Vasiljevic, paragraph 0007).
As per claim 5, Hirota discloses a plurality of values that include data from respective tasks of the plurality of tasks (FIGs. 6; paragraphs 0023, 0033, and 0062-0033); and
a plurality of indices that correspond to the plurality of tasks (paragraph 0033).
Hirota does not explicitly disclose wherein the data transfer aggregation buffer is configured to maintain the aggregated.
Vasiljevic further discloses wherein the data transfer aggregation buffer is configured to maintain the aggregated (FIGs. 2 and 5; paragraphs 0052, 0054, 0059, 0061 and 0068: buffers/streams to store a combined data (aggregated data)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Vasiljevic into Hirota’s teaching and Fowler’s teaching because it would provide for the purpose of utilizing a network overlay layer and network overlay graph to efficiently execute an application data flow graph (Vasiljevic, paragraph 0007).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hirota in view of Fowler, Westendorp, and Vasiljevic, as applied to claim 4, and further in view of US 2006/0150010 to Stiffer et al. (hereafter “Stiffer”)
As per claim 6, Hirota does not explicitly disclose wherein the command processor is configured to perform a runtime check to detect overflow of the data transfer aggregation buffer.
Basiljevic further discloses the data transfer aggregation buffer (FIGs. 2 and 5; paragraphs 0052, 0054, 0059, 0061 and 0068: buffers/streams to store a combined data (aggregated data)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Vasiljevic into Hirota’s teaching, Fowler’s teaching, and Westendorp’s teaching because it would provide for the purpose of utilizing a network overlay layer and network overlay graph to efficiently execute an application data flow graph (Vasiljevic, paragraph 0007).
Stiffer further discloses wherein the command processor is configured to perform a runtime check to detect overflow of the data transfer (paragraph 0053)
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Stiffer into Hirota’s teaching, Fowler’s teaching, Westendorp’s teaching and Vasiljevic’s teaching because it would provide for the purpose of preventing a buffer overflow in the I/O device (Stiffer, paragraph 0053).
Claim 8, 10 and 21 rejected under 35 U.S.C. 103 as being unpatentable over US 2002/0124012 to Liem in view of Vasiljevic.
As per claim 8, Liem discloses a system comprising:
a processor configured in hardware using circuitry to perform one or more operations (FIG. 1; paragraph 0037);
and a memory configured in hardware to maintain a compiler (FIG. 1), the compiler including instructions that are executable by the processor to perform the one or more operations (FIG. 1 and 4; paragraphs 0012-0013, 0018, and 0043-0044) to insert a node within a task graph that includes a plurality of computation nodes (FIGs. 1-5; paragraphs 0044 and 0049: “Some nodes are task nodes 152' that represent tasks.”).
Liem discloses insert a node within a task graph that includes a plurality of computation nodes (FIGs. 1-5; paragraphs 0044 and 0049: “Some nodes are task nodes 152' that represent tasks.”), however, Liem does not explicitly disclose the node is a transfer node; the data transfer node inserted within the task graph as a node of the task graph alongside the plurality of computation nodes, and the data transfer node configured to cause a data transfer operation using data aggregated from a plurality of tasks associated with the plurality of computation nodes.
Vasiljevic further discloses the node is a transfer node (FIG. 2; paragraphs 0030-0033: “overlay graph 203 includes intermediate nodes that guide the data flow, that are neither present in application data flow graph 202 nor represented by variables or operands (or otherwise described) in application code 201. The intermediate nodes in overlay graph 203 can be assigned to computational nodes in the network of computational nodes” [Wingdings font/0xE0] adding an intermediate node 230 which guide the data flow (a transfer node as claimed));
the data transfer node inserted within the task graph as a node of the task graph alongside the plurality of computation nodes (FIG. 2; paragraphs 0030-0033: “The intermediate nodes in overlay graph 203 can be assigned to computational nodes in the network of computational nodes.” [Wingdings font/0xE0] the intermediate nodes inserted within the graph alongside with computational nodes (a task graph as claimed)), and
the data transfer node configured to cause a data transfer operation using data aggregated from a plurality of tasks associated with the plurality of computation nodes (FIG. 2; paragraphs 0030-0033: “In the overlay graph, the intermediate nodes can direct the data flow by, for example, grouping requests and then multicasting the combined data to other nodes.” [Wingdings font/0xE0] node 230 combining data from A1-A3 [Wingdings font/0xE0] transferring combined data to B1-B3 in the overlay graph 203).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Vasiljevic into Liem’s teaching because it would provide for the purpose of overlay graph can be compiled to facilitate the execution of the instructions in the application code represent the data that is ultimately being produced by the computation layer of the network or provided to the graph from the computation layer (Vasiljevic, paragraph 0030).
As per claim 10, Liem discloses insert a node within a task graph that includes a plurality of computation nodes (FIGs. 1-5; paragraphs 0044 and 0049: “Some nodes are task nodes 152' that represent tasks.”), however, Liem does not explicitly disclose the node is a transfer node; and to insert the data transfer node within the task graph (FIG. 2; paragraphs 0030-0033) based a cost associated with performing multiple data transfer operations to transfer the data.
Vasiljevic discloses the node is a transfer node (FIG. 2; paragraphs 0030-0033: “overlay graph 203 includes intermediate nodes that guide the data flow, that are neither present in application data flow graph 202 nor represented by variables or operands (or otherwise described) in application code 201. The intermediate nodes in overlay graph 203 can be assigned to computational nodes in the network of computational nodes” [Wingdings font/0xE0] adding an intermediate node 230 which guide the data flow (a transfer node as claimed)); and
to insert the data transfer node within the task graph (FIG. 2; paragraphs 0030-0033) based a cost associated with performing multiple data transfer operations to transfer the data (FIGs. 8A-8B; paragraphs 0029, 0060 and 0068: “In the example of FIGS. 8A and 8B, by implementing double buffering, higher performance levels can be achieved since series execution in the intermediary core can be optimized by simultaneous execution of receive and send operations. The double buffering approach is advantageous in that it allows the system to increase consumption of data by the destination nodes of the overlay graph and maximize the overlap of computation and data transfers through the application data flow graph.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Vasiljevic into Liem’s teaching because it would provide for the purpose of overlay graph can be compiled to facilitate the execution of the instructions in the application code represent the data that is ultimately being produced by the computation layer of the network or provided to the graph from the computation layer (Vasiljevic, paragraph 0030).
As per claim 21, Liem discloses wherein the plurality of computation nodes define the plurality of tasks to be performed by respective processing elements configured in hardware (FIG. 5; paragraphs 0048-0049).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Liem and Vasiljevic, as applied to claim 8, and further in view of US 2004/0139413 to Dehon et al. (hereafter “Dehon”)
As per claim 9, Liem discloses wherein the compiler is configured to insert the node within the task graph (FIGs. 1-5; paragraphs 0044 and 0049: “Some nodes are task nodes 152' that represent tasks.”).
Liem discloses insert a node within a task graph that includes a plurality of computation nodes (FIGs. 1-5; paragraphs 0044 and 0049: “Some nodes are task nodes 152' that represent tasks.”), however, Liem does not explicitly disclose the node is a transfer node; and configured to insert the data transfer node within the task graph based a cost associated with an amount of time to perform data aggregation.
Vasilijevic discloses the node is a transfer node (FIG. 2; paragraphs 0030-0033: “overlay graph 203 includes intermediate nodes that guide the data flow, that are neither present in application data flow graph 202 nor represented by variables or operands (or otherwise described) in application code 201. The intermediate nodes in overlay graph 203 can be assigned to computational nodes in the network of computational nodes” [Wingdings font/0xE0] adding an intermediate node 230 which guide the data flow (a transfer node as claimed)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Vasiljevic into Liem’s teaching because it would provide for the purpose of overlay graph can be compiled to facilitate the execution of the instructions in the application code represent the data that is ultimately being produced by the computation layer of the network or provided to the graph from the computation layer (Vasiljevic, paragraph 0030).
Dehon further discloses to insert the data transfer node within the task graph based a cost associated with an amount of time to perform data aggregation (FIG. 8; paragraph 0088: “provide for the addition of nodes between the adders having a longer distance between them, such as between adders 53 and 54 (one additional node) or between the control box 51 and adder 52 (three additional nodes), to allow transmission of aggregate information between adders/nodes in a single clock cycle.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Dehon into Liem’s teaching, and Vasiljevic’s teaching because it would provide for the purpose of each processing unit is able to be paired with one of the one or more processing unit to reach a determination on whether to exchange associations with the respective elements between the paired processing units, the determination being in part based on randomness and in part based on a cost function (Dehon, paragraph 0015).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Liem and Vasiljevic, as applied to claim 8, and further in view of US 2017/0041216 to Fu.
As per claim 11, Liem does not explicitly disclose insert the data transfer node within the task graph based a route within the task graph; and select the route from a plurality of routes within the task graph.
Vasiljevic discloses select the route from a plurality of routes within the task graph (paragraphs 0031 and 0039).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Vasiljevic into Liem’s teaching because it would provide for the purpose of overlay graph can be compiled to facilitate the execution of the instructions in the application code represent the data that is ultimately being produced by the computation layer of the network or provided to the graph from the computation layer (Vasiljevic, paragraph 0030).
Fu further discloses insert the data transfer node within the task graph based a route within the task graph (paragraphs 0018-0019 and 0066).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Fu into Liem’s teaching and Vasiljevic’s teaching because it would provide for the purpose of determining an intermediate routing node, including determining at least one intermediate routing node that is used to transfer to-be-transmitted data between the two routing nodes when there is a fault in a communication path between two routing nodes, adding a channel dependency relationship between a to-be-verified intermediate routing node and the two routing nodes to a channel dependency graph of a routing network in which this fault has not occurred in order to enable the channel dependency graph to become an updated channel dependency graph (Fu, paragraph 0008).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Vasiljevic and further in view of Hirota.
As per claim 12, Liem does not explicitly disclose wherein the task graph is configured to specify execution of the plurality of tasks by a plurality of processing elements configured in hardware using circuitry for executing the plurality of tasks.
Hirota further discloses wherein the task graph is configured to specify execution of the plurality of tasks by a plurality of processing elements configured in hardware using circuitry for executing the plurality of tasks (paragraph 0023).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Hirota into Liem’s teaching Vasiljevic’s teaching because it would provide for the purpose of automatically re-initializing a dependency tracking without any software intervention can reduce the overall time required to execute the workload (Hirota, paragraph 0006).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Liem, Vasiljevic and Hirota, as applied to claim 12, and further in view of US 2019/0050355 to Becker et al. (hereafter “Becker”)
As per claim 13, Liem does not explicitly disclose wherein a command processor associated with the plurality of processing elements is configured to interpret the data transfer node to generate: a first data packet configured to initiate a direct memory access operation on a first processing element of the plurality of processing elements that is to transmit the data; and a second data packet configured to complete the direct memory access operation on a second processing element of the plurality of processing elements that is to receive the data.
Becker further discloses wherein a command processor associated with the plurality of processing elements is configured to interpret the data transfer node to generate:
a first data packet configured to initiate a direct memory access operation on a first said processing element of the plurality of processing elements that is to transmit the data (paragraphs 0020, 0030 and 0070: trigger signal); and
a second data packet configured to complete the direct memory access operation on a second said processing element of the plurality of processing elements that is to receive the data (ack/interrupt signal).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Becker into Liem’s teaching, Vasiljevic’s teaching and Hirota’s teaching because it would provide for the purpose of a direct memory access control unit for a processing unit that includes a working memory, the direct memory access control unit including a terminal for connecting the direct memory access control unit to a bus system that connects the processing unit to the working memory (Becker, paragraph 0005).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hirota and further in view of US 2009/0089544 to Liu
As per claim 14, Hirota discloses A device comprising:
processing elements configured in hardware using circuitry for executing a plurality of tasks (FIG. 1; paragraphs 0023 and 0055-0056: “the software application 126 includes, without limitation, a task graph 128. The task graph 128 specifies a workload via a graph (e.g., a directed graph) that is to be executed by at least one of the PPUs. Each node in the task graph is a task, and each edge in the task graph specifies a relationship between a producer task and a consumer task that is dependent on the producer task. A task is a set of program instructions that may be loaded into any type of memory of cache.”); and
a command processor configured in hardware using circuitry to:
schedule execution of the plurality of tasks by the processing elements (FIG. 1; paragraphs 0023 and 0055-0056: “The task management unit 234 receives tasks from the host interface unit 232, the work distribution unit 236, and/or the SMs 310 and schedules the tasks for execution by the SMs 310”), the plurality of tasks specified by a plurality of nodes in a task graph (FIG. 1; paragraphs 0023 and 0055-0056: “The task graph 128 specifies a workload as a directed graph. The nodes of the graph specify tasks, and the edges between the nodes specify dependency relationships between “producer tasks” and “consumer tasks.” Each dependency relationship may be a data dependency and/or an execution dependency (i.e., the producer task “happens before” the consumer task”); and
wherein the first task depends on the second task (FIG. 1; paragraphs 0023 and 0055-0056: “The task graph 128 specifies a workload as a directed graph. The nodes of the graph specify tasks, and the edges between the nodes specify dependency relationships between “producer tasks” and “consumer tasks.” Each dependency relationship may be a data dependency and/or an execution dependency (i.e., the producer task “happens before” the consumer task”).
Hirota does not explicitly disclose initiate a data transfer of aggregated data by a first task of a plurality of tasks to a respective processing element of the processing elements, the aggregated data generated from the first task and a second task of the plurality of tasks.
Liu further discloses initiate a data transfer of aggregated data by a first task of a plurality of tasks to a respective processing element of the processing elements (FIGs 1, and 10; paragraphs 0052-0053 and 0082: “Recurse minimizes network traffic for operations that need partial results. For example, where a programmer needs to identify the top 10 revenue producing customers, each node computes the local top 10 customers and forwards the results (e.g., partial results) to neighbouring nodes that in turn merge the partial results with the local result of the receiving node to produce the top 10. Each node only passes the top 10 records to particular neighbouring nodes, rather than passing every record of each node to a single node performing the reduce operation. Accordingly, the recurse operator avoids large bandwidth requirements and undesired network traffic, and provides higher computational performance” [Wingdings font/0xE0] recursively operation [Wingdings font/0xE0] a node forwarding the combined results (its own result and a neighbouring result) to a next node), the aggregated data generated from the first task and a second task of the plurality of tasks (FIGs 1, and 10; paragraphs 0052-0053 and 0082: “Recurse minimizes network traffic for operations that need partial results. For example, where a programmer needs to identify the top 10 revenue producing customers, each node computes the local top 10 customers and forwards the results (e.g., partial results) to neighbouring nodes that in turn merge the partial results with the local result of the receiving node to produce the top 10. Each node only passes the top 10 records to particular neighbouring nodes, rather than passing every record of each node to a single node performing the reduce operation. Accordingly, the recurse operator avoids large bandwidth requirements and undesired network traffic, and provides higher computational performance” [Wingdings font/0xE0] (a local result and the neighbouring node result).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Liu into Hirota’s teaching because it would provide for the purpose of minimizing the amounts of data transmitted to multiple processors to perform parallel processing computations (Liu, paragraph 0011).
Claim 15-16 is rejected under 35 U.S.C. 103 as being unpatentable over Hirota in view of Liu, as applied to claim 14, and further in view of Fowler.
As per claim 15, Hirota does not explicitly disclose wherein the command processor is configured to initiate the data transfer based on a counter.
Fowler further discloses wherein the command processor is configured to initiate the data transfer based on a counter (paragraph 0053: “incrementing the counter when a new processing thread is initiated for the transaction at the processing element; and decrementing the counter when a processing thread for the transaction completes; wherein processing result information collected for a plurality of threads associated with the transaction is preferably transmitted to the transaction manager when the counter is decremented to a value (e.g. zero) indicating that no threads remain executing for the transaction.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Fowler into Hirota’s teaching and Liu’s teaching because it would provide for the purpose of The multiple messages (and associated processing) preferably relate to the same distributed transaction. Thus, processing results for a particular transaction resulting from multiple calls to the processing element as part of that transaction may be grouped (Fowler, paragraph 0053).
As per claim 16, Hirota discloses wherein the counter includes a value based on a number of data dependencies identified for the first task in the task graph (FIG. 4; paragraphs 0059, 0062 and 0067-0069: “The dependency count 442 specifies the number of dependencies that the task associated with the task descriptor 430 has on producer tasks. The dependency count 442 for a join task is therefore at least two. By contrast, if the dependency count 422 for a task is one, then the task is dependent upon one other task. The current count 444 specifies the number of dependencies of the task that have not yet been met. The self-reset flag 446 triggers the dependency/prefetch unit 410 to automatically copy the dependency count 442 to the current count 444 when the task-related activities for the task have completed” [Wingdings font/0xE0] both dependency count and current count are based on the number of dependencies that the task associated with the task descriptor has on producer task).
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hirota in view of Liu, as applied to claim 14, and further in view of Vasiljevic.
As per claim 18, Hirota does not explicitly disclose a data transfer aggregation buffer configured to store the aggregated data.
Vasiljevic further discloses a data transfer aggregation buffer configured to store the aggregated data (FIGs. 2 and 5; paragraphs 0052, 0054, 0059, 0061 and 0068: buffers/streams to store a combined data (aggregated data)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Vasiljevic into Hirota’s teaching and Liu’s teaching because it would provide for the purpose of utilizing a network overlay layer and network overlay graph to efficiently execute an application data flow graph (Vasiljevic, paragraph 0007).
As per claim 19, Hirota does not explicitly disclose wherein the data transfer aggregation buffer is associated with a respective processing element of the processing elements that executes the first task.
Vasiljevic further discloses wherein the data transfer aggregation buffer is associated with a respective processing element of the processing elements that executes the first task (FIGs. 2 and 5; paragraphs 0052, 0054, 0059, 0061 and 0068: buffers/streams to store a combined data (aggregated data) produced by multiple threads).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Vasiljevic into Hirota’s teaching and Liu’s teaching because it would provide for the purpose of utilizing a network overlay layer and network overlay graph to efficiently execute an application data flow graph (Vasiljevic, paragraph 0007).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Hirota in view of Flower and Westendorp, as applied to claim 1, and further in view of US 2019/0340034 to Saballus et al. (hereafter “Saballus”).
As per claim 22, Hirota does not explicitly disclose wherein the command processor is configured to adjust the value of the counter responsive to dispatching a respective task of the plurality of tasks by a respective processing element of the processing elements.
Saballus further discloses wherein the command processor is configured to adjust the value of the counter responsive to dispatching a respective task of the plurality of tasks by a respective processing element of the processing elements (paragraphs 0042 and 0058).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Saballus into Hirota’s teaching, Fowler’s teaching, and Westendorp’s teaching because it would provide for the purpose of Jobs may be processed by a task for example if a counter in the data structure indicates that task is released for processing (Saballus, paragraph 0042).
Response to Arguments
Applicants’ arguments have been considered but are moot in view of the new ground(s) of rejection. Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action.
Applicant's arguments filed on 07/2026 have been fully considered but they are not persuasive for the following reasons:
It appears that the applicants argue that the overlay graph disclosed by Vasiljevic is not a task graph. Further more, the applicants argue “the nodes in Vasiljevic’s overlay graph are data routing nodes that do not modify or process the data …” (remarks, page 9)
The Examiner respectfully disagrees for following reasons.
Vasiljevic paragraphs 0027, 0028, and 0032 state:
[0027] FIG. 2 is a high-level block diagram 200 to illustrate the compilation of a network overlay graph 203 to execute an application data flow graph 202 for a network of computational nodes. Block diagram 200 illustrates an example of an application code 201 that describes a portion of a complex computation to be executed by the network of computational nodes. In this example, the illustrated application code 201 includes “concatenate” functions for explicative purposes, but the application code is to be understood as the source code description of the complex computation, written for example in human-readable format, and can include any definition, variables, functions, etc. to describe and allow for the execution of the complex computation. Step 210 represents the compilation of an application data flow graph 202 from the application code 201. Application data flow graph 202 can be compiled to execute the instructions in the application code 201. In the illustrated example, A1, A2, A3, B1, B2 and B3 represent nodes of the application data flow graph where the data is ultimately being produced (or injected into the graph) and/or consumed (or withdrawn from the graph). In the specific example of FIG. 2, A1, A2 and A3 are source nodes and B1, B2 and B3 are destination nodes, because data is flowing from A to B. The nodes can be associated with computational nodes of the network.
[0028] In embodiments where the computational nodes are cores in a multicore processor, the nodes of the application data flow graph can be associated with different cores. The association can be a product of the compilation process for a particular complex computation (e.g., node “A1” is associated with “core #5” because the data for node “A1” is physically stored on the memory of core #5). In this way, data from nodes A1 to B1 can be data produced by a source core associated with A1 to be consumed by a destination core associated with B1. In specific embodiments of the invention, the application data flow graph can be compiled for implementation within a single computational node and be related to local operations such as local transfers of data between different modules within the computational node. In those embodiments, the endpoints can be located within the same computational node.
[0032] Step 220 can be carried out by a compiler working in association with the computational nodes. The compiler can be a software module instantiated by a higher-level controller. The physical location of the data associated with the nodes of the application data flow graph can be used as an input in the compilation of the overlay graph 203. Additionally, the functions in the application code 201 and/or edges of the application data flow graph 202 that define the data flow can also be used to generate the graph. During the compilation of the overlay graph 203, the application code 201 and/or application data flow graph 202 can be parsed so that a representation of the application code/application data flow graph can be generated in the form of an overlay graph. In other words, the application code/application data flow graph can be “translated” into an overlay graph representation.
Accordingly, the overlay graph compiled/generated from the application code/application data flow graph is considered a task graph including a plurality computational node A1-N and B1-N associated with computational nodes in the network.
Therefore, Vasiljevic further discloses the node is a transfer node (FIG. 2; paragraphs 0030-0033: “overlay graph 203 includes intermediate nodes that guide the data flow, that are neither present in application data flow graph 202 nor represented by variables or operands (or otherwise described) in application code 201. The intermediate nodes in overlay graph 203 can be assigned to computational nodes in the network of computational nodes” [Wingdings font/0xE0] adding an intermediate node 230 which guide the data flow (a transfer node as claimed));
the data transfer node inserted within the task graph as a node of the task graph alongside the plurality of computation nodes (FIG. 2; paragraphs 0030-0033: “The intermediate nodes in overlay graph 203 can be assigned to computational nodes in the network of computational nodes.” [Wingdings font/0xE0] the intermediate nodes inserted within the graph alongside with computational nodes (a task graph as claimed)), and
the data transfer node configured to cause a data transfer operation using data aggregated from a plurality of tasks associated with the plurality of computation nodes (FIG. 2; paragraphs 0030-0033: “In the overlay graph, the intermediate nodes can direct the data flow by, for example, grouping requests and then multicasting the combined data to other nodes.” [Wingdings font/0xE0] node 230 combining data from A1-A3 [Wingdings font/0xE0] transferring combined data to B1-B3 in the overlay graph 203).
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication should be directed to examiner Tuan Dao, whose telephone/fax numbers are (571) 270 3387 and (571) 270 4387, respectively. The examiner can normally be reached on every Monday-Thursday and the second Friday of the bi-week from 7:30AM to 5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Pierre Vital, can be reached at telephone number (571) 272 4215.
The fax phone number for the organization where this application or proceeding is assigned is (571) 273 8300.
Any inquiry of a general nature of relating to the status of this application or proceeding should be directed to the TC 2100 Group receptionist whose telephone number is (571) 272 2100.
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/TUAN C DAO/ Primary Examiner, Art Unit 2198
