DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Request for Continued Examination
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 04/03/2026 has been entered.
Response to Arguments
4. Applicant’s argument filed on 04/03/2025 with respect claims 1-20 have been fully considered but they are not persuasive.
The applicant contends that the office action fails to teach or suggest the limitation of "the controller transitions from the recovery state to a loopback state included in the LTSSM, based on the first symbol including the lane number and the loopback bit being set to an active logic state, for both of the two consecutive received sequences." The applicant indicates Bisson is silent about transition into loopback state based on the first symbol including the lane number.
First, Examiner directs the applicant’s attention that during examination, a claim must be given its broadest reasonable interpretation (BRI) consistent with the specification as it would be interpreted by one of ordinary skill in the art (MPEP 2111. Therefore, Examiner respectfully disagrees and asserts that the reference of Bisson et al. (US 7,136,953 B1) in column 5 lines 58-67 & column 6, lines 1-3, column 8, lines 1-15, 50-67, column 9, lines 1-18, and column 10, lines 6-26, and Figs. 5 &12 teaches such limitation. For example, referring to arrows 480 and 485, the renegotiation process uses one or more additional states of the link state machine to access the configuration state 420 from operational state 425. A recovery state 430 is sometimes included in a link state machine to permit a bus to recover an attribute of the bus. In one embodiment, the renegotiation process begins in the normal operational state 425. One of the interfaces generates a training sequence that causes both interfaces to enter recovery state 430. From recovery state 430 the interfaces then enter configuration state 420 and re-negotiate link width using any constraints on link width imposed by the initiating user interface. FIG. 5 illustrates a state machine diagram for an alternate embodiment. Referring to arrows 480, 490, and 495, in one embodiment the initiating interface generates training messages that cause a transition to the Recovery state 430. From the recovery state 430 the state machines enter a Loopback state 435. Loopback states are sometimes included in bus interfaces to perform diagnostics of individual components. In this embodiment of the present invention, the Detect state 410 is entered from the Loopback state 435. Thus, the Reset state 405 is avoided. Moreover, as described below in more detail, in some embodiments, the interactions of the state machines may be adapted to eliminate some of the sub-states of the detect state. See column 5 lines 58-67 & column 6, lines1-3. FIG. 9 is a block diagram illustrating a sub-state machine for implementing a recovery state of a PCI Express.TM. LTSSM. The recovery state allows a configured link to re-establish bit lock, symbol lock, and lane-to-lane de-skew. In the recovery state the transmitter and receivers are sending and receiving data using the configured link and lane number as well as the previously negotiated data rate. The recovery sub-state machine includes a Recovery.Rcvrlock state 905 that sends ordered training sets to re-establish bit and symbol lock, a Recovery.RcvrCfg state 910 to re-establish lane-to-lane deskew and re-confirm the lane ordering assignment, and a Recovery.Idle state 915 that permits access to other states, based upon directions or other conditions. The PCI Express.TM. specification defines a protocol of training sets for each recovery sub-state. See column 8, lines 1-15.The interface compares 1110 RNCTRL.Maxwidth to the value of the LinkStat.Linkwidth, the currently negotiated bus width recorded in a link status register. If LinkState.Linkwidth, M, is greater than RNCTRL.Maxwidth, N, (e.g., N<M), it corresponds to a determination that the bus width can be reduced to save power. The endpoint device LTSSM then enters 1115 the recovery state. It sends out training sets TS1 and TS2 according to the current link and lane numbers as specified by the PCI Express.TM. for the Recovery.Rcvrlock and Recovery.Rcvrcfg states of the recovery sub-state machine. As a result the upstream device (e.g., the root complex) is driven 1120 into the recovery state upon detecting the TS1/TS2 training sets sent by the downstream device. The link number and lane number fields in the TS1/TS2 remain the same as for previously negotiated values during Recovery.Rcvrlock and Recovery.Rcvrcfg. Since the link number and lane number fields are unchanged, the Recover.RcvrLock and Recovery.RcvrCfg sub-states may be completed comparatively quickly, e.g., around 32 TS1/TS2 periods, or 512 Symbol times. This results in both ends of the link being driven into the Recovery.Idle sub-state at the end of recovery. At the recovery.idle sub-state, instead of placing the link into a locally idle state by sending null symbols, the endpoint device sends out 1125 TS1 ordered sets on all configured lanes with the link number the same as the original value. The lane number field of the TS1 ordered sets is assigned the value of "PAD". The endpoint device enters the configuration sub-state Configuration.Linkwidth.Start The upstream component is driven 1130 into the configuration state by receiving TS1 ordered sets with lane number being "PAD". In one embodiment, two consecutive TS1 ordered sets with lane number field being "PAD" on the Recovery.Idle state causes the upstream component to enter the Configuration.Linkwidth.Start sub-state. See column 8, lines 50-67 & column 9, lines 1-18.In response to the TS1/TS2 ordered sets, the upstream device is driven 1220 into the Recovery state. Consequently, both ends of the link are driven into the Recovery.Idle sub-state of the recovery state after Recovery.RcvrLock and Recovery.RcvrCfg. At the Recovery.Idle sub-state, the endpoint device sends out 1230 TS1 ordered sets on all configured lanes with the loopback bit in the training control field asserted. The endpoint device LTSSM enters the Loopback.Entry sub-state of the loopback state as the loopback master. The upstream component is driven 1240 into the Loopback.Active sub-state as a loopback slave after receiving TS1 with loopback asserted while it is in the Recovery.Idle state. The upstream component then starts looping back the TS1 ordered sets with the loopback bit asserted that are received from the endpoint component. In response to the endpoint component receiving the TS1 looped back from the upstream device, it skips the Loopback.Active state and enters 1250 Loopback.Exit immediately. This drives the upstream device into the Loopback.Exit state as well. See column 10, lines 6-26. As been described above, it’s clear that the initiating interface generates transitions [training sequences TS1/TS2 including lane number] from the recovery state 430 to a loopback state 435 to perform diagnostics of individual components for two consecutive received sequences [TS1/TS2] according to the lane numbers." Therefore, Bisson teaches the controller transitions from the recovery state to a loopback state included in the LTSSM, based on the first symbol including the lane number and the loopback bit being set to an active logic state, for both of the two consecutive received sequences. Emphasis added. Also, see Figs. 5, 11B, and 12A are printed below for your convenience.
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Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) (1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-3, 13-15, and 20 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Bisson et al. (US 7,136,953 B1) "herein after as Bisson."
As per claims 1, 13, and 20:
Bisson teaches or discloses a device comprising (see Fig. 1): a port connected to a link comprising one or more lanes to support communication between the device and another device (see column 3, lines 2-5, herein Referring to FIG. 1, system 100 includes two components 105 and 110 that are communicatively coupled by a data bus 115 comprised of a plurality of serial data lanes 120 and bus interfaces 130 and 135, and Fig. 1) ; and a controller configured to control the link based on a link training and status state machine (LTSSM) (see column 3, lines 25-28, herein Each bus interface 130 and 135 includes its own local link state machine 140 for initializing a common data link between the components in which one or more of the data lanes are associated to form a common data link, and Fig. 1), wherein: the port receives two consecutive received sequences, each defined as a training sequence, through the link in a recovery state included in the LTSSM (see column 8, 26-28, herein In a PCI Express.TM. implementation, the two LTSSMs of the bus interfaces interact through TS1 and TS2 ordered training sets that are exchanged between the LTSSMs, and lines 55-58, herein the endpoint device LTSSM then enters 1115 the recovery state. It sends out training sets TS1 and TS2 according to the current link and lane numbers as specified by the PCI Express), the training sequence comprising a first symbol including a lane number or a special symbol indicating an unassigned lane number (see column 4, lines 65-67 include creating training sequence messages that indicate to the other interface that certain lanes are not to be used, even though they are operable lanes (e.g., by sending a signal indicating that one or more lanes are disabled), and a second symbol including a loopback bit (see column 10, lines 1-5, herein the endpoint device LTSSM enters 1210 the recovery state and sends out TSI/TS2 training sets according to the current link and lane numbers during the Recovery. RcvrLock and Recovery. RcvrCfg sub-states. Additionally, the loopback bit in the training control field of the TS1/TS2 training sets is asserted), and the controller transitions from the recovery state to a loopback state included in the LTSSM, based on the first symbol including the lane number and the loopback bit being set to an active logic state, for both of the two consecutive received sequences (see column 5, lines 60-62, herein generates training messages that cause a transition to the Recovery state 430. From the recovery state 430 the state machines enter a Loopback state 435, See column 10, lines 1-15, herein the endpoint device LTSSM enters 1210 the recovery state and sends out TSI/TS2 training sets according to the current link and lane numbers during the Recovery.RcvrLock and Recovery.RcvrCfg sub-states. Additionally, the loopback bit in the training control field of the TS1/TS2 training sets is asserted. In response to the TS1/TS2 ordered sets, the upstream device is driven 1220 into the Recovery state. Consequently, both ends of the link are driven into the Recovery.Idle sub-state of the recovery state after Recovery.RcvrLock and Recovery.RcvrCfg. At the Recovery.Idle sub-state, the endpoint device sends out 1230 TS1 ordered sets on all configured lanes with the loopback bit in the training control field asserted. The endpoint device LTSSM enters the Loopback.Entry sub-state of the loopback state as the loopback master; and Figs. 5, 11B, 12A).
As per claims 2 and 14:
Bisson teaches that wherein: the controller transitions from the recovery state to a configuration state included in the LTSSM based on the first symbol including the special symbol (see column 7, lines 8-11, herein PCI Express.TM. also includes special symbols that are distinct from data symbols. These include special symbols used for link management. The symbol "PAD" is used in framing and link width and lane ordering negotiations).
As per claims 3 and 15:
Bisson teaches that wherein: the port receives two different received sequences, each defined as the training sequence, through the link in the configuration state, and the controller transitions from the configuration state to the loopback state for both of the two different received sequences based on the loopback bit being set to the active logic state (see column 11-15, herein At the Recovery.Idle sub-state, the endpoint device sends out 1230 TS1 ordered sets on all configured lanes with the loopback bit in the training control field asserted. The endpoint device LTSSM enters the Loopback.Entry sub-state of the loopback state as the loopback master, and Figs. 5 &12).
Allowable Subject Matter
6. Claims 4, 7, 12, 16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Dependent claims 5, 6, 8-11, and 17-18 depend from on claims 4 and 16 respectively and inherently include limitations therein and therefore are allowed as well.
Examiner Notes
7. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
8. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN ALSHACK/
Patent Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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