DETAILED ACTION
This action is in response to the claims filed 11/30/2023 for Application number 18/525,027. Claim 15, 23 and 44 has been amended, claims 47-49 are new and claims 16-22 and 24-43 are canceled. Thus, claims 1-15, 23, and 44-47 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 03/20/2024 and 11/12/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
a first signal output module configured to generate… in claim 1.
a signal acquisition module configured to acquire and process… in claim 1.
a control module configured to output… in claim 1
a waveform output unit configured to generate… in claim 3
a DAC united and configured to receive… in claim 3
a waveform synthesizing unit and configured to process… in claim 4
an ADC unit configured to acquire and process… in claim 7
a data processing unit and configured to receive and process… in claim 7
a data distributor configured to receive and process in claim 8.
a plurality of operators configured to receive and process… in claim 8
a task management module which is configured to receive… in claim 12
a second signal output module which is configured to output… in claim 13
a qubit measurement determining module configured to determine…in claim 15.
a quantum computing task receiving module configured to receive…in claim 23
a quantum computing task analyzing module configured to analyze… in claim 23
a measurement determining module configured to determine…in claim 23
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-15, 23, and 44-47 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. ("QubiC: An open source FPGA-based control and measurement system for superconducting quantum information processors", hereinafter "Xu") in view of Heinsoo et al. ("Rapid high-fidelity multiplexed readout of superconducting qubits", hereinafter, "Heinsoo") and further in view of Lin et al. ("High Performance and Scalable AWG for Superconducting Quantum Computer", hereinafter "Lin").
Regarding claim 1, Xu teaches A quantum measurement and control system (Abstract), comprising:
a first signal output module (N DACs, Figure 2), configured to generate waveforms to be processed corresponding to qubits connected with a qubit measurement bus (“The single-tone experiment involves measuring all the readout resonator frequencies on the readout bus.” [pg. 4, bottom right col]) based on a preset time sequence (“The hardware module shifts frequencies between the RF and IF, while the gateware DSP module is responsible for the generation and processing of the data stream between the IF signal and the baseband signal…. A qubit algorithm typically consists of a series of qubit gates and measurements, which are eventually realized by the sequence of RF pulses.” [pg. 3, §B.1-B.2])
a signal acquisition module (See Figure 2, “ADC”), configured to acquire and process a qubit reading feedback signal output by the qubit measurement bus based on the preset time sequence (“When the processing module is used in the down conversion mode, it receives the qubit signals from the ADC, and recovers the baseband I and Q components” [pg. 3, bottom right col]), to obtain quantum state information of each qubit which needs to be measured (“The qubit response is acquired from the FPGA (“Acquire”) and processed by QubiC software to discriminate the state (“Process”)” [pg. 6, left col, ¶2]); and
However fails to explicitly teach and process the waveforms to be processed into one synthesized waveform, and output a qubit reading signal corresponding to the synthesized waveform to the qubit measurement bus; wherein a waveform to be processed for a qubit comprises a measurement waveform when the qubit needs to be measured or an empty waveform when the qubit does not need to be measured;
a control module, configured to output a synchronous trigger signal as a start time of the preset time sequence to the first signal output module and the signal acquisition module.
Heinsoo teaches and process the waveforms to be processed into one synthesized waveform, and output a qubit reading signal corresponding to the synthesized waveform to the qubit measurement bus (“Multi frequency pulses used for readout are synthesized with a digital signal processing (DSP) unit, then upconverted to microwave frequencies by analog mixing with a local oscillator(LO)field, and applied to the input port of the feedline after several stages of attenuation. The readout signal emitted from the sample is amplified, downconverted and digitized with an analog-to digital (ADC) converter and further processed with the same DSP unit used for pulse synthesis.” [pg. 2, Figure 1 caption]); wherein a waveform to be processed for a qubit comprises a measurement waveform when the qubit needs to be measured or an empty waveform when the qubit does not need to be measured; (“Extensions of dispersive readout to multiple qubits can be realized by either coupling multiple qubits to a single readout resonator [23, 24] or by probing several readout resonators coupled to a single feedline with a multi-frequency pulse [9]. The latter approach allows for selective readout of any subset of the qubits by choosing the corresponding frequency components in the measurement pulse.” [pg. 1, left col, bottom para; note: The claim recites “or” thus under BRI the examiner is only required to map to one of the corresponding conditions.])
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Xu’s teachings in order to synthesize waveforms as taught by Heinsoo. One would have been motivated to make this modification in order to present a qubit readout scheme that would be particularly useful for the selective readout of individual qubits in multi-qubit quantum processors. [Abstract, Heinsoo]
However Xu/Heinsoo fails to explicitly teach a control module, configured to output a synchronous trigger signal as a start time of the preset time sequence to the first signal output module and the signal acquisition module
Lin teaches a control module, configured to output a synchronous trigger signal as a start time of the preset time sequence to the first signal output module and the signal acquisition module (“Another external input trigger which is synchronized to the same clock source can provide accurate output control. An extensible AWG array may be easily achieved by integration of multiple AWGs with a dedicated synchronize control module.” [pg. 2, right col, ¶1])
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Xu’s/Heinsoo’s teachings in order to implement the synchronous input trigger signal as taught by Lin. One would have been motivated to make this modification in order to provide accurate output control and integrate multiple AWGs with a dedicated control module. [pg. 2, right col, ¶2, Lin]
Regarding claim 2, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 1, Xu teaches wherein the first signal output module is further configured to update the waveforms to be processed for the qubits according to a first preset time (“The host computer interface needs to be designed to accommodate both types of experiments by way of parametric waveform generation… All commands repeat at a defined period until the acc buffer is full. The acc buffer can be cleared by the software after reading the data.” [pg. 4, left col, Host Interface]); the first preset time is determined according to a working clock frequency of the first signal output module. (“The DSP implements basic qubit control and measure ment functions and it is designed to be independent of the low-level FPGA/ADC/DAC selection. The DSP runs in a single clock domain and the HOI and BSP handle the clock domain crossing for the required registers, and also buffers the transmitted and received data.” [pg. 3, B. FPGA gateware, 2nd bullet])
Regarding claim 3, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 1, wherein the first signal output module comprises:
Xu teaches a waveform output unit, configured to generate the waveforms to be processed corresponding to the qubits connected with the qubit measurement bus based on the preset time sequence (“The host computer interface needs to be designed to accommodate both types of experiments by way of parametric waveform generation.” pg. 4, left col, Host Interface]) and
a DAC unit, connected with the waveform output unit, and configured to receive the synthesized waveform and output the qubit reading signal corresponding to the synthesized waveform to the qubit measurement bus (“The calculated result then feeds into any DAC through an m-to-n switch. Signals from multiple processing elements can be sent to the same DAC and added together. For each pulse to be generated, the software needs to specify the processing element, and the DAC to be used for the destination.” [pg. 3, right col, ¶2]).
Heinsoo teaches and process the waveforms to be processed into the synthesized waveform; [pg. 2, Figure 1 caption])
Same motivation to combine the teachings of Xu/Heinsoo/Lin as claim 1.
Regarding claim 4, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 3, Xu teaches wherein the waveform output unit comprises: a plurality of waveform generating units, any one of which is configured to generate a waveform to be processed for a qubit (See Figure 1. QubiC prototype hardware); and
Heinsoo teaches a waveform synthesizing unit, connected with the plurality of waveform generating units and configured to process the waveforms to be processed output by the plurality of waveform generating units into the synthesized waveform. (“Multi frequency pulses used for readout are synthesized with a digital signal processing (DSP) unit, then upconverted to microwave frequencies by analog mixing with a local oscillator(LO)field, and applied to the input port of the feedline after several stages of attenuation. The readout signal emitted from the sample is amplified, downconverted and digitized with an analog-to digital (ADC) converter and further processed with the same DSP unit used for pulse synthesis.” [pg. 2, Figure 1 caption])
Same motivation to combine the teachings of Xu/Heinsoo/Lin as claim 1.
Regarding claim 5, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 4, Xu teaches wherein the plurality of waveform generating units are configured to generate the waveforms to be processed for the qubits connected with the qubit measurement bus based on the preset time sequence and output the waveforms to be processed. (“The hardware module shifts frequencies between the RF and IF, while the gateware DSP module is responsible for the generation and processing of the data stream between the IF signal and the baseband signal…. A qubit algorithm typically consists of a series of qubit gates and measurements, which are eventually realized by the sequence of RF pulses.” [pg. 3, §B.1-B.2])
Regarding claim 6, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 3, Xu teaches wherein the DAC unit comprises at least one output channel, any one of which is configured to output one qubit reading signal to one qubit measurement bus on a quantum chip. (“The hardware configuration contains the sampling rate, the physical wiring diagram between the DACs and the qubits and the gateware register maps. This only needs to be updated when the quantum chip or the chip wiring changes.” [pg. left col, ¶2])
Regarding claim 7, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 1, Xu teaches wherein the signal acquisition module comprises:
an ADC unit, configured to acquire and process the qubit reading feedback signal output by the qubit measurement bus to obtain a first digital signal; wherein the first digital signal carries quantum state information of measured qubits connected with the qubit measurement bus (“The QubiC prototype hardware employs the heterodyne
technique to generate and detect RF signals. It includes three basic building modules: the FPGA/ADC(analog-to digital converter)/DAC(digital-to-analog converter) module to generate/detect the intermediate frequency (IF) signal” [pg. 2, left col, A. Electronics Hardware, ¶1; See further Figure 4 caption “digitizes the IF signal”]); and
a data processing unit, connected with the ADC unit and configured to receive and process the first digital signal based on the preset time sequence to obtain the quantum state information of the measured qubits. (“When the processing module is used in the down conversion mode, it receives the qubit signals from the ADC” [pg. 3, right col, ¶2])
Regarding claim 8, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 7, Xu teaches wherein the data processing unit comprises:
a data distributor, configured to receive and process the first digital signal to obtain a plurality of pieces of first data and output the plurality of pieces of first data; (“The digital modulation/demodulation between the baseband envelope and the IF data stream is realized by a module called the processing element. Processing elements can be configured to execute digital up or down conversions.” [pg. 3, left col, 1) Gateware DSP, ¶2]) wherein, the plurality of pieces of first data and a plurality of qubits connected with the qubit measurement bus are in one-to-one correspondence (See Figure 5. “Each point corresponds to a measurement result of a random quantum circuit”); and
a plurality of operators, connected with the data distributor, wherein each of the plurality of operators is configured to receive and process one of the plurality of pieces of first data and output quantum state information of one measured qubit. (“K down conversion processing elements can be assigned to process K-qubit readout data simultaneously through the same ADC pair.” [pg. 3, Fig. 2])
Regarding claim 9, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 7, Xu teaches wherein each of the operators is specifically configured to receive and process one of the plurality of pieces of first data based on the preset time sequence, and output the quantum state information of one measured qubit. (See Figure 2, “The processing elements are employed as the up or down converters in the digital domain… K down conversion processing elements can be assigned to process K-qubit readout data simultaneously through the same ADC pair”)
Regarding claim 10, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 7, Xu teaches wherein the ADC unit comprises at least one acquisition channel, any one of which is configured to acquire a qubit reading feedback signal output by a qubit measurement bus. (“…and 4 channels of high speed (1 GSPS) 16-bit ADCs” [pg. 2, bottom left col])
Regarding claim 11, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 1, Xu teaches wherein the preset time sequence is determined according to an execution time and a measurement time of a quantum computing task to be executed. (“Furthermore, QubiC can execute the RC protocol relatively quickly, as shown in Fig. 7. The total execution time grows linearly with the increase of the number of RC circuits or the number of two-qubit gates. The “Compile” and the “Transpile” account for the majority of the execution time, which are limited by the host computer performance. The major part of the QubiC execution time is the “Run”, while command writing is the most time-consuming task in the “Run”.” [pg. 6, right col, bottom para])
Regarding claim 12, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 11, wherein the quantum measurement and control system further comprises a task management module, which is configured to receive the execution time and measurement time of the quantum computing task to be executed and output the corresponding preset time sequence. (“The major part of the QubiC execution time is the “Run”, while command writing is the most time-consuming task in the “Run”. One can observe that the “Run” time increases linearly with the number of RC circuits and the number of two-qubit gates respectively, since the command depth also grows linearly. The speed of the “Run” portion is currently limited by the constraint that the load command only accepts 16k commands and takes ∼55 ms to execute.” [pg. 6, right col, bottom para])
Regarding claim 13, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 1, Xu teaches wherein the quantum measurement and control system further comprises a second signal output module, which is configured to output control signals to a plurality of qubits connected with the qubit measurement bus based on the preset time sequence, and wherein the control signals are configured to regulate the quantum state information of the qubits. (“The acq buffer serves as a live oscilloscope for the ADC/DLO/DAC raw data. M up conversion processing elements are switched to N DACs (second signal output module) with the dynamic mapping” [pg. 3, Figure 2])
Regarding claim 14, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 1, Xu teaches wherein the first signal output module and the signal acquisition module are located on a same board card. (See Figure 1, pg. 2)
Regarding claim 15, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 1, Xu teaches which is configured for measurement of qubits connected with at least one qubit measurement bus on a quantum chip (“This is a hardware dependent layer. The hardware configuration contains the sampling rate, the physical wiring diagram between the DACs and the qubits and the gateware register maps. This only needs to be updated when the quantum chip or the chip wiring changes” [pg. 8, left col, ¶2]); wherein the measurement of the qubits comprises applying a qubit reading signal to the qubits (“Writing to the command/envelope buffer to generate pulses, and reading from the acc/acq buffer to collect responses are the lowest level software interface provided by the FPGA gateware.” [pg. 4, left col, bottom para]), and acquiring from the qubits and processing a qubit reading feedback signal after a preset delay (“Quantum processor characterization begins with time alignment, which measures the latency for the readout signal and aligns it with the DLO.” [pg. 4, bottom right col]); the quantum measurement and control system further comprises:
a qubit measurement determining module, configured to determine first information on whether each of the qubits connected with the qubit measurement bus needs to be measured at a current time; (“In the current QubiC gateware, each pulse is defined by the pulse start time, the envelope information, and the carrier information… Trig t (24 bits) Pulse start time relative to the start of the whole sequence.” [pg. 4, left col, 2) Host Interface, ¶2])
Regarding claim 23, Xu/Heinsoo/Lin teaches The quantum measurement and control system according to claim 15, Xu teaches wherein the qubit measurement determining module comprises:
a quantum computing task receiving module, configured to receive a quantum computing task (“Furthermore, QubiC can execute the RC protocol relatively quickly, as shown in Fig. 7. The total execution time grows linearly with the increase of the number of RC circuits or the number of two-qubit gates. The “Compile” and the “Transpile” account for the majority of the execution time, which are limited by the host computer performance.” [pg. 6, bottom right col]); and
a quantum computing task analyzing module, configured to analyze the quantum computing task and determine a task execution time and a measurement time of a qubit (“The major part of the QubiC execution time is the “Run”, while command writing is the most time-consuming task in the “Run”. One can observe that the “Run” time increases linearly with the number of RC circuits and the number of two-qubit gates respectively, since the command depth also grows linearly. The speed of the “Run” portion is currently limited by the constraint that the load command only accepts 16k commands and takes ∼55 ms to execute.” [pg. 6, bottom right col]); and
a measurement determining module, configured to determine the first information on whether each of the qubits connected with the qubit measurement bus needs to be measured at the current time, based on the execution time and the measurement time. “In the current QubiC gateware, each pulse is defined by the pulse start time, the envelope information, and the carrier information… Trig t (24 bits) Pulse start time relative to the start of the whole sequence.” [pg. 4, left col, 2) Host Interface, ¶2])
Regarding claim 44, Xu/Heinsoo/Lin teaches A quantum computer comprising a quantum chip and the quantum measurement and control system according to claim 1; wherein, the quantum chip is provided with at least one group of qubits, each group of qubits is connected with one qubit measurement bus (“The quantum processor gate pulse specification contains two parts: the frequencies (readout resonator and qubit drive) that represent the specific properties of each qubit and the gates that drive interactions between the control system and the qubits.” [pg. 4, right col, ¶3]);
an input end of each qubit measurement bus is connected with the first signal output module, and an output end of each qubit measurement bus is connected with the signal acquisition module (See Figure 2, DAC x N and ADC).
Regarding claims 47-49, they are substantially similar to claim 44 respectively, and are rejected in the same manner, the same art, and reasoning applying.
Conclusion
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/MICHAEL H HOANG/PRIMARY EXAMINER, Art Unit 2122
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